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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654316086424100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/ptw.h | 10 +-- target/arm/helper.c | 194 +------------------------------------------- target/arm/ptw.c | 190 +++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 198 insertions(+), 196 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index d6e3fee152..d24b7c263a 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -33,14 +33,14 @@ simple_ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_id= x, int ap) return simple_ap_to_rw_prot_is_user(ap, regime_is_user(env, mmu_idx)); } =20 +bool m_is_ppb_region(CPUARMState *env, uint32_t address); +bool m_is_system_region(CPUARMState *env, uint32_t address); + void get_phys_addr_pmsav7_default(CPUARMState *env, ARMMMUIdx mmu_idx, int32_t address, int *prot); -bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi); +bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_= user); + bool get_phys_addr_pmsav8(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *txattrs, diff --git a/target/arm/helper.c b/target/arm/helper.c index 7dd54c1863..9cbf3422ec 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -11642,8 +11642,7 @@ do_fault: return true; } =20 -static bool pmsav7_use_background_region(ARMCPU *cpu, - ARMMMUIdx mmu_idx, bool is_user) +bool pmsav7_use_background_region(ARMCPU *cpu, ARMMMUIdx mmu_idx, bool is_= user) { /* Return true if we should use the default memory map as a * "background" region if there are no hits against any MPU regions. @@ -11662,14 +11661,14 @@ static bool pmsav7_use_background_region(ARMCPU *= cpu, } } =20 -static inline bool m_is_ppb_region(CPUARMState *env, uint32_t address) +bool m_is_ppb_region(CPUARMState *env, uint32_t address) { /* True if address is in the M profile PPB region 0xe0000000 - 0xe00ff= fff */ return arm_feature(env, ARM_FEATURE_M) && extract32(address, 20, 12) =3D=3D 0xe00; } =20 -static inline bool m_is_system_region(CPUARMState *env, uint32_t address) +bool m_is_system_region(CPUARMState *env, uint32_t address) { /* True if address is in the M profile system region * 0xe0000000 - 0xffffffff @@ -11677,193 +11676,6 @@ static inline bool m_is_system_region(CPUARMState= *env, uint32_t address) return arm_feature(env, ARM_FEATURE_M) && extract32(address, 29, 3) = =3D=3D 0x7; } =20 -bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - ARMCPU *cpu =3D env_archcpu(env); - int n; - bool is_user =3D regime_is_user(env, mmu_idx); - - *phys_ptr =3D address; - *page_size =3D TARGET_PAGE_SIZE; - *prot =3D 0; - - if (regime_translation_disabled(env, mmu_idx) || - m_is_ppb_region(env, address)) { - /* MPU disabled or M profile PPB access: use default memory map. - * The other case which uses the default memory map in the - * v7M ARM ARM pseudocode is exception vector reads from the vector - * table. In QEMU those accesses are done in arm_v7m_load_vector(), - * which always does a direct read using address_space_ldl(), rath= er - * than going via this function, so we don't need to check that he= re. - */ - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { /* MPU enabled */ - for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { - /* region search */ - uint32_t base =3D env->pmsav7.drbar[n]; - uint32_t rsize =3D extract32(env->pmsav7.drsr[n], 1, 5); - uint32_t rmask; - bool srdis =3D false; - - if (!(env->pmsav7.drsr[n] & 0x1)) { - continue; - } - - if (!rsize) { - qemu_log_mask(LOG_GUEST_ERROR, - "DRSR[%d]: Rsize field cannot be 0\n", n); - continue; - } - rsize++; - rmask =3D (1ull << rsize) - 1; - - if (base & rmask) { - qemu_log_mask(LOG_GUEST_ERROR, - "DRBAR[%d]: 0x%" PRIx32 " misaligned " - "to DRSR region size, mask =3D 0x%" PRIx32 "= \n", - n, base, rmask); - continue; - } - - if (address < base || address > base + rmask) { - /* - * Address not in this region. We must check whether the - * region covers addresses in the same page as our address. - * In that case we must not report a size that covers the - * whole page for a subsequent hit against a different MPU - * region or the background region, because it would resul= t in - * incorrect TLB hits for subsequent accesses to addresses= that - * are in this MPU region. - */ - if (ranges_overlap(base, rmask, - address & TARGET_PAGE_MASK, - TARGET_PAGE_SIZE)) { - *page_size =3D 1; - } - continue; - } - - /* Region matched */ - - if (rsize >=3D 8) { /* no subregions for regions < 256 bytes */ - int i, snd; - uint32_t srdis_mask; - - rsize -=3D 3; /* sub region size (power of 2) */ - snd =3D ((address - base) >> rsize) & 0x7; - srdis =3D extract32(env->pmsav7.drsr[n], snd + 8, 1); - - srdis_mask =3D srdis ? 0x3 : 0x0; - for (i =3D 2; i <=3D 8 && rsize < TARGET_PAGE_BITS; i *=3D= 2) { - /* This will check in groups of 2, 4 and then 8, wheth= er - * the subregion bits are consistent. rsize is increme= nted - * back up to give the region size, considering consis= tent - * adjacent subregions as one region. Stop testing if = rsize - * is already big enough for an entire QEMU page. - */ - int snd_rounded =3D snd & ~(i - 1); - uint32_t srdis_multi =3D extract32(env->pmsav7.drsr[n], - snd_rounded + 8, i); - if (srdis_mask ^ srdis_multi) { - break; - } - srdis_mask =3D (srdis_mask << i) | srdis_mask; - rsize++; - } - } - if (srdis) { - continue; - } - if (rsize < TARGET_PAGE_BITS) { - *page_size =3D 1 << rsize; - } - break; - } - - if (n =3D=3D -1) { /* no hits */ - if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { - /* background fault */ - fi->type =3D ARMFault_Background; - return true; - } - get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); - } else { /* a MPU hit! */ - uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); - uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); - - if (m_is_system_region(env, address)) { - /* System space is always execute never */ - xn =3D 1; - } - - if (is_user) { /* User mode AP bit decoding */ - switch (ap) { - case 0: - case 1: - case 5: - break; /* no access */ - case 3: - *prot |=3D PAGE_WRITE; - /* fall through */ - case 2: - case 6: - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - case 7: - /* for v7M, same as 6; for R profile a reserved value = */ - if (arm_feature(env, ARM_FEATURE_M)) { - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - } - /* fall through */ - default: - qemu_log_mask(LOG_GUEST_ERROR, - "DRACR[%d]: Bad value for AP bits: 0x%" - PRIx32 "\n", n, ap); - } - } else { /* Priv. mode AP bits decoding */ - switch (ap) { - case 0: - break; /* no access */ - case 1: - case 2: - case 3: - *prot |=3D PAGE_WRITE; - /* fall through */ - case 5: - case 6: - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - case 7: - /* for v7M, same as 6; for R profile a reserved value = */ - if (arm_feature(env, ARM_FEATURE_M)) { - *prot |=3D PAGE_READ | PAGE_EXEC; - break; - } - /* fall through */ - default: - qemu_log_mask(LOG_GUEST_ERROR, - "DRACR[%d]: Bad value for AP bits: 0x%" - PRIx32 "\n", n, ap); - } - } - - /* execute never */ - if (xn) { - *prot &=3D ~PAGE_EXEC; - } - } - } - - fi->type =3D ARMFault_Permission; - fi->level =3D 1; - return !(*prot & (1 << access_type)); -} - static bool v8m_is_sau_exempt(CPUARMState *env, uint32_t address, MMUAccessType access_type) { diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 74650c6c52..27715dbfa8 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -8,6 +8,7 @@ =20 #include "qemu/osdep.h" #include "qemu/log.h" +#include "qemu/range.h" #include "cpu.h" #include "internals.h" #include "ptw.h" @@ -415,6 +416,195 @@ void get_phys_addr_pmsav7_default(CPUARMState *env, } } =20 +static bool get_phys_addr_pmsav7(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_= idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + ARMCPU *cpu =3D env_archcpu(env); + int n; + bool is_user =3D regime_is_user(env, mmu_idx); + + *phys_ptr =3D address; + *page_size =3D TARGET_PAGE_SIZE; + *prot =3D 0; + + if (regime_translation_disabled(env, mmu_idx) || + m_is_ppb_region(env, address)) { + /* + * MPU disabled or M profile PPB access: use default memory map. + * The other case which uses the default memory map in the + * v7M ARM ARM pseudocode is exception vector reads from the vector + * table. In QEMU those accesses are done in arm_v7m_load_vector(), + * which always does a direct read using address_space_ldl(), rath= er + * than going via this function, so we don't need to check that he= re. + */ + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { /* MPU enabled */ + for (n =3D (int)cpu->pmsav7_dregion - 1; n >=3D 0; n--) { + /* region search */ + uint32_t base =3D env->pmsav7.drbar[n]; + uint32_t rsize =3D extract32(env->pmsav7.drsr[n], 1, 5); + uint32_t rmask; + bool srdis =3D false; + + if (!(env->pmsav7.drsr[n] & 0x1)) { + continue; + } + + if (!rsize) { + qemu_log_mask(LOG_GUEST_ERROR, + "DRSR[%d]: Rsize field cannot be 0\n", n); + continue; + } + rsize++; + rmask =3D (1ull << rsize) - 1; + + if (base & rmask) { + qemu_log_mask(LOG_GUEST_ERROR, + "DRBAR[%d]: 0x%" PRIx32 " misaligned " + "to DRSR region size, mask =3D 0x%" PRIx32 "= \n", + n, base, rmask); + continue; + } + + if (address < base || address > base + rmask) { + /* + * Address not in this region. We must check whether the + * region covers addresses in the same page as our address. + * In that case we must not report a size that covers the + * whole page for a subsequent hit against a different MPU + * region or the background region, because it would resul= t in + * incorrect TLB hits for subsequent accesses to addresses= that + * are in this MPU region. + */ + if (ranges_overlap(base, rmask, + address & TARGET_PAGE_MASK, + TARGET_PAGE_SIZE)) { + *page_size =3D 1; + } + continue; + } + + /* Region matched */ + + if (rsize >=3D 8) { /* no subregions for regions < 256 bytes */ + int i, snd; + uint32_t srdis_mask; + + rsize -=3D 3; /* sub region size (power of 2) */ + snd =3D ((address - base) >> rsize) & 0x7; + srdis =3D extract32(env->pmsav7.drsr[n], snd + 8, 1); + + srdis_mask =3D srdis ? 0x3 : 0x0; + for (i =3D 2; i <=3D 8 && rsize < TARGET_PAGE_BITS; i *=3D= 2) { + /* + * This will check in groups of 2, 4 and then 8, wheth= er + * the subregion bits are consistent. rsize is increme= nted + * back up to give the region size, considering consis= tent + * adjacent subregions as one region. Stop testing if = rsize + * is already big enough for an entire QEMU page. + */ + int snd_rounded =3D snd & ~(i - 1); + uint32_t srdis_multi =3D extract32(env->pmsav7.drsr[n], + snd_rounded + 8, i); + if (srdis_mask ^ srdis_multi) { + break; + } + srdis_mask =3D (srdis_mask << i) | srdis_mask; + rsize++; + } + } + if (srdis) { + continue; + } + if (rsize < TARGET_PAGE_BITS) { + *page_size =3D 1 << rsize; + } + break; + } + + if (n =3D=3D -1) { /* no hits */ + if (!pmsav7_use_background_region(cpu, mmu_idx, is_user)) { + /* background fault */ + fi->type =3D ARMFault_Background; + return true; + } + get_phys_addr_pmsav7_default(env, mmu_idx, address, prot); + } else { /* a MPU hit! */ + uint32_t ap =3D extract32(env->pmsav7.dracr[n], 8, 3); + uint32_t xn =3D extract32(env->pmsav7.dracr[n], 12, 1); + + if (m_is_system_region(env, address)) { + /* System space is always execute never */ + xn =3D 1; + } + + if (is_user) { /* User mode AP bit decoding */ + switch (ap) { + case 0: + case 1: + case 5: + break; /* no access */ + case 3: + *prot |=3D PAGE_WRITE; + /* fall through */ + case 2: + case 6: + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + case 7: + /* for v7M, same as 6; for R profile a reserved value = */ + if (arm_feature(env, ARM_FEATURE_M)) { + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + } + /* fall through */ + default: + qemu_log_mask(LOG_GUEST_ERROR, + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); + } + } else { /* Priv. mode AP bits decoding */ + switch (ap) { + case 0: + break; /* no access */ + case 1: + case 2: + case 3: + *prot |=3D PAGE_WRITE; + /* fall through */ + case 5: + case 6: + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + case 7: + /* for v7M, same as 6; for R profile a reserved value = */ + if (arm_feature(env, ARM_FEATURE_M)) { + *prot |=3D PAGE_READ | PAGE_EXEC; + break; + } + /* fall through */ + default: + qemu_log_mask(LOG_GUEST_ERROR, + "DRACR[%d]: Bad value for AP bits: 0x%" + PRIx32 "\n", n, ap); + } + } + + /* execute never */ + if (xn) { + *prot &=3D ~PAGE_EXEC; + } + } + } + + fi->type =3D ARMFault_Permission; + fi->level =3D 1; + return !(*prot & (1 << access_type)); +} + /** * get_phys_addr - get the physical address for this virtual address * --=20 2.34.1