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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654315744358100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/ptw.h | 15 +++-- target/arm/helper.c | 137 +++----------------------------------------- target/arm/ptw.c | 123 +++++++++++++++++++++++++++++++++++++++ 3 files changed, 140 insertions(+), 135 deletions(-) diff --git a/target/arm/ptw.h b/target/arm/ptw.h index e2023ae750..2dbd97b8cb 100644 --- a/target/arm/ptw.h +++ b/target/arm/ptw.h @@ -11,16 +11,21 @@ =20 #ifndef CONFIG_USER_ONLY =20 +uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); +uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi); + bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu_idx); bool regime_translation_disabled(CPUARMState *env, ARMMMUIdx mmu_idx); ARMCacheAttrs combine_cacheattrs(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2); =20 -bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi); +bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t *table, uint32_t address); +int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, + int ap, int domain_prot); + bool get_phys_addr_pmsav5(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, int *prot, diff --git a/target/arm/helper.c b/target/arm/helper.c index 7015ce4efc..48294cb87c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -10542,8 +10542,7 @@ bool regime_is_user(CPUARMState *env, ARMMMUIdx mmu= _idx) * @ap: The 3-bit access permissions (AP[2:0]) * @domain_prot: The 2-bit domain access permissions */ -static inline int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, - int ap, int domain_prot) +int ap_to_rw_prot(CPUARMState *env, ARMMMUIdx mmu_idx, int ap, int domain_= prot) { bool is_user =3D regime_is_user(env, mmu_idx); =20 @@ -10746,8 +10745,8 @@ static int get_S1prot(CPUARMState *env, ARMMMUIdx m= mu_idx, bool is_aa64, return prot_rw | PAGE_EXEC; } =20 -static bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, - uint32_t *table, uint32_t address) +bool get_level1_table_address(CPUARMState *env, ARMMMUIdx mmu_idx, + uint32_t *table, uint32_t address) { /* Note that we can only get here for an AArch32 PL0/PL1 lookup */ TCR *tcr =3D regime_tcr(env, mmu_idx); @@ -10846,8 +10845,8 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, } =20 /* All loads done in the course of a page table walk go through here. */ -static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +uint32_t arm_ldl_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -10875,8 +10874,8 @@ static uint32_t arm_ldl_ptw(CPUState *cs, hwaddr ad= dr, bool is_secure, return 0; } =20 -static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, - ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) +uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, + ARMMMUIdx mmu_idx, ARMMMUFaultInfo *fi) { ARMCPU *cpu =3D ARM_CPU(cs); CPUARMState *env =3D &cpu->env; @@ -10904,128 +10903,6 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr = addr, bool is_secure, return 0; } =20 -bool get_phys_addr_v5(CPUARMState *env, uint32_t address, - MMUAccessType access_type, ARMMMUIdx mmu_idx, - hwaddr *phys_ptr, int *prot, - target_ulong *page_size, - ARMMMUFaultInfo *fi) -{ - CPUState *cs =3D env_cpu(env); - int level =3D 1; - uint32_t table; - uint32_t desc; - int type; - int ap; - int domain =3D 0; - int domain_prot; - hwaddr phys_addr; - uint32_t dacr; - - /* Pagetable walk. */ - /* Lookup l1 descriptor. */ - if (!get_level1_table_address(env, mmu_idx, &table, address)) { - /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - type =3D (desc & 3); - domain =3D (desc >> 5) & 0x0f; - if (regime_el(env, mmu_idx) =3D=3D 1) { - dacr =3D env->cp15.dacr_ns; - } else { - dacr =3D env->cp15.dacr_s; - } - domain_prot =3D (dacr >> (domain * 2)) & 3; - if (type =3D=3D 0) { - /* Section translation fault. */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - if (type !=3D 2) { - level =3D 2; - } - if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { - fi->type =3D ARMFault_Domain; - goto do_fault; - } - if (type =3D=3D 2) { - /* 1Mb section. */ - phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); - ap =3D (desc >> 10) & 3; - *page_size =3D 1024 * 1024; - } else { - /* Lookup l2 entry. */ - if (type =3D=3D 1) { - /* Coarse pagetable. */ - table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); - } else { - /* Fine pagetable. */ - table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); - } - desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), - mmu_idx, fi); - if (fi->type !=3D ARMFault_None) { - goto do_fault; - } - switch (desc & 3) { - case 0: /* Page translation fault. */ - fi->type =3D ARMFault_Translation; - goto do_fault; - case 1: /* 64k page. */ - phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); - ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; - *page_size =3D 0x10000; - break; - case 2: /* 4k page. */ - phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; - *page_size =3D 0x1000; - break; - case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ - if (type =3D=3D 1) { - /* ARMv6/XScale extended small page format */ - if (arm_feature(env, ARM_FEATURE_XSCALE) - || arm_feature(env, ARM_FEATURE_V6)) { - phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); - *page_size =3D 0x1000; - } else { - /* UNPREDICTABLE in ARMv5; we choose to take a - * page translation fault. - */ - fi->type =3D ARMFault_Translation; - goto do_fault; - } - } else { - phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); - *page_size =3D 0x400; - } - ap =3D (desc >> 4) & 3; - break; - default: - /* Never happens, but compiler isn't smart enough to tell. */ - g_assert_not_reached(); - } - } - *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); - *prot |=3D *prot ? PAGE_EXEC : 0; - if (!(*prot & (1 << access_type))) { - /* Access permission fault. */ - fi->type =3D ARMFault_Permission; - goto do_fault; - } - *phys_ptr =3D phys_addr; - return false; -do_fault: - fi->domain =3D domain; - fi->level =3D level; - return true; -} - bool get_phys_addr_v6(CPUARMState *env, uint32_t address, MMUAccessType access_type, ARMMMUIdx mmu_idx, hwaddr *phys_ptr, MemTxAttrs *attrs, int *prot, diff --git a/target/arm/ptw.c b/target/arm/ptw.c index 318000f6d9..09c4472628 100644 --- a/target/arm/ptw.c +++ b/target/arm/ptw.c @@ -13,6 +13,129 @@ #include "ptw.h" =20 =20 +static bool get_phys_addr_v5(CPUARMState *env, uint32_t address, + MMUAccessType access_type, ARMMMUIdx mmu_idx, + hwaddr *phys_ptr, int *prot, + target_ulong *page_size, + ARMMMUFaultInfo *fi) +{ + CPUState *cs =3D env_cpu(env); + int level =3D 1; + uint32_t table; + uint32_t desc; + int type; + int ap; + int domain =3D 0; + int domain_prot; + hwaddr phys_addr; + uint32_t dacr; + + /* Pagetable walk. */ + /* Lookup l1 descriptor. */ + if (!get_level1_table_address(env, mmu_idx, &table, address)) { + /* Section translation fault if page walk is disabled by PD0 or PD= 1 */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + type =3D (desc & 3); + domain =3D (desc >> 5) & 0x0f; + if (regime_el(env, mmu_idx) =3D=3D 1) { + dacr =3D env->cp15.dacr_ns; + } else { + dacr =3D env->cp15.dacr_s; + } + domain_prot =3D (dacr >> (domain * 2)) & 3; + if (type =3D=3D 0) { + /* Section translation fault. */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + if (type !=3D 2) { + level =3D 2; + } + if (domain_prot =3D=3D 0 || domain_prot =3D=3D 2) { + fi->type =3D ARMFault_Domain; + goto do_fault; + } + if (type =3D=3D 2) { + /* 1Mb section. */ + phys_addr =3D (desc & 0xfff00000) | (address & 0x000fffff); + ap =3D (desc >> 10) & 3; + *page_size =3D 1024 * 1024; + } else { + /* Lookup l2 entry. */ + if (type =3D=3D 1) { + /* Coarse pagetable. */ + table =3D (desc & 0xfffffc00) | ((address >> 10) & 0x3fc); + } else { + /* Fine pagetable. */ + table =3D (desc & 0xfffff000) | ((address >> 8) & 0xffc); + } + desc =3D arm_ldl_ptw(cs, table, regime_is_secure(env, mmu_idx), + mmu_idx, fi); + if (fi->type !=3D ARMFault_None) { + goto do_fault; + } + switch (desc & 3) { + case 0: /* Page translation fault. */ + fi->type =3D ARMFault_Translation; + goto do_fault; + case 1: /* 64k page. */ + phys_addr =3D (desc & 0xffff0000) | (address & 0xffff); + ap =3D (desc >> (4 + ((address >> 13) & 6))) & 3; + *page_size =3D 0x10000; + break; + case 2: /* 4k page. */ + phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); + ap =3D (desc >> (4 + ((address >> 9) & 6))) & 3; + *page_size =3D 0x1000; + break; + case 3: /* 1k page, or ARMv6/XScale "extended small (4k) page" */ + if (type =3D=3D 1) { + /* ARMv6/XScale extended small page format */ + if (arm_feature(env, ARM_FEATURE_XSCALE) + || arm_feature(env, ARM_FEATURE_V6)) { + phys_addr =3D (desc & 0xfffff000) | (address & 0xfff); + *page_size =3D 0x1000; + } else { + /* + * UNPREDICTABLE in ARMv5; we choose to take a + * page translation fault. + */ + fi->type =3D ARMFault_Translation; + goto do_fault; + } + } else { + phys_addr =3D (desc & 0xfffffc00) | (address & 0x3ff); + *page_size =3D 0x400; + } + ap =3D (desc >> 4) & 3; + break; + default: + /* Never happens, but compiler isn't smart enough to tell. */ + g_assert_not_reached(); + } + } + *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); + *prot |=3D *prot ? PAGE_EXEC : 0; + if (!(*prot & (1 << access_type))) { + /* Access permission fault. */ + fi->type =3D ARMFault_Permission; + goto do_fault; + } + *phys_ptr =3D phys_addr; + return false; +do_fault: + fi->domain =3D domain; + fi->level =3D level; + return true; +} + /** * get_phys_addr - get the physical address for this virtual address * --=20 2.34.1