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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=mksmTgYxc+i1xeor+23w3y2aLNd6eFpnSEzpP11e0Kc=; b=uWdAnGytpL8zYWw2bLGkMHLBZhI+VgBdsap+Afoq2rVBY/YgfMIWgB8/Do6ZasMQsV YLYsPaXAgpvQcpR3J71KRPtYW6ur56XRY3v6xJG8tLzQ328RwX+YcFY0cUogcLmneNem 7QjEQDdid7B+1wUd+7Ec1yZrXUSGEcHNsCH0+5/v5bntZOSyPDhEbuxMvl/hAZ95GA5D aAiSAZb8BYIWajoTujht82xkx3aOC1Lu2qCccswQyl4ZenoYMjZkaJpzj2rJY9OZiGe+ J+eDPPzCns982bXwwv7YxGQ3jcOor1ziyC9mXt/ozyTnw46Ss2h+4qXB4O+XV9YiZMgT 6kcQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mksmTgYxc+i1xeor+23w3y2aLNd6eFpnSEzpP11e0Kc=; b=M4rjI/TfI8Q0LB2eyqwVLkwg0eSgR8w+VtCGZAZRCsSIf1eJ/ygQi0vGbPHhNQv/Dw 1A1mc4AaDs6wxE3HvU2kglm6/f19LTNiCtgodlB/wCE7/NHdz0eO5SHJlK1rg9Uo8wzZ h9rOB+aiEYeuvjt9NeUsoXPbl8G2mKxTiNW9OYNXELtnkde8V7cWPZ2/Y1chfP4jey14 fZHeq9sk4IkAM4iBvWG2JxIW+wIex5XHZfrbXzhaobLhE6b0DjexQDKG5q3cpdJxwFwQ R9E6dVLws2c6xvrGH/hEXrDYd2DKzvFQQzH7BzpYeyz33kDpN2Snzotw60TYngcftcdw ijfA== X-Gm-Message-State: AOAM532juktFYg2MkGx/XkjrDd9Qr0Ftt3iilxv8Mgy3bmyKrEaFiZfG YDvQa5PvoglAZ20nYxSDirevEtzEP/kiHw== X-Google-Smtp-Source: ABdhPJyrgcpkimoiTcwfMhiRMQE9L9nWMgeABdFaTanwyesgvBgF9ySR4vVnEFeAK4Z48Hlpb27IrA== X-Received: by 2002:a17:902:d4d1:b0:163:82c7:24 with SMTP id o17-20020a170902d4d100b0016382c70024mr6881254plg.5.1654206758724; Thu, 02 Jun 2022 14:52:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 50/71] target/arm: Implement FMOPA, FMOPS (non-widening) Date: Thu, 2 Jun 2022 14:48:32 -0700 Message-Id: <20220602214853.496211-51-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654209640930100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 9 +++++ target/arm/sme_helper.c | 67 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 33 +++++++++++++++++++ 4 files changed, 114 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 6f0fce7e2c..727095a3eb 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -119,3 +119,8 @@ DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, = ptr, ptr, ptr, ptr, i32) DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) + +DEF_HELPER_FLAGS_7(sme_fmopa_s, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_7(sme_fmopa_d, TCG_CALL_NO_RWG, + void, ptr, ptr, ptr, ptr, ptr, ptr, i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index 8cb6c4053c..ba4774d174 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -64,3 +64,12 @@ ADDHA_s 11000000 10 01000 0 ... ... ..... 000 ..= @adda_32 ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 + +### SME Outer Product + +&op zad zn zm pm pn sub:bool +@op_32 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 .. zad:2 &op +@op_64 ........ ... zm:5 pm:3 pn:3 zn:5 sub:1 . zad:3 &op + +FMOPA_s 10000000 100 ..... ... ... ..... . 00 .. @op_32 +FMOPA_d 10000000 110 ..... ... ... ..... . 0 ... @op_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b2b6380901..16655c86a2 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -25,6 +25,7 @@ #include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "qemu/int128.h" +#include "fpu/softfloat.h" #include "vec_internal.h" #include "sve_ldst_internal.h" =20 @@ -896,3 +897,69 @@ void HELPER(sme_addva_d)(void *vzda, void *vzn, void *= vpn, } } } + +void HELPER(sme_fmopa_s)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_maxsz(desc); + uint32_t neg =3D simd_data(desc) << 31; + uint16_t *pn =3D vpn, *pm =3D vpm; + + bool save_dn =3D get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row =3D 0; row < oprsz; ) { + uint16_t pa =3D pn[H2(row >> 4)]; + do { + if (pa & 1) { + void *vza_row =3D vza + row * sizeof(ARMVectorReg); + uint32_t n =3D *(uint32_t *)(vzn + row) ^ neg; + + for (col =3D 0; col < oprsz; ) { + uint16_t pb =3D pm[H2(col >> 4)]; + do { + if (pb & 1) { + uint32_t *a =3D vza_row + col; + uint32_t *m =3D vzm + col; + *a =3D float32_muladd(n, *m, *a, 0, vst); + } + col +=3D 4; + pb >>=3D 4; + } while (col & 15); + } + } + row +=3D 4; + pa >>=3D 4; + } while (row & 15); + } + + set_default_nan_mode(save_dn, vst); +} + +void HELPER(sme_fmopa_d)(void *vza, void *vzn, void *vzm, void *vpn, + void *vpm, void *vst, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint64_t neg =3D (uint64_t)simd_data(desc) << 63; + uint64_t *za =3D vza, *zn =3D vzn, *zm =3D vzm; + uint8_t *pn =3D vpn, *pm =3D vpm; + + bool save_dn =3D get_default_nan_mode(vst); + set_default_nan_mode(true, vst); + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t *za_row =3D &za[row * sizeof(ARMVectorReg)]; + uint64_t n =3D zn[row] ^ neg; + + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + uint64_t *a =3D &za_row[col]; + *a =3D float64_muladd(n, zm[col], *a, 0, vst); + } + } + } + } + + set_default_nan_mode(save_dn, vst); +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index e9676b2415..e6e4541e76 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -273,3 +273,36 @@ TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_h= elper_sme_addha_s) TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) + +static bool do_outprod_fpst(DisasContext *s, arg_op *a, MemOp esz, + gen_helper_gvec_5_ptr *fn) +{ + uint32_t desc =3D simd_desc(s->svl, s->svl, a->sub); + TCGv_ptr za, zn, zm, pn, pm, fpst; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + zm =3D vec_full_reg_ptr(s, a->zm); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + fpst =3D fpstatus_ptr(FPST_FPCR); + + fn(za, zn, zm, pn, pm, fpst, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + tcg_temp_free_ptr(fpst); + return true; +} + +TRANS_FEAT(FMOPA_s, aa64_sme, do_outprod_fpst, + a, MO_32, gen_helper_sme_fmopa_s) +TRANS_FEAT(FMOPA_d, aa64_sme_f64f64, do_outprod_fpst, + a, MO_64, gen_helper_sme_fmopa_d) --=20 2.34.1