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[174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=sgRdSe37RQpWV2b3fES1plqznaLnrgUpAgZ7R8ertBU=; b=LwgAeufXBNNtdQ6RiRkVhqEH5JpYxrCI9OpUrnwKAqGsdoAHVfjuGFD1Tz2g5v0Efq vhQtqQk6xDh/4R2LbYQh0oK7WDRVnM/PXzFH64LRujKHd684f7EY8PXj6L1MYU/knz89 rs00VL/M3cshj9TEPYpySm+2wu1YknyayDS4KT6yeR6Wzv35cNxYvb+lPz9iIOTZgzWn cINopf6FEk8hrqml0TKjAEMModc4xmkC5rOfAm2Mnxf6NQhZKkniDlQS0NmZwdSTGXe6 KxYxy9U9wJyexlfTMNIlWfl9CgQ9NVCw4M7XcSshf5JaSnTQlgagZrKOo8njwueEmEJu hRdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52e; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654209176608100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Richard Henderson --- target/arm/helper-sme.h | 5 +++ target/arm/sme.decode | 11 +++++ target/arm/sme_helper.c | 90 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-sme.c | 30 +++++++++++++ 4 files changed, 136 insertions(+) diff --git a/target/arm/helper-sme.h b/target/arm/helper-sme.h index 5cca01f372..6f0fce7e2c 100644 --- a/target/arm/helper-sme.h +++ b/target/arm/helper-sme.h @@ -114,3 +114,8 @@ DEF_HELPER_FLAGS_5(sme_st1q_be_h_mte, TCG_CALL_NO_WG, v= oid, env, ptr, ptr, tl, i DEF_HELPER_FLAGS_5(sme_st1q_le_h_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_be_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) DEF_HELPER_FLAGS_5(sme_st1q_le_v_mte, TCG_CALL_NO_WG, void, env, ptr, ptr,= tl, i32) + +DEF_HELPER_FLAGS_5(sme_addha_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_s, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addha_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) +DEF_HELPER_FLAGS_5(sme_addva_d, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,= i32) diff --git a/target/arm/sme.decode b/target/arm/sme.decode index f1ebd857a5..8cb6c4053c 100644 --- a/target/arm/sme.decode +++ b/target/arm/sme.decode @@ -53,3 +53,14 @@ LDST1 1110000 111 st:1 rm:5 v:1 .. pg:3 rn= :5 0 za_imm:4 \ =20 LDR 1110000 100 0 000000 .. 000 ..... 0 .... @ldstr STR 1110000 100 1 000000 .. 000 ..... 0 .... @ldstr + +### SME Add Vector to Array + +&adda zad zn pm pn +@adda_32 ........ .. ..... . pm:3 pn:3 zn:5 ... zad:2 &adda +@adda_64 ........ .. ..... . pm:3 pn:3 zn:5 .. zad:3 &adda + +ADDHA_s 11000000 10 01000 0 ... ... ..... 000 .. @adda_32 +ADDVA_s 11000000 10 01000 1 ... ... ..... 000 .. @adda_32 +ADDHA_d 11000000 11 01000 0 ... ... ..... 00 ... @adda_64 +ADDVA_d 11000000 11 01000 1 ... ... ..... 00 ... @adda_64 diff --git a/target/arm/sme_helper.c b/target/arm/sme_helper.c index b32c8435cb..b2b6380901 100644 --- a/target/arm/sme_helper.c +++ b/target/arm/sme_helper.c @@ -806,3 +806,93 @@ DO_ST(q, _be, MO_128) DO_ST(q, _le, MO_128) =20 #undef DO_ST + +void HELPER(sme_addha_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn[= col]; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addha_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn[col]; + } + } + } + } +} + +void HELPER(sme_addva_s)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 4; + uint64_t *pn =3D vpn, *pm =3D vpm; + uint32_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ) { + uint64_t pa =3D pn[row >> 4]; + do { + if (pa & 1) { + uint32_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ) { + uint64_t pb =3D pm[col >> 4]; + do { + if (pb & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn_= row; + } + pb >>=3D 4; + } while (++col & 15); + } + } + pa >>=3D 4; + } while (++row & 15); + } +} + +void HELPER(sme_addva_d)(void *vzda, void *vzn, void *vpn, + void *vpm, uint32_t desc) +{ + intptr_t row, col, oprsz =3D simd_oprsz(desc) / 8; + uint8_t *pn =3D vpn, *pm =3D vpm; + uint64_t * restrict zda =3D vzda, * restrict zn =3D vzn; + + for (row =3D 0; row < oprsz; ++row) { + if (pn[H1(row)] & 1) { + uint64_t zn_row =3D zn[row]; + for (col =3D 0; col < oprsz; ++col) { + if (pm[H1(col)] & 1) { + zda[row * sizeof(ARMVectorReg) + col] +=3D zn_row; + } + } + } + } +} diff --git a/target/arm/translate-sme.c b/target/arm/translate-sme.c index c3e544d69c..e9676b2415 100644 --- a/target/arm/translate-sme.c +++ b/target/arm/translate-sme.c @@ -243,3 +243,33 @@ static bool do_ldst_r(DisasContext *s, arg_ldstr *a, G= enLdStR *fn) =20 TRANS_FEAT(LDR, aa64_sme, do_ldst_r, a, gen_sve_ldr) TRANS_FEAT(STR, aa64_sme, do_ldst_r, a, gen_sve_str) + +static bool do_adda(DisasContext *s, arg_adda *a, MemOp esz, + gen_helper_gvec_4 *fn) +{ + uint32_t desc =3D simd_desc(s->svl, s->svl, 0); + TCGv_ptr za, zn, pn, pm; + + if (!sme_smza_enabled_check(s)) { + return true; + } + + /* Sum XZR+zad to find ZAd. */ + za =3D get_tile_rowcol(s, esz, 31, a->zad, false); + zn =3D vec_full_reg_ptr(s, a->zn); + pn =3D pred_full_reg_ptr(s, a->pn); + pm =3D pred_full_reg_ptr(s, a->pm); + + fn(za, zn, pn, pm, tcg_constant_i32(desc)); + + tcg_temp_free_ptr(za); + tcg_temp_free_ptr(zn); + tcg_temp_free_ptr(pn); + tcg_temp_free_ptr(pm); + return true; +} + +TRANS_FEAT(ADDHA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addha_s) +TRANS_FEAT(ADDVA_s, aa64_sme, do_adda, a, MO_32, gen_helper_sme_addva_s) +TRANS_FEAT(ADDHA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= ha_d) +TRANS_FEAT(ADDVA_d, aa64_sme_i16i64, do_adda, a, MO_64, gen_helper_sme_add= va_d) --=20 2.34.1