From nobody Tue Feb 10 19:50:10 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1654210034; cv=none; d=zohomail.com; s=zohoarc; b=RpK44ArBAIPAnmfexC8eyjqKJGA9i1oZjAE9yLh4b/sjYiA8Rhs3HH1p6+hiHeI/yMreKAZrefs1HpDbgJW4yMcR0jAcsTq9TNwpJQFwiEAgSBy9CtLaSQUjw0BEPN7rlkIgGoTEsWCWpuMKCKfGXVIIey7zoWg5b7sOI2gP2cQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1654210034; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=j/X+8isFAY+oKQEJkk0Ycj9MUAE1OrjrflLWCL55TbBi5ADDt4yEt0iDMwlyGOVm3UQo+4/l8T8eee/LMVDs1/k2S6jg0FxbH2+JPYzEbwLXQQBaIlPS1cpK5mYR/AZ9IxFswjvUNUwmirSBrXsl3ZtPji8n9Vy2F6MpT937Pig= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1654210034182762.1007930440617; Thu, 2 Jun 2022 15:47:14 -0700 (PDT) Received: from localhost ([::1]:43974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nwtaz-0008DE-7g for importer@patchew.org; Thu, 02 Jun 2022 18:47:13 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38830) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nwskQ-0001ic-1b for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:59 -0400 Received: from mail-qv1-xf2c.google.com ([2607:f8b0:4864:20::f2c]:40567) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nwskL-0000xB-Dy for qemu-devel@nongnu.org; Thu, 02 Jun 2022 17:52:52 -0400 Received: by mail-qv1-xf2c.google.com with SMTP id el14so4460405qvb.7 for ; Thu, 02 Jun 2022 14:52:47 -0700 (PDT) Received: from stoup.. (174-21-71-225.tukw.qwest.net. [174.21.71.225]) by smtp.gmail.com with ESMTPSA id e14-20020a170902ed8e00b0015edfccfdb5sm4039605plj.50.2022.06.02.14.52.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 02 Jun 2022 14:52:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=UNh13BfV7arA5TxObmWyk4RxENWFy7Fxw2O8EH2PYF5eIgLYtQ6qv/c9wau5my+FZV 7OUy9EpTk5lCrrOgFUwSfnT36X8HVtcctH1NvymVOUW0Try7w++FwidfcuromWfjd9yT NBxFLnWRG4HeX6BBiRMEhEHI6zNfPC8Fjoc1HwjRAou6fgul2dtx4MxAWkj1Vm41ufdz qJ/SolNoycnVx1FVhCJUg3dEieCeXd4opCao1koeLYqySNLgT/pfE1FOwZltmPYF8vnT vqfDJU91bewoWOTAqkl+l0VYnRTY48s4lT40caFzyYOz8knJm4an771ca+N1W9w6tQMr SQQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hBZdPZWCdnFknqirCWCAN0zMysKwnh33zUMVY3zWbxw=; b=A2mCashB0+zOsF3/PjPFllI+ysVN/UR8lvPC6Q4jjYzQaCFhyLScOIou2rZws834kt k9xtNh380RoAb7sL8NcoqUfIjw2yQoesITa8wd3844eKE+DWqEBkvUpqxpFS3DuacUX6 8pqFpYxVuihmaaVMBQ2aVTXcGho1/yOvjaX5eo161RoIojrSZ6ykLL9fFMApNtOniX15 LnSY6j+LT+fUvb6aWwJCsjsffedYAP5waSrG0kNrduYKR0xGYX/oj64G5QSak8sG+ZfL PyhX/gHJRTpnAuHlEmo7SW3yVFXh6BtSygvDNNaEv0V/lUXoahTmnEXxPug2b+JDd0F+ 3w6g== X-Gm-Message-State: AOAM530W7SRdYTdALmMBXzqdO166M/wkNMBYF87zXLEMK3oemQKcrE8o ZEaumHWhcozKQMw+qBICDsg8pnZ/ucXYxQ== X-Google-Smtp-Source: ABdhPJzYHLcGwLKpBSX8GR7vEe55Pq9ndNY66z+qYRy6v22VAEz5HWoIbEy9DhaG2hCvOKoblgdC9g== X-Received: by 2002:a17:903:41c1:b0:163:771e:e61c with SMTP id u1-20020a17090341c100b00163771ee61cmr6945534ple.49.1654206756302; Thu, 02 Jun 2022 14:52:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 47/71] target/arm: Export unpredicated ld/st from translate-sve.c Date: Thu, 2 Jun 2022 14:48:29 -0700 Message-Id: <20220602214853.496211-48-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220602214853.496211-1-richard.henderson@linaro.org> References: <20220602214853.496211-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::f2c; envelope-from=richard.henderson@linaro.org; helo=mail-qv1-xf2c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1654210035697100001 Content-Type: text/plain; charset="utf-8" Add a TCGv_ptr base argument, which will be cpu_env for SVE. We will reuse this for SME save and restore array insns. Signed-off-by: Richard Henderson --- target/arm/translate-a64.h | 3 +++ target/arm/translate-sve.c | 48 ++++++++++++++++++++++++++++---------- 2 files changed, 39 insertions(+), 12 deletions(-) diff --git a/target/arm/translate-a64.h b/target/arm/translate-a64.h index c341c95582..54503745a9 100644 --- a/target/arm/translate-a64.h +++ b/target/arm/translate-a64.h @@ -165,4 +165,7 @@ void gen_gvec_xar(unsigned vece, uint32_t rd_ofs, uint3= 2_t rn_ofs, uint32_t rm_ofs, int64_t shift, uint32_t opr_sz, uint32_t max_sz); =20 +void gen_sve_ldr(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); +void gen_sve_str(DisasContext *s, TCGv_ptr, int vofs, int len, int rn, int= imm); + #endif /* TARGET_ARM_TRANSLATE_A64_H */ diff --git a/target/arm/translate-sve.c b/target/arm/translate-sve.c index 13bdd027a5..adf0cd3e68 100644 --- a/target/arm/translate-sve.c +++ b/target/arm/translate-sve.c @@ -4294,7 +4294,8 @@ TRANS_FEAT(UCVTF_dd, aa64_sve, gen_gvec_fpst_arg_zpz, * The load should begin at the address Rn + IMM. */ =20 -static void do_ldr(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_ldr(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4320,7 +4321,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { tcg_gen_qemu_ld_i64(t0, clean_addr, midx, MO_LEUQ); - tcg_gen_st_i64(t0, cpu_env, vofs + i); + tcg_gen_st_i64(t0, base, vofs + i); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } tcg_temp_free_i64(t0); @@ -4333,6 +4334,12 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); @@ -4340,7 +4347,7 @@ static void do_ldr(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) tcg_gen_addi_i64(clean_addr, clean_addr, 8); =20 tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_addi_ptr(i, i, 8); tcg_gen_st_i64(t0, tp, vofs); tcg_temp_free_ptr(tp); @@ -4348,6 +4355,11 @@ static void do_ldr(DisasContext *s, uint32_t vofs, i= nt len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* @@ -4376,13 +4388,14 @@ static void do_ldr(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) default: g_assert_not_reached(); } - tcg_gen_st_i64(t0, cpu_env, vofs + len_align); + tcg_gen_st_i64(t0, base, vofs + len_align); tcg_temp_free_i64(t0); } } =20 /* Similarly for stores. */ -static void do_str(DisasContext *s, uint32_t vofs, int len, int rn, int im= m) +void gen_sve_str(DisasContext *s, TCGv_ptr base, int vofs, + int len, int rn, int imm) { int len_align =3D QEMU_ALIGN_DOWN(len, 8); int len_remain =3D len % 8; @@ -4408,7 +4421,7 @@ static void do_str(DisasContext *s, uint32_t vofs, in= t len, int rn, int imm) =20 t0 =3D tcg_temp_new_i64(); for (i =3D 0; i < len_align; i +=3D 8) { - tcg_gen_ld_i64(t0, cpu_env, vofs + i); + tcg_gen_ld_i64(t0, base, vofs + i); tcg_gen_qemu_st_i64(t0, clean_addr, midx, MO_LEUQ); tcg_gen_addi_i64(clean_addr, clean_addr, 8); } @@ -4422,11 +4435,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) clean_addr =3D new_tmp_a64_local(s); tcg_gen_mov_i64(clean_addr, t0); =20 + if (base !=3D cpu_env) { + TCGv_ptr b =3D tcg_temp_local_new_ptr(); + tcg_gen_mov_ptr(b, base); + base =3D b; + } + gen_set_label(loop); =20 t0 =3D tcg_temp_new_i64(); tp =3D tcg_temp_new_ptr(); - tcg_gen_add_ptr(tp, cpu_env, i); + tcg_gen_add_ptr(tp, base, i); tcg_gen_ld_i64(t0, tp, vofs); tcg_gen_addi_ptr(i, i, 8); tcg_temp_free_ptr(tp); @@ -4437,12 +4456,17 @@ static void do_str(DisasContext *s, uint32_t vofs, = int len, int rn, int imm) =20 tcg_gen_brcondi_ptr(TCG_COND_LTU, i, len_align, loop); tcg_temp_free_ptr(i); + + if (base !=3D cpu_env) { + tcg_temp_free_ptr(base); + assert(len_remain =3D=3D 0); + } } =20 /* Predicate register stores can be any multiple of 2. */ if (len_remain) { t0 =3D tcg_temp_new_i64(); - tcg_gen_ld_i64(t0, cpu_env, vofs + len_align); + tcg_gen_ld_i64(t0, base, vofs + len_align); =20 switch (len_remain) { case 2: @@ -4474,7 +4498,7 @@ static bool trans_LDR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4487,7 +4511,7 @@ static bool trans_LDR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_ldr(s, off, size, a->rn, a->imm * size); + gen_sve_ldr(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4500,7 +4524,7 @@ static bool trans_STR_zri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D vec_full_reg_size(s); int off =3D vec_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } @@ -4513,7 +4537,7 @@ static bool trans_STR_pri(DisasContext *s, arg_rri *a) if (sve_access_check(s)) { int size =3D pred_full_reg_size(s); int off =3D pred_full_reg_offset(s, a->rd); - do_str(s, off, size, a->rn, a->imm * size); + gen_sve_str(s, cpu_env, off, size, a->rn, a->imm * size); } return true; } --=20 2.34.1