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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1654034221746100001 Content-Type: text/plain; charset="utf-8" To enable user creatable PnvPHB devices for powernv9 we'll revert the powernv9 related changes made in 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices". This change alone isn't enough to enable user creatable devices for powernv= 10 due to how pnv_phb4_get_pec() currently works. For now let's just enable it for powernv9 alone. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 58 +++++++++++++++++++++++++++++++++++++- hw/pci-host/pnv_phb4_pec.c | 6 ++-- hw/ppc/pnv.c | 2 ++ 3 files changed, 63 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 22cf1c2a5e..a5c8ae494b 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1571,13 +1571,69 @@ void pnv_phb4_bus_init(DeviceState *dev, PnvPHB4 *p= hb) pci->bus->flags |=3D PCI_BUS_EXTENDED_CONFIG_SPACE; } =20 +static PnvPhb4PecState *pnv_phb4_get_pec(PnvChip *chip, PnvPHB4 *phb, + Error **errp) +{ + Pnv9Chip *chip9 =3D PNV9_CHIP(chip); + int chip_id =3D phb->chip_id; + int index =3D phb->phb_id; + int i, j; + + for (i =3D 0; i < chip->num_pecs; i++) { + /* + * For each PEC, check the amount of phbs it supports + * and see if the given phb4 index matches an index. + */ + PnvPhb4PecState *pec =3D &chip9->pecs[i]; + + for (j =3D 0; j < pec->num_phbs; j++) { + if (index =3D=3D pnv_phb4_pec_get_phb_id(pec, j)) { + return pec; + } + } + } + + error_setg(errp, + "pnv-phb4 chip-id %d index %d didn't match any existing PEC= ", + chip_id, index); + + return NULL; +} + static void pnv_phb4_realize(DeviceState *dev, Error **errp) { PnvPHB4 *phb =3D PNV_PHB4(dev); + PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); + PnvChip *chip =3D pnv_get_chip(pnv, phb->chip_id); XiveSource *xsrc =3D &phb->xsrc; + BusState *s; + Error *local_err =3D NULL; int nr_irqs; char name[32]; =20 + if (!chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + /* User created PHBs need to be assigned to a PEC */ + if (!phb->pec) { + phb->pec =3D pnv_phb4_get_pec(chip, phb, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } + + /* Reparent the PHB to the chip to build the device tree */ + pnv_chip_parent_fixup(chip, OBJECT(phb->phb_base), phb->phb_id); + + s =3D qdev_get_parent_bus(DEVICE(chip)); + if (!qdev_set_parent_bus(DEVICE(phb->phb_base), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + /* Set the "big_phb" flag */ phb->big_phb =3D phb->phb_id =3D=3D 0 || phb->phb_id =3D=3D 3; =20 @@ -1803,7 +1859,7 @@ static void pnv_phb4_root_port_class_init(ObjectClass= *klass, void *data) PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_CLASS(klass); =20 dc->desc =3D "IBM PHB4 PCIE Root Port"; - dc->user_creatable =3D false; + dc->user_creatable =3D true; =20 device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, &rpc->parent_realize); diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 888ecbe8f3..0e67f3a338 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -146,8 +146,10 @@ static void pnv_pec_realize(DeviceState *dev, Error **= errp) pec->num_phbs =3D pecc->num_phbs[pec->index]; =20 /* Create PHBs if running with defaults */ - for (i =3D 0; i < pec->num_phbs; i++) { - pnv_pec_default_phb_realize(pec, i, errp); + if (defaults_enabled()) { + for (i =3D 0; i < pec->num_phbs; i++) { + pnv_pec_default_phb_realize(pec, i, errp); + } } =20 /* Initialize the XSCOM regions for the PEC registers */ diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 3b0b230e49..697a2b5302 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2186,6 +2186,8 @@ static void pnv_machine_power9_class_init(ObjectClass= *oc, void *data) pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); pmc->dt_power_mgt =3D pnv_dt_power_mgt; + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); } =20 static void pnv_machine_power10_class_init(ObjectClass *oc, void *data) --=20 2.36.1