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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x231.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1654034161481100001 Content-Type: text/plain; charset="utf-8" Change the parent type of the PnvPHB4 device to TYPE_PARENT since the PCI bus is going to be initialized by the PnvPHB parent. Functions that needs to access the bus via a PnvPHB4 object can do so via the phb4->phb_base pointer. pnv_phb4_pec now creates a PnvPHB object. The powernv9 machine class will create PnvPHB devices with version '4'. powernv10 will create using version '5'. Both are using global machine properties in their class_init() to do that. These changes will benefit us when adding PnvPHB user creatable devices for powernv9 and powernv10. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb4.c | 29 +++++++++-------------------- hw/pci-host/pnv_phb4_pec.c | 6 +----- hw/ppc/pnv.c | 20 +++++++++++++++++++- include/hw/pci-host/pnv_phb4.h | 5 ++++- 4 files changed, 33 insertions(+), 27 deletions(-) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index ae5494fe72..22cf1c2a5e 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -49,7 +49,7 @@ static inline uint64_t SETFIELD(uint64_t mask, uint64_t w= ord, =20 static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) { - PCIHostState *pci =3D PCI_HOST_BRIDGE(phb); + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); uint64_t addr =3D phb->regs[PHB_CONFIG_ADDRESS >> 3]; uint8_t bus, devfn; =20 @@ -145,7 +145,7 @@ static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsi= gned off, static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, unsigned size, uint64_t val) { - PCIHostState *pci =3D PCI_HOST_BRIDGE(phb); + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); PCIDevice *pdev; =20 if (size !=3D 4) { @@ -166,7 +166,7 @@ static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsi= gned off, static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, unsigned size) { - PCIHostState *pci =3D PCI_HOST_BRIDGE(phb); + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); PCIDevice *pdev; uint64_t val; =20 @@ -1608,16 +1608,6 @@ static void pnv_phb4_realize(DeviceState *dev, Error= **errp) pnv_phb4_xscom_realize(phb); } =20 -static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, - PCIBus *rootbus) -{ - PnvPHB4 *phb =3D PNV_PHB4(host_bridge); - - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", - phb->chip_id, phb->phb_id); - return phb->bus_path; -} - /* * Address base trigger mode (POWER10) * @@ -1702,19 +1692,18 @@ static Property pnv_phb4_properties[] =3D { DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, PnvPhb4PecState *), + DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, + TYPE_PNV_PHB, PnvPHB *), DEFINE_PROP_END_OF_LIST(), }; =20 static void pnv_phb4_class_init(ObjectClass *klass, void *data) { - PCIHostBridgeClass *hc =3D PCI_HOST_BRIDGE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); XiveNotifierClass *xfc =3D XIVE_NOTIFIER_CLASS(klass); =20 - hc->root_bus_path =3D pnv_phb4_root_bus_path; dc->realize =3D pnv_phb4_realize; device_class_set_props(dc, pnv_phb4_properties); - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->user_creatable =3D false; =20 xfc->notify =3D pnv_phb4_xive_notify; @@ -1722,7 +1711,7 @@ static void pnv_phb4_class_init(ObjectClass *klass, v= oid *data) =20 static const TypeInfo pnv_phb4_type_info =3D { .name =3D TYPE_PNV_PHB4, - .parent =3D TYPE_PCIE_HOST_BRIDGE, + .parent =3D TYPE_DEVICE, .instance_init =3D pnv_phb4_instance_init, .instance_size =3D sizeof(PnvPHB4), .class_init =3D pnv_phb4_class_init, @@ -1785,11 +1774,11 @@ static void pnv_phb4_root_port_realize(DeviceState = *dev, Error **errp) PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); PCIDevice *pci =3D PCI_DEVICE(dev); PCIBus *bus =3D pci_get_bus(pci); - PnvPHB4 *phb =3D NULL; + PnvPHB *phb =3D NULL; Error *local_err =3D NULL; =20 - phb =3D (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB4); + phb =3D (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB); =20 if (!phb) { error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id= ); diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 61bc0b503e..888ecbe8f3 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -115,8 +115,7 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState= *pec, int stack_no, Error **errp) { - PnvPhb4PecClass *pecc =3D PNV_PHB4_PEC_GET_CLASS(pec); - PnvPHB4 *phb =3D PNV_PHB4(qdev_new(pecc->phb_type)); + PnvPHB *phb =3D PNV_PHB(qdev_new(TYPE_PNV_PHB)); int phb_id =3D pnv_phb4_pec_get_phb_id(pec, stack_no); =20 object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); @@ -130,9 +129,6 @@ static void pnv_pec_default_phb_realize(PnvPhb4PecState= *pec, if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { return; } - - /* Add a single Root port if running with defaults */ - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), pecc->rp_model); } =20 static void pnv_pec_realize(DeviceState *dev, Error **errp) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 081b6839cc..3b0b230e49 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -688,7 +688,14 @@ static void pnv_chip_power8_pic_print_info(PnvChip *ch= ip, Monitor *mon) static int pnv_chip_power9_pic_print_info_child(Object *child, void *opaqu= e) { Monitor *mon =3D opaque; - PnvPHB4 *phb4 =3D (PnvPHB4 *) object_dynamic_cast(child, TYPE_PNV_PHB4= ); + PnvPHB *phb =3D (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); + PnvPHB4 *phb4; + + if (!phb) { + return 0; + } + + phb4 =3D (PnvPHB4 *)phb->backend; =20 if (phb4) { pnv_phb4_pic_print_info(phb4, mon); @@ -2164,8 +2171,14 @@ static void pnv_machine_power9_class_init(ObjectClas= s *oc, void *data) PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); static const char compat[] =3D "qemu,powernv9\0ibm,powernv"; =20 + static GlobalProperty phb_compat[] =3D { + { TYPE_PNV_PHB, "version", "4" }, + }; + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER9"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power9_v2.0"); + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat= )); + xfc->match_nvt =3D pnv_match_nvt; =20 mc->alias =3D "powernv"; @@ -2182,8 +2195,13 @@ static void pnv_machine_power10_class_init(ObjectCla= ss *oc, void *data) XiveFabricClass *xfc =3D XIVE_FABRIC_CLASS(oc); static const char compat[] =3D "qemu,powernv10\0ibm,powernv"; =20 + static GlobalProperty phb_compat[] =3D { + { TYPE_PNV_PHB, "version", "5" }, + }; + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER10"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power10_v2.0"); + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat= )); =20 pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); diff --git a/include/hw/pci-host/pnv_phb4.h b/include/hw/pci-host/pnv_phb4.h index 90843ac3a9..f22253358f 100644 --- a/include/hw/pci-host/pnv_phb4.h +++ b/include/hw/pci-host/pnv_phb4.h @@ -18,6 +18,7 @@ typedef struct PnvPhb4PecState PnvPhb4PecState; typedef struct PnvPhb4PecStack PnvPhb4PecStack; typedef struct PnvPHB4 PnvPHB4; +typedef struct PnvPHB PnvPHB; typedef struct PnvChip PnvChip; =20 /* @@ -78,7 +79,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB4, PNV_PHB4) #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) =20 struct PnvPHB4 { - PCIExpressHost parent_obj; + DeviceState parent; + + PnvPHB *phb_base; =20 uint32_t chip_id; uint32_t phb_id; --=20 2.36.1