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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22a; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22a.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1654034354844100001 Content-Type: text/plain; charset="utf-8" Let's reintroduce the powernv8 bits of the code what was removed in commit 9c10d86fee "ppc/pnv: Remove user-created PHB{3,4,5} devices", allowing us to enable user creatable pnv-phb devices for the powernv8 machine. The difference is that this time we're adding support for a PnvPHB device that is the same that will be used by the other powernv machines, allowing the user to deal with a single PnvPHB device instead of versioned PHBs for each one. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb.c | 5 ++++- hw/pci-host/pnv_phb3.c | 26 +++++++++++++++++++++++++- hw/ppc/pnv.c | 23 ++++++++++++++++++++++- include/hw/ppc/pnv.h | 1 + 4 files changed, 52 insertions(+), 3 deletions(-) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index fa8472622f..17532d25f0 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -17,6 +17,7 @@ #include "hw/ppc/pnv.h" #include "hw/qdev-properties.h" #include "qom/object.h" +#include "sysemu/sysemu.h" =20 =20 static void pnv_phb_realize(DeviceState *dev, Error **errp) @@ -71,7 +72,9 @@ static void pnv_phb_realize(DeviceState *dev, Error **err= p) pnv_phb3_bus_init(dev, (PnvPHB3 *)phb->backend); } =20 - pnv_phb_attach_root_port(pci, phb_rootport_typename); + if (defaults_enabled()) { + pnv_phb_attach_root_port(pci, phb_rootport_typename); + } } =20 static const char *pnv_phb_root_bus_path(PCIHostState *host_bridge, diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index a39aa0e8c4..839c2dad00 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1015,6 +1015,30 @@ static void pnv_phb3_realize(DeviceState *dev, Error= **errp) PnvMachineState *pnv =3D PNV_MACHINE(qdev_get_machine()); int i; =20 + /* User created devices */ + if (!phb->chip) { + Error *local_err =3D NULL; + BusState *s; + + phb->chip =3D pnv_get_chip(pnv, phb->chip_id); + if (!phb->chip) { + error_setg(errp, "invalid chip id: %d", phb->chip_id); + return; + } + + /* + * Reparent user created devices to the chip to build + * correctly the device tree. + */ + pnv_chip_parent_fixup(phb->chip, OBJECT(phb->phb_base), phb->phb_i= d); + + s =3D qdev_get_parent_bus(DEVICE(phb->chip)); + if (!qdev_set_parent_bus(DEVICE(phb->phb_base), s, &local_err)) { + error_propagate(errp, local_err); + return; + } + } + if (phb->phb_id >=3D PNV_CHIP_GET_CLASS(phb->chip)->num_phbs) { error_setg(errp, "invalid PHB index: %d", phb->phb_id); return; @@ -1167,7 +1191,7 @@ static void pnv_phb3_root_port_class_init(ObjectClass= *klass, void *data) =20 device_class_set_parent_realize(dc, pnv_phb3_root_port_realize, &rpc->parent_realize); - dc->user_creatable =3D false; + dc->user_creatable =3D true; =20 k->vendor_id =3D PCI_VENDOR_ID_IBM; k->device_id =3D 0x03dc; diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 6cd0af9adf..081b6839cc 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -1164,7 +1164,9 @@ static void pnv_chip_power8_instance_init(Object *obj) =20 object_initialize_child(obj, "homer", &chip8->homer, TYPE_PNV8_HOMER); =20 - chip8->num_phbs =3D pcc->num_phbs; + if (defaults_enabled()) { + chip8->num_phbs =3D pcc->num_phbs; + } =20 for (i =3D 0; i < chip8->num_phbs; i++) { object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_P= HB); @@ -1990,6 +1992,23 @@ static ICSState *pnv_ics_get(XICSFabric *xi, int irq) return NULL; } =20 +void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index) +{ + Object *parent =3D OBJECT(chip); + g_autofree char *default_id =3D + g_strdup_printf("%s[%d]", object_get_typename(obj), index); + + if (obj->parent =3D=3D parent) { + return; + } + + object_ref(obj); + object_unparent(obj); + object_property_add_child( + parent, DEVICE(obj)->id ? DEVICE(obj)->id : default_id, obj); + object_unref(obj); +} + PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id) { int i; @@ -2134,6 +2153,8 @@ static void pnv_machine_power8_class_init(ObjectClass= *oc, void *data) =20 pmc->compat =3D compat; pmc->compat_size =3D sizeof(compat); + + machine_class_allow_dynamic_sysbus_dev(mc, TYPE_PNV_PHB); } =20 static void pnv_machine_power9_class_init(ObjectClass *oc, void *data) diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 4595db418e..fc95b8cfaa 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -191,6 +191,7 @@ DECLARE_INSTANCE_CHECKER(PnvChip, PNV_CHIP_POWER10, =20 PowerPCCPU *pnv_chip_find_cpu(PnvChip *chip, uint32_t pir); void pnv_phb_attach_root_port(PCIHostState *pci, const char *name); +void pnv_chip_parent_fixup(PnvChip *chip, Object *obj, int index); =20 #define TYPE_PNV_MACHINE MACHINE_TYPE_NAME("powernv") typedef struct PnvMachineClass PnvMachineClass; --=20 2.36.1