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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22f.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1654034106595100001 Content-Type: text/plain; charset="utf-8" We need a handful of changes that needs to be done in a single swoop to turn PnvPHB3 into a PnvPHB backend. In the PnvPHB3, since the PnvPHB device implements PCIExpressHost and will hold the PCI bus, change PnvPHB3 parent to TYPE_DEVICE. There are a couple of instances in pnv_phb3.c that needs to access the PCI bus, so a phb_base pointer is added to allow access to the parent PnvPHB. The PnvPHB3 root port will now be connected to a PnvPHB object. In pnv.c, the powernv8 machine chip8 will now hold an array of PnvPHB objects. pnv_get_phb3_child() needs to be adapted to return the PnvPHB3 backend from the PnvPHB child. A global property is added in pnv_machine_power8_class_init() to ensure that all PnvPHBs are created with phb->version =3D 3. After all these changes we're still able to boot a powernv8 machine with default settings. The real gain will come with user created PnvPHB devices, coming up next. Signed-off-by: Daniel Henrique Barboza --- hw/pci-host/pnv_phb3.c | 29 ++++++++--------------------- hw/ppc/pnv.c | 21 +++++++++++++++++---- include/hw/pci-host/pnv_phb3.h | 5 ++++- include/hw/ppc/pnv.h | 3 ++- 4 files changed, 31 insertions(+), 27 deletions(-) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index 60584e2aae..a39aa0e8c4 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -11,6 +11,7 @@ #include "qapi/visitor.h" #include "qapi/error.h" #include "hw/pci-host/pnv_phb3_regs.h" +#include "hw/pci-host/pnv_phb.h" #include "hw/pci-host/pnv_phb3.h" #include "hw/pci/pcie_host.h" #include "hw/pci/pcie_port.h" @@ -26,7 +27,7 @@ =20 static PCIDevice *pnv_phb3_find_cfg_dev(PnvPHB3 *phb) { - PCIHostState *pci =3D PCI_HOST_BRIDGE(phb); + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); uint64_t addr =3D phb->regs[PHB_CONFIG_ADDRESS >> 3]; uint8_t bus, devfn; =20 @@ -590,7 +591,7 @@ void pnv_phb3_reg_write(void *opaque, hwaddr off, uint6= 4_t val, unsigned size) uint64_t pnv_phb3_reg_read(void *opaque, hwaddr off, unsigned size) { PnvPHB3 *phb =3D opaque; - PCIHostState *pci =3D PCI_HOST_BRIDGE(phb); + PCIHostState *pci =3D PCI_HOST_BRIDGE(phb->phb_base); uint64_t val; =20 if ((off & 0xfffc) =3D=3D PHB_CONFIG_DATA) { @@ -1057,8 +1058,6 @@ static void pnv_phb3_realize(DeviceState *dev, Error = **errp) "phb3-regs", 0x1000); =20 pnv_phb3_bus_init(dev, phb); - - pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), TYPE_PNV_PHB3_ROOT_PORT= ); } =20 void pnv_phb3_update_regions(PnvPHB3 *phb) @@ -1083,38 +1082,26 @@ void pnv_phb3_update_regions(PnvPHB3 *phb) pnv_phb3_check_all_m64s(phb); } =20 -static const char *pnv_phb3_root_bus_path(PCIHostState *host_bridge, - PCIBus *rootbus) -{ - PnvPHB3 *phb =3D PNV_PHB3(host_bridge); - - snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", - phb->chip_id, phb->phb_id); - return phb->bus_path; -} - static Property pnv_phb3_properties[] =3D { DEFINE_PROP_UINT32("index", PnvPHB3, phb_id, 0), DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), + DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvP= HB *), DEFINE_PROP_END_OF_LIST(), }; =20 static void pnv_phb3_class_init(ObjectClass *klass, void *data) { - PCIHostBridgeClass *hc =3D PCI_HOST_BRIDGE_CLASS(klass); DeviceClass *dc =3D DEVICE_CLASS(klass); =20 - hc->root_bus_path =3D pnv_phb3_root_bus_path; dc->realize =3D pnv_phb3_realize; device_class_set_props(dc, pnv_phb3_properties); - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); dc->user_creatable =3D false; } =20 static const TypeInfo pnv_phb3_type_info =3D { .name =3D TYPE_PNV_PHB3, - .parent =3D TYPE_PCIE_HOST_BRIDGE, + .parent =3D TYPE_DEVICE, .instance_size =3D sizeof(PnvPHB3), .class_init =3D pnv_phb3_class_init, .instance_init =3D pnv_phb3_instance_init, @@ -1146,11 +1133,11 @@ static void pnv_phb3_root_port_realize(DeviceState = *dev, Error **errp) PCIERootPortClass *rpc =3D PCIE_ROOT_PORT_GET_CLASS(dev); PCIDevice *pci =3D PCI_DEVICE(dev); PCIBus *bus =3D pci_get_bus(pci); - PnvPHB3 *phb =3D NULL; + PnvPHB *phb =3D NULL; Error *local_err =3D NULL; =20 - phb =3D (PnvPHB3 *) object_dynamic_cast(OBJECT(bus->qbus.parent), - TYPE_PNV_PHB3); + phb =3D (PnvPHB *) object_dynamic_cast(OBJECT(bus->qbus.parent), + TYPE_PNV_PHB); =20 if (!phb) { error_setg(errp, diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index aaf4d241c3..6cd0af9adf 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -43,6 +43,7 @@ #include "hw/ipmi/ipmi.h" #include "target/ppc/mmu-hash64.h" #include "hw/pci/msi.h" +#include "hw/pci-host/pnv_phb.h" =20 #include "hw/ppc/xics.h" #include "hw/qdev-properties.h" @@ -654,7 +655,13 @@ static ISABus *pnv_isa_create(PnvChip *chip, Error **e= rrp) =20 static PnvPHB3 *pnv_get_phb3_child(Object *child) { - return (PnvPHB3 *)object_dynamic_cast(child, TYPE_PNV_PHB3); + PnvPHB *phb =3D (PnvPHB *) object_dynamic_cast(child, TYPE_PNV_PHB); + + if (!phb) { + return NULL; + } + + return (PnvPHB3 *)phb->backend; } =20 static int pnv_chip_power8_pic_print_info_child(Object *child, void *opaqu= e) @@ -1160,7 +1167,7 @@ static void pnv_chip_power8_instance_init(Object *obj) chip8->num_phbs =3D pcc->num_phbs; =20 for (i =3D 0; i < chip8->num_phbs; i++) { - object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_P= HB3); + object_initialize_child(obj, "phb[*]", &chip8->phbs[i], TYPE_PNV_P= HB); } =20 } @@ -1282,9 +1289,9 @@ static void pnv_chip_power8_realize(DeviceState *dev,= Error **errp) memory_region_add_subregion(get_system_memory(), PNV_HOMER_BASE(chip), &chip8->homer.regs); =20 - /* PHB3 controllers */ + /* PHB controllers */ for (i =3D 0; i < chip8->num_phbs; i++) { - PnvPHB3 *phb =3D &chip8->phbs[i]; + PnvPHB *phb =3D &chip8->phbs[i]; =20 object_property_set_int(OBJECT(phb), "index", i, &error_fatal); object_property_set_int(OBJECT(phb), "chip-id", chip->chip_id, @@ -1957,6 +1964,7 @@ static int pnv_ics_get_child(Object *child, void *opa= que) args->ics =3D ICS(&phb3->msis); } } + return args->ics ? 1 : 0; } =20 @@ -2112,8 +2120,13 @@ static void pnv_machine_power8_class_init(ObjectClas= s *oc, void *data) PnvMachineClass *pmc =3D PNV_MACHINE_CLASS(oc); static const char compat[] =3D "qemu,powernv8\0qemu,powernv\0ibm,power= nv"; =20 + static GlobalProperty phb_compat[] =3D { + { TYPE_PNV_PHB, "version", "3" }, + }; + mc->desc =3D "IBM PowerNV (Non-Virtualized) POWER8"; mc->default_cpu_type =3D POWERPC_CPU_TYPE_NAME("power8_v2.0"); + compat_props_add(mc->compat_props, phb_compat, G_N_ELEMENTS(phb_compat= )); =20 xic->icp_get =3D pnv_icp_get; xic->ics_get =3D pnv_ics_get; diff --git a/include/hw/pci-host/pnv_phb3.h b/include/hw/pci-host/pnv_phb3.h index 1375f18fc1..3b9ff1096a 100644 --- a/include/hw/pci-host/pnv_phb3.h +++ b/include/hw/pci-host/pnv_phb3.h @@ -14,6 +14,7 @@ #include "hw/pci/pcie_port.h" #include "hw/ppc/xics.h" #include "qom/object.h" +#include "hw/pci-host/pnv_phb.h" =20 typedef struct PnvPHB3 PnvPHB3; typedef struct PnvChip PnvChip; @@ -127,7 +128,9 @@ OBJECT_DECLARE_SIMPLE_TYPE(PnvPHB3, PNV_PHB3) #define PCI_MMIO_TOTAL_SIZE (0x1ull << 60) =20 struct PnvPHB3 { - PCIExpressHost parent_obj; + DeviceState parent; + + PnvPHB *phb_base; =20 uint32_t chip_id; uint32_t phb_id; diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h index 86cb7d7f97..4595db418e 100644 --- a/include/hw/ppc/pnv.h +++ b/include/hw/ppc/pnv.h @@ -32,6 +32,7 @@ #include "hw/ppc/pnv_core.h" #include "hw/pci-host/pnv_phb3.h" #include "hw/pci-host/pnv_phb4.h" +#include "hw/pci-host/pnv_phb.h" #include "qom/object.h" =20 #define TYPE_PNV_CHIP "pnv-chip" @@ -80,7 +81,7 @@ struct Pnv8Chip { PnvHomer homer; =20 #define PNV8_CHIP_PHB3_MAX 4 - PnvPHB3 phbs[PNV8_CHIP_PHB3_MAX]; + PnvPHB phbs[PNV8_CHIP_PHB3_MAX]; uint32_t num_phbs; =20 XICSFabric *xics; --=20 2.36.1