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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=atishp@rivosinc.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @rivosinc-com.20210112.gappssmtp.com) X-ZM-MESSAGEID: 1654021774119100001 Content-Type: text/plain; charset="utf-8" vstimecmp CSR allows the guest OS or to program the next guest timer interrupt directly. Thus, hypervisor no longer need to inject the timer interrupt to the guest if vstimecmp is used. This was ratified as a part of the Sstc extension. Signed-off-by: Atish Patra --- target/riscv/cpu.h | 4 ++ target/riscv/cpu_bits.h | 4 ++ target/riscv/cpu_helper.c | 11 ++-- target/riscv/csr.c | 100 ++++++++++++++++++++++++++++++++++++- target/riscv/machine.c | 1 + target/riscv/time_helper.c | 16 ++++++ 6 files changed, 131 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9a5e02f217ba..063d90eebf4d 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -279,6 +279,8 @@ struct CPUArchState { /* Sstc CSRs */ uint64_t stimecmp; =20 + uint64_t vstimecmp; + /* physical memory protection */ pmp_table_t pmp_state; target_ulong mseccfg; @@ -333,6 +335,8 @@ struct CPUArchState { =20 /* Fields from here on are preserved across CPU reset. */ QEMUTimer *stimer; /* Internal timer for S-mode interrupt */ + QEMUTimer *vstimer; /* Internal timer for VS-mode interrupt */ + bool vstime_irq; =20 hwaddr kernel_addr; hwaddr fdt_addr; diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 29d0e4a1be01..5c9f512872e1 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -272,6 +272,10 @@ #define CSR_VSIP 0x244 #define CSR_VSATP 0x280 =20 +/* Sstc virtual CSRs */ +#define CSR_VSTIMECMP 0x24D +#define CSR_VSTIMECMPH 0x25D + #define CSR_MTINST 0x34a #define CSR_MTVAL2 0x34b =20 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e1aa4f2097c1..2715021c022e 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -344,8 +344,9 @@ static uint64_t riscv_cpu_all_pending(CPURISCVState *en= v) { uint32_t gein =3D get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; + uint64_t vstip =3D (env->vstime_irq) ? MIP_VSTIP : 0; =20 - return (env->mip | vsgein) & env->mie; + return (env->mip | vsgein | vstip) & env->mie; } =20 int riscv_cpu_mirq_pending(CPURISCVState *env) @@ -604,7 +605,7 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t m= ask, uint64_t value) { CPURISCVState *env =3D &cpu->env; CPUState *cs =3D CPU(cpu); - uint64_t gein, vsgein =3D 0, old =3D env->mip; + uint64_t gein, vsgein =3D 0, vstip =3D 0, old =3D env->mip; bool locked =3D false; =20 if (riscv_cpu_virt_enabled(env)) { @@ -612,6 +613,10 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t = mask, uint64_t value) vsgein =3D (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; } =20 + /* No need to update mip for VSTIP */ + mask =3D ((mask =3D=3D MIP_VSTIP) && env->vstime_irq) ? 0 : mask; + vstip =3D env->vstime_irq ? MIP_VSTIP : 0; + if (!qemu_mutex_iothread_locked()) { locked =3D true; qemu_mutex_lock_iothread(); @@ -619,7 +624,7 @@ uint64_t riscv_cpu_update_mip(RISCVCPU *cpu, uint64_t m= ask, uint64_t value) =20 env->mip =3D (env->mip & ~mask) | (value & mask); =20 - if (env->mip | vsgein) { + if (env->mip | vsgein | vstip) { cpu_interrupt(cs, CPU_INTERRUPT_HARD); } else { cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 48d07911ae14..6d1875509ce2 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -567,17 +567,98 @@ static RISCVException sstc(CPURISCVState *env, int cs= rno) return RISCV_EXCP_NONE; } =20 +static RISCVException sstc_hmode(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + + if (!cpu->cfg.ext_sstc || !env->rdtime_fn) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (env->priv =3D=3D PRV_M) { + return RISCV_EXCP_NONE; + } + + if (!(get_field(env->mcounteren, COUNTEREN_TM) & + get_field(env->menvcfg, MENVCFG_STCE))) { + return RISCV_EXCP_ILLEGAL_INST; + } + + if (!(get_field(env->hcounteren, COUNTEREN_TM) & + get_field(env->henvcfg, HENVCFG_STCE))) { + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; + } + + return RISCV_EXCP_NONE; +} + +static RISCVException read_vstimecmp(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->vstimecmp; + + return RISCV_EXCP_NONE; +} + +static RISCVException read_vstimecmph(CPURISCVState *env, int csrno, + target_ulong *val) +{ + *val =3D env->vstimecmp >> 32; + + return RISCV_EXCP_NONE; +} + +static RISCVException write_vstimecmp(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + env->vstimecmp =3D deposit64(env->vstimecmp, 0, 32, (uint64_t)val); + } else { + env->vstimecmp =3D val; + } + + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + + return RISCV_EXCP_NONE; +} + +static RISCVException write_vstimecmph(CPURISCVState *env, int csrno, + target_ulong val) +{ + RISCVCPU *cpu =3D env_archcpu(env); + + env->vstimecmp =3D deposit64(env->vstimecmp, 32, 32, (uint64_t)val); + riscv_timer_write_timecmp(cpu, env->vstimer, env->vstimecmp, + env->htimedelta, MIP_VSTIP); + + return RISCV_EXCP_NONE; +} + static RISCVException read_stimecmp(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->stimecmp; + if (riscv_cpu_virt_enabled(env)) { + *val =3D env->vstimecmp; + } else { + *val =3D env->stimecmp; + } + return RISCV_EXCP_NONE; } =20 static RISCVException read_stimecmph(CPURISCVState *env, int csrno, target_ulong *val) { - *val =3D env->stimecmp >> 32; + if (riscv_cpu_virt_enabled(env)) { + *val =3D env->vstimecmp >> 32; + } else { + *val =3D env->stimecmp >> 32; + } + return RISCV_EXCP_NONE; } =20 @@ -586,6 +667,10 @@ static RISCVException write_stimecmp(CPURISCVState *en= v, int csrno, { RISCVCPU *cpu =3D env_archcpu(env); =20 + if (riscv_cpu_virt_enabled(env)) { + return write_vstimecmp(env, csrno, val); + } + if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { env->stimecmp =3D deposit64(env->stimecmp, 0, 32, (uint64_t)val); } else { @@ -602,6 +687,10 @@ static RISCVException write_stimecmph(CPURISCVState *e= nv, int csrno, { RISCVCPU *cpu =3D env_archcpu(env); =20 + if (riscv_cpu_virt_enabled(env)) { + return write_vstimecmph(env, csrno, val); + } + env->stimecmp =3D deposit64(env->stimecmp, 32, 32, (uint64_t)val); riscv_timer_write_timecmp(cpu, env->stimer, env->stimecmp, 0, MIP_STIP= ); =20 @@ -1601,6 +1690,7 @@ static RISCVException rmw_mip64(CPURISCVState *env, i= nt csrno, if (csrno !=3D CSR_HVIP) { gin =3D get_field(env->hstatus, HSTATUS_VGEIN); old_mip |=3D (env->hgeip & ((target_ulong)1 << gin)) ? MIP_VSEIP := 0; + old_mip |=3D env->vstime_irq ? MIP_VSTIP : 0; } =20 if (ret_val) { @@ -3422,6 +3512,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, [CSR_STIMECMPH] =3D { "stimecmph", sstc, read_stimecmph, write_stimecm= ph, .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VSTIMECMP] =3D { "vstimecmp", sstc_hmode, read_vstimecmp, + write_vstimecmp, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, + [CSR_VSTIMECMPH] =3D { "vstimecmph", sstc_hmode, read_vstimecmph, + write_vstimecmph, + .min_priv_ver =3D PRIV_VERSION_1= _12_0 }, =20 /* Supervisor Protection and Translation */ [CSR_SATP] =3D { "satp", smode, read_satp, write_satp = }, diff --git a/target/riscv/machine.c b/target/riscv/machine.c index ee02bfc18916..d453b401bdfd 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -92,6 +92,7 @@ static const VMStateDescription vmstate_hyper =3D { VMSTATE_UINTTL(env.hgeie, RISCVCPU), VMSTATE_UINTTL(env.hgeip, RISCVCPU), VMSTATE_UINT64(env.htimedelta, RISCVCPU), + VMSTATE_UINT64(env.vstimecmp, RISCVCPU), =20 VMSTATE_UINTTL(env.hvictl, RISCVCPU), VMSTATE_UINT8_ARRAY(env.hviprio, RISCVCPU, 64), diff --git a/target/riscv/time_helper.c b/target/riscv/time_helper.c index f3fb5eac7b7b..8cce667dfd47 100644 --- a/target/riscv/time_helper.c +++ b/target/riscv/time_helper.c @@ -22,6 +22,14 @@ #include "time_helper.h" #include "hw/intc/riscv_aclint.h" =20 +static void riscv_vstimer_cb(void *opaque) +{ + RISCVCPU *cpu =3D opaque; + CPURISCVState *env =3D &cpu->env; + env->vstime_irq =3D 1; + riscv_cpu_update_mip(cpu, MIP_VSTIP, BOOL_TO_MASK(1)); +} + static void riscv_stimer_cb(void *opaque) { RISCVCPU *cpu =3D opaque; @@ -47,10 +55,16 @@ void riscv_timer_write_timecmp(RISCVCPU *cpu, QEMUTimer= *timer, * If we're setting an stimecmp value in the "past", * immediately raise the timer interrupt */ + if (timer_irq =3D=3D MIP_VSTIP) { + env->vstime_irq =3D 1; + } riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(1)); return; } =20 + if (timer_irq =3D=3D MIP_VSTIP) { + env->vstime_irq =3D 0; + } /* Clear the [V]STIP bit in mip */ riscv_cpu_update_mip(cpu, timer_irq, BOOL_TO_MASK(0)); =20 @@ -95,4 +109,6 @@ void riscv_timer_init(RISCVCPU *cpu) env->stimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_stimer_cb, cpu= ); env->stimecmp =3D 0; =20 + env->vstimer =3D timer_new_ns(QEMU_CLOCK_VIRTUAL, &riscv_vstimer_cb, c= pu); + env->vstimecmp =3D 0; } --=20 2.25.1