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Tsirkin" , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , =?UTF-8?q?Herv=C3=A9=20Poussineau?= , Igor Mammedov , Ani Sinha , Bernhard Beschow , Eduardo Habkost , Marcel Apfelbaum , Aurelien Jarno , Paolo Bonzini Subject: [PATCH v2 07/11] hw/acpi/piix4: use qdev gpio to wire up sci_irq Date: Mon, 30 May 2022 13:27:14 +0200 Message-Id: <20220530112718.26582-8-philippe.mathieu.daude@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> References: <20220530112718.26582-1-philippe.mathieu.daude@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1035; envelope-from=philippe.mathieu.daude@gmail.com; helo=mail-pj1-x1035.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1653911906681100001 From: Mark Cave-Ayland Introduce piix4_pm_init() instance init function and use it to initialise the separate qdev gpio for the SCI IRQ. The sci_irq can now be wired up directly using a qdev gpio instead of having to set the IRQ externally in piix4_pm_initfn(). Signed-off-by: Mark Cave-Ayland Reviewed-by: Philippe Mathieu-Daud=C3=A9 Message-Id: <20220528091934.15520-9-mark.cave-ayland@ilande.co.uk> [PMD: Partially squash 20220528091934.15520-8-mark.cave-ayland@ilande.co.uk] Signed-off-by: Philippe Mathieu-Daud=C3=A9 --- hw/acpi/piix4.c | 12 +++++++++--- hw/i386/pc_piix.c | 4 ++-- hw/isa/piix4.c | 6 +++--- include/hw/southbridge/piix.h | 3 +-- 4 files changed, 15 insertions(+), 10 deletions(-) diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 418ec4ee56..fe5ec0a723 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -497,9 +497,15 @@ static void piix4_pm_realize(PCIDevice *dev, Error **e= rrp) piix4_pm_add_properties(s); } =20 +static void piix4_pm_init(Object *obj) +{ + PIIX4PMState *s =3D PIIX4_PM(obj); + + qdev_init_gpio_out(DEVICE(obj), &s->irq, 1); +} + PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled) + qemu_irq smi_irq, bool smm_enabled) { PCIDevice *pci_dev; DeviceState *dev; @@ -511,7 +517,6 @@ PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, u= int32_t smb_io_base, qdev_prop_set_bit(dev, "smm-enabled", smm_enabled); =20 s =3D PIIX4_PM(dev); - s->irq =3D sci_irq; s->smi_irq =3D smi_irq; =20 pci_realize_and_unref(pci_dev, bus, &error_fatal); @@ -663,6 +668,7 @@ static void piix4_pm_class_init(ObjectClass *klass, voi= d *data) static const TypeInfo piix4_pm_info =3D { .name =3D TYPE_PIIX4_PM, .parent =3D TYPE_PCI_DEVICE, + .instance_init =3D piix4_pm_init, .instance_size =3D sizeof(PIIX4PMState), .class_init =3D piix4_pm_class_init, .interfaces =3D (InterfaceInfo[]) { diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index d2ab9f966c..0662bf44a9 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -284,9 +284,9 @@ static void pc_init1(MachineState *machine, PIIX4PMState *piix4_pm; =20 smi_irq =3D qemu_allocate_irq(pc_acpi_smi_interrupt, first_cpu, 0); - piix4_pm =3D piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, - x86ms->gsi[9], smi_irq, + piix4_pm =3D piix4_pm_initfn(pci_bus, piix3_devfn + 3, 0xb100, smi= _irq, x86_machine_is_smm_enabled(x86ms)); + qdev_connect_gpio_out(DEVICE(piix4_pm), 0, x86ms->gsi[9]); pcms->smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(piix4_pm), "i2c"= )); /* TODO: Populate SPD eeprom data. */ smbus_eeprom_init(pcms->smbus, 8, NULL, 0); diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index 33a7015ea3..0b6ea22143 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -311,9 +311,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa= _bus, I2CBus **smbus) =20 pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { - pms =3D piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, - qdev_get_gpio_in_named(dev, "isa", 9), - NULL, 0); + pms =3D piix4_pm_initfn(pci_bus, devfn + 3, 0x1100, NULL, 0); + qdev_connect_gpio_out(DEVICE(pms), 0, + qdev_get_gpio_in_named(dev, "isa", 9)); *smbus =3D I2C_BUS(qdev_get_child_bus(DEVICE(pms), "i2c")); } =20 diff --git a/include/hw/southbridge/piix.h b/include/hw/southbridge/piix.h index f75a4adf5f..105d158f78 100644 --- a/include/hw/southbridge/piix.h +++ b/include/hw/southbridge/piix.h @@ -17,8 +17,7 @@ #include "hw/acpi/piix4.h" =20 PIIX4PMState *piix4_pm_initfn(PCIBus *bus, int devfn, uint32_t smb_io_base, - qemu_irq sci_irq, qemu_irq smi_irq, - bool smm_enabled); + qemu_irq smi_irq, bool smm_enabled); =20 /* PIRQRC[A:D]: PIRQx Route Control Registers */ #define PIIX_PIRQCA 0x60 --=20 2.36.1