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a="274974836" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974836" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993775" From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 1/6] tests/acpi: allow SSDT changes Date: Mon, 30 May 2022 11:40:42 +0800 Message-Id: <20220530034047.730356-2-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1653882395628100001 Content-Type: text/plain; charset="utf-8" Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu Reviewed-by: Igor Mammedov --- tests/qtest/bios-tables-test-allowed-diff.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index dfb8523c8b..eb8bae1407 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1 +1,3 @@ /* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/SSDT.dimmpxm", +"tests/data/acpi/q35/SSDT.dimmpxm", --=20 2.31.1 From nobody Thu May 16 00:23:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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a="274974839" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974839" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993788" From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 2/6] acpi/ssdt: Fix aml_or() and aml_and() in if clause Date: Mon, 30 May 2022 11:40:43 +0800 Message-Id: <20220530034047.730356-3-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1653882206992100005 Content-Type: text/plain; charset="utf-8" In If condition, using bitwise and/or, rather than logical and/or. The result change in AML code: If (((Local6 =3D=3D Zero) | (Arg0 !=3D Local0))) =3D=3D> If (((Local6 =3D=3D Zero) || (Arg0 !=3D Local0))) If (((ObjectType (Arg3) =3D=3D 0x04) & (SizeOf (Arg3) =3D=3D One))) =3D=3D> If (((ObjectType (Arg3) =3D=3D 0x04) && (SizeOf (Arg3) =3D=3D One))) Fixes: 90623ebf603 ("nvdimm acpi: check UUID") Fixes: 4568c948066 ("nvdimm acpi: save arg3 of _DSM method") Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu Reviewed-by: Igor Mammedov --- hw/acpi/nvdimm.c | 7 +++---- 1 file changed, 3 insertions(+), 4 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 0d43da19ea..0ab247a870 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -1040,7 +1040,7 @@ static void nvdimm_build_common_dsm(Aml *dev, =20 uuid_invalid =3D aml_lnot(aml_equal(uuid, expected_uuid)); =20 - unsupport =3D aml_if(aml_or(unpatched, uuid_invalid, NULL)); + unsupport =3D aml_if(aml_lor(unpatched, uuid_invalid)); =20 /* * function 0 is called to inquire what functions are supported by @@ -1072,10 +1072,9 @@ static void nvdimm_build_common_dsm(Aml *dev, * in the DSM Spec. */ pckg =3D aml_arg(3); - ifctx =3D aml_if(aml_and(aml_equal(aml_object_type(pckg), + ifctx =3D aml_if(aml_land(aml_equal(aml_object_type(pckg), aml_int(4 /* Package */)) /* It is a Package? */, - aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? *= /, - NULL)); + aml_equal(aml_sizeof(pckg), aml_int(1)) /* 1 element? *= /)); =20 pckg_index =3D aml_local(2); pckg_buf =3D aml_local(3); --=20 2.31.1 From nobody Thu May 16 00:23:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1653882204; cv=none; d=zohomail.com; s=zohoarc; b=jjFNlVTja3iBSRp7Bex5TTReRHSW+Yu3nYKCgCcQmJL9RNDCcQ+yqjhW79O1Cg4ZoW1NY5G+5+C/fQFsEd9p6zRGuO/xOA+TDJ1qQTydzsH87wCwAvLwQqjEIpK1tRvM5ixpwVR6hNiKkrjyAxTnbibEmVNn7gAHQgHSnH7ULSY= ARC-Message-Signature: i=1; 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bh=mKqNvHjGeoxS+aXxDCIjDV9OBVOE1uvThYOFAHUogmo=; b=SpcnV8cwcm+MLdRBARl6UgHqSkvDve7DS+Vf42oMiB910Ki279neRBZ+ s8PyKOU3VdnC8S5fmiEeG5zRbt3jHU9i0de3hC+Zm7PvvMbAJVVkHo43z E7gjmHwWR8qh2BtOxr3Oi3usv0Y2xfbmeviYfhNXS5pQy0UZxDum8am/H BP5S7Vw9/c+9VHf+9qCS9O8pqDS6B0r3DFo11c+dzh7GlUVOsKvDb6CMh dqfuc/o12Zv5WCpHedX2b7rE1DXTJH4SeMOmn4TJ2zShlrasKt0F8HK14 bVv/Yue/NgVLCd3e47EdJbAOIpH72doAVduxuFI5UWTYHk4QoR65wPWgQ Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974840" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974840" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993796" From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 3/6] acpi/nvdimm: NVDIMM _DSM Spec supports revision 2 Date: Mon, 30 May 2022 11:40:44 +0800 Message-Id: <20220530034047.730356-4-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1653882206754100001 The Intel Optane PMem DSM Interface, Version 2.0 [1], is the up-to-date spec for NVDIMM _DSM definition, which supports revision_id =3D=3D 2. Nevertheless, Rev.2 of NVDIMM _DSM has no functional change on those Label Data _DSM Functions, which are the only ones implemented for vNVDIMM. So, simple change to support this revision_id =3D=3D 2 case. [1] https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- hw/acpi/nvdimm.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 0ab247a870..59b42afcf1 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -849,9 +849,13 @@ nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t v= al, unsigned size) nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", in->revisi= on, in->handle, in->function); =20 - if (in->revision !=3D 0x1 /* Currently we only support DSM Spec Rev1. = */) { - nvdimm_debug("Revision 0x%x is not supported, expect 0x%x.\n", - in->revision, 0x1); + /* + * Current NVDIMM _DSM Spec supports Rev1 and Rev2 + * Intel=C2=AE OptanePersistent Memory Module DSM Interface, Revision = 2.0 + */ + if (in->revision !=3D 0x1 && in->revision !=3D 0x2) { + nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n= ", + in->revision); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_add= r); 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Sun, 29 May 2022 23:41:03 -0400 Received: from orsmga003.jf.intel.com ([10.7.209.27]) by fmsmga103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 29 May 2022 20:40:59 -0700 Received: from sqa-gate.sh.intel.com (HELO robert-clx2.tsp.org) ([10.239.48.212]) by orsmga003.jf.intel.com with ESMTP; 29 May 2022 20:40:56 -0700 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1653882059; x=1685418059; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=gKVEge3bEJXMZpv1Om5gEVWB6AJuAwOAd7P66bJei2E=; b=jfPc4/BuPF3McxxKUkaAuAfr+IkhiQsZkcm/RB22LueJL/A06cbSqOGi HDjUwr96xJJCth5vXAyfNRb1vsZv7M11K61p40YsGDHj065NEtHJvn99V IPQ+ipSrN8buMy4q2shLMdRUr14to7c/L9Wyb8wUyKt/TQxfG8/C+bZ9N S3BCkXNdIMVI7OK3MPNChIxdigZKSY+EASU8pWxRV0qw54d8yz1Ob8+SQ igRbz84Z8apP6GSwVbxLcKD4GGCCnNuRZUlTAorgaX1NTqxcnJdaZi7uC YSztdk7Aa67lsOhihBiRDQe94U3dGtXwx0p4L0Oa0/bMAL3qBWEIWEX6a Q==; X-IronPort-AV: E=McAfee;i="6400,9594,10362"; a="274974848" X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="274974848" X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993814" From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 4/6] nvdimm: Implement ACPI NVDIMM Label Methods Date: Mon, 30 May 2022 11:40:45 +0800 Message-Id: <20220530034047.730356-5-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1653882210833100001 Recent ACPI spec [1] has defined NVDIMM Label Methods _LS{I,R,W}, which depricates corresponding _DSM Functions defined by PMEM _DSM Interface spec [2]. In this implementation, we do 2 things 1. Generalize the QEMU<->ACPI BIOS NVDIMM interface, wrap it with ACPI method dispatch, _DSM is one of the branches. This also paves the way for adding other ACPI methods for NVDIMM. 2. Add _LS{I,R,W} method in each NVDIMM device in SSDT. ASL form of SSDT changes can be found in next test/qtest/bios-table-test commit message. [1] ACPI Spec v6.4, 6.5.10 NVDIMM Label Methods https://uefi.org/sites/default/files/resources/ACPI_Spec_6_4_Jan22.pdf [2] Intel PMEM _DSM Interface Spec v2.0, 3.10 Deprecated Functions https://pmem.io/documents/IntelOptanePMem_DSM_Interface-V2.0.pdf Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- hw/acpi/nvdimm.c | 424 +++++++++++++++++++++++++++++++--------- include/hw/mem/nvdimm.h | 6 + 2 files changed, 338 insertions(+), 92 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 59b42afcf1..50ee85866b 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -416,17 +416,22 @@ static void nvdimm_build_nfit(NVDIMMState *state, GAr= ray *table_offsets, =20 #define NVDIMM_DSM_MEMORY_SIZE 4096 =20 -struct NvdimmDsmIn { +struct NvdimmMthdIn { uint32_t handle; + uint32_t method; + uint8_t args[4088]; +} QEMU_PACKED; +typedef struct NvdimmMthdIn NvdimmMthdIn; +struct NvdimmDsmIn { uint32_t revision; uint32_t function; /* the remaining size in the page is used by arg3. */ union { - uint8_t arg3[4084]; + uint8_t arg3[4080]; }; } QEMU_PACKED; typedef struct NvdimmDsmIn NvdimmDsmIn; -QEMU_BUILD_BUG_ON(sizeof(NvdimmDsmIn) !=3D NVDIMM_DSM_MEMORY_SIZE); +QEMU_BUILD_BUG_ON(sizeof(NvdimmMthdIn) !=3D NVDIMM_DSM_MEMORY_SIZE); =20 struct NvdimmDsmOut { /* the size of buffer filled by QEMU. */ @@ -470,7 +475,8 @@ struct NvdimmFuncGetLabelDataIn { } QEMU_PACKED; typedef struct NvdimmFuncGetLabelDataIn NvdimmFuncGetLabelDataIn; QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncGetLabelDataIn) + - offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE); + offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, arg= s) > + NVDIMM_DSM_MEMORY_SIZE); =20 struct NvdimmFuncGetLabelDataOut { /* the size of buffer filled by QEMU. */ @@ -488,14 +494,16 @@ struct NvdimmFuncSetLabelDataIn { } QEMU_PACKED; typedef struct NvdimmFuncSetLabelDataIn NvdimmFuncSetLabelDataIn; QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncSetLabelDataIn) + - offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE); + offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, arg= s) > + NVDIMM_DSM_MEMORY_SIZE); =20 struct NvdimmFuncReadFITIn { uint32_t offset; /* the offset into FIT buffer. */ } QEMU_PACKED; typedef struct NvdimmFuncReadFITIn NvdimmFuncReadFITIn; QEMU_BUILD_BUG_ON(sizeof(NvdimmFuncReadFITIn) + - offsetof(NvdimmDsmIn, arg3) > NVDIMM_DSM_MEMORY_SIZE); + offsetof(NvdimmDsmIn, arg3) + offsetof(NvdimmMthdIn, arg= s) > + NVDIMM_DSM_MEMORY_SIZE); =20 struct NvdimmFuncReadFITOut { /* the size of buffer filled by QEMU. */ @@ -636,7 +644,8 @@ static uint32_t nvdimm_get_max_xfer_label_size(void) * the max data ACPI can write one time which is transferred by * 'Set Namespace Label Data' function. */ - max_set_size =3D dsm_memory_size - offsetof(NvdimmDsmIn, arg3) - + max_set_size =3D dsm_memory_size - offsetof(NvdimmMthdIn, args) - + offsetof(NvdimmDsmIn, arg3) - sizeof(NvdimmFuncSetLabelDataIn); =20 return MIN(max_get_size, max_set_size); @@ -697,16 +706,15 @@ static uint32_t nvdimm_rw_label_data_check(NVDIMMDevi= ce *nvdimm, /* * DSM Spec Rev1 4.5 Get Namespace Label Data (Function Index 5). */ -static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *i= n, - hwaddr dsm_mem_addr) +static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvdimm, + NvdimmFuncGetLabelDataIn *get_label_da= ta, + hwaddr dsm_mem_addr) { NVDIMMClass *nvc =3D NVDIMM_GET_CLASS(nvdimm); - NvdimmFuncGetLabelDataIn *get_label_data; NvdimmFuncGetLabelDataOut *get_label_data_out; uint32_t status; int size; =20 - get_label_data =3D (NvdimmFuncGetLabelDataIn *)in->arg3; get_label_data->offset =3D le32_to_cpu(get_label_data->offset); get_label_data->length =3D le32_to_cpu(get_label_data->length); =20 @@ -737,15 +745,13 @@ static void nvdimm_dsm_get_label_data(NVDIMMDevice *n= vdimm, NvdimmDsmIn *in, /* * DSM Spec Rev1 4.6 Set Namespace Label Data (Function Index 6). */ -static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, NvdimmDsmIn *i= n, +static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvdimm, + NvdimmFuncSetLabelDataIn *set_label_= data, hwaddr dsm_mem_addr) { NVDIMMClass *nvc =3D NVDIMM_GET_CLASS(nvdimm); - NvdimmFuncSetLabelDataIn *set_label_data; uint32_t status; =20 - set_label_data =3D (NvdimmFuncSetLabelDataIn *)in->arg3; - set_label_data->offset =3D le32_to_cpu(set_label_data->offset); set_label_data->length =3D le32_to_cpu(set_label_data->length); =20 @@ -760,19 +766,21 @@ static void nvdimm_dsm_set_label_data(NVDIMMDevice *n= vdimm, NvdimmDsmIn *in, } =20 assert(offsetof(NvdimmDsmIn, arg3) + sizeof(*set_label_data) + - set_label_data->length <=3D NVDIMM_DSM_MEMORY_SIZE); + set_label_data->length <=3D NVDIMM_DSM_MEMORY_SIZE - + offsetof(NvdimmMthdIn, args)); =20 nvc->write_label_data(nvdimm, set_label_data->in_buf, set_label_data->length, set_label_data->offset); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_SUCCESS, dsm_mem_addr); } =20 -static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr dsm_mem_addr) +static void nvdimm_dsm_device(uint32_t nv_handle, NvdimmDsmIn *dsm_in, + hwaddr dsm_mem_addr) { - NVDIMMDevice *nvdimm =3D nvdimm_get_device_by_handle(in->handle); + NVDIMMDevice *nvdimm =3D nvdimm_get_device_by_handle(nv_handle); =20 /* See the comments in nvdimm_dsm_root(). */ - if (!in->function) { + if (!dsm_in->function) { uint32_t supported_func =3D 0; =20 if (nvdimm && nvdimm->label_size) { @@ -794,7 +802,7 @@ static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr d= sm_mem_addr) } =20 /* Encode DSM function according to DSM Spec Rev1. */ - switch (in->function) { + switch (dsm_in->function) { case 4 /* Get Namespace Label Size */: if (nvdimm->label_size) { nvdimm_dsm_label_size(nvdimm, dsm_mem_addr); @@ -803,13 +811,17 @@ static void nvdimm_dsm_device(NvdimmDsmIn *in, hwaddr= dsm_mem_addr) break; case 5 /* Get Namespace Label Data */: if (nvdimm->label_size) { - nvdimm_dsm_get_label_data(nvdimm, in, dsm_mem_addr); + nvdimm_dsm_get_label_data(nvdimm, + (NvdimmFuncGetLabelDataIn *)dsm_in->= arg3, + dsm_mem_addr); return; } break; case 0x6 /* Set Namespace Label Data */: if (nvdimm->label_size) { - nvdimm_dsm_set_label_data(nvdimm, in, dsm_mem_addr); + nvdimm_dsm_set_label_data(nvdimm, + (NvdimmFuncSetLabelDataIn *)dsm_in->arg3, + dsm_mem_addr); return; } break; @@ -819,67 +831,128 @@ static void nvdimm_dsm_device(NvdimmDsmIn *in, hwadd= r dsm_mem_addr) } =20 static uint64_t -nvdimm_dsm_read(void *opaque, hwaddr addr, unsigned size) +nvdimm_method_read(void *opaque, hwaddr addr, unsigned size) { - nvdimm_debug("BUG: we never read _DSM IO Port.\n"); + nvdimm_debug("BUG: we never read NVDIMM Method IO Port.\n"); return 0; } =20 static void -nvdimm_dsm_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +nvdimm_dsm_handle(void *opaque, NvdimmMthdIn *method_in, hwaddr dsm_mem_ad= dr) { NVDIMMState *state =3D opaque; - NvdimmDsmIn *in; - hwaddr dsm_mem_addr =3D val; + NvdimmDsmIn *dsm_in =3D (NvdimmDsmIn *)method_in->args; =20 nvdimm_debug("dsm memory address 0x%" HWADDR_PRIx ".\n", dsm_mem_addr); =20 - /* - * The DSM memory is mapped to guest address space so an evil guest - * can change its content while we are doing DSM emulation. Avoid - * this by copying DSM memory to QEMU local memory. - */ - in =3D g_new(NvdimmDsmIn, 1); - cpu_physical_memory_read(dsm_mem_addr, in, sizeof(*in)); - - in->revision =3D le32_to_cpu(in->revision); - in->function =3D le32_to_cpu(in->function); - in->handle =3D le32_to_cpu(in->handle); - - nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", in->revisi= on, - in->handle, in->function); + dsm_in->revision =3D le32_to_cpu(dsm_in->revision); + dsm_in->function =3D le32_to_cpu(dsm_in->function); =20 + nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", + dsm_in->revision, method_in->handle, dsm_in->function); /* * Current NVDIMM _DSM Spec supports Rev1 and Rev2 * Intel=C2=AE OptanePersistent Memory Module DSM Interface, Revision = 2.0 */ - if (in->revision !=3D 0x1 && in->revision !=3D 0x2) { + if (dsm_in->revision !=3D 0x1 && dsm_in->revision !=3D 0x2) { nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n= ", - in->revision); + dsm_in->revision); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_add= r); - goto exit; + return; } =20 - if (in->handle =3D=3D NVDIMM_QEMU_RSVD_HANDLE_ROOT) { - nvdimm_dsm_handle_reserved_root_method(state, in, dsm_mem_addr); - goto exit; + if (method_in->handle =3D=3D NVDIMM_QEMU_RSVD_HANDLE_ROOT) { + nvdimm_dsm_handle_reserved_root_method(state, dsm_in, dsm_mem_addr= ); + return; } =20 /* Handle 0 is reserved for NVDIMM Root Device. */ - if (!in->handle) { - nvdimm_dsm_root(in, dsm_mem_addr); - goto exit; + if (!method_in->handle) { + nvdimm_dsm_root(dsm_in, dsm_mem_addr); + return; } =20 - nvdimm_dsm_device(in, dsm_mem_addr); + nvdimm_dsm_device(method_in->handle, dsm_in, dsm_mem_addr); +} =20 -exit: - g_free(in); +static void nvdimm_lsi_handle(uint32_t nv_handle, hwaddr dsm_mem_addr) +{ + NVDIMMDevice *nvdimm =3D nvdimm_get_device_by_handle(nv_handle); + + if (nvdimm->label_size) { + nvdimm_dsm_label_size(nvdimm, dsm_mem_addr); + } + + return; +} + +static void nvdimm_lsr_handle(uint32_t nv_handle, + void *data, + hwaddr dsm_mem_addr) +{ + NVDIMMDevice *nvdimm =3D nvdimm_get_device_by_handle(nv_handle); + NvdimmFuncGetLabelDataIn *get_label_data =3D data; + + if (nvdimm->label_size) { + nvdimm_dsm_get_label_data(nvdimm, get_label_data, dsm_mem_addr); + } + return; +} + +static void nvdimm_lsw_handle(uint32_t nv_handle, + void *data, + hwaddr dsm_mem_addr) +{ + NVDIMMDevice *nvdimm =3D nvdimm_get_device_by_handle(nv_handle); + NvdimmFuncSetLabelDataIn *set_label_data =3D data; + + if (nvdimm->label_size) { + nvdimm_dsm_set_label_data(nvdimm, set_label_data, dsm_mem_addr); + } + return; +} + +static void +nvdimm_method_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) +{ + NvdimmMthdIn *method_in; + hwaddr dsm_mem_addr =3D val; + + /* + * The DSM memory is mapped to guest address space so an evil guest + * can change its content while we are doing DSM emulation. Avoid + * this by copying DSM memory to QEMU local memory. + */ + method_in =3D g_new(NvdimmMthdIn, 1); + cpu_physical_memory_read(dsm_mem_addr, method_in, sizeof(*method_in)); + + method_in->handle =3D le32_to_cpu(method_in->handle); + method_in->method =3D le32_to_cpu(method_in->method); + + switch (method_in->method) { + case NVDIMM_METHOD_DSM: + nvdimm_dsm_handle(opaque, method_in, dsm_mem_addr); + break; + case NVDIMM_METHOD_LSI: + nvdimm_lsi_handle(method_in->handle, dsm_mem_addr); + break; + case NVDIMM_METHOD_LSR: + nvdimm_lsr_handle(method_in->handle, method_in->args, dsm_mem_addr= ); + break; + case NVDIMM_METHOD_LSW: + nvdimm_lsw_handle(method_in->handle, method_in->args, dsm_mem_addr= ); + break; + default: + nvdimm_debug("%s: Unkown method 0x%x\n", __func__, method_in->meth= od); + break; + } + + g_free(method_in); } =20 -static const MemoryRegionOps nvdimm_dsm_ops =3D { - .read =3D nvdimm_dsm_read, - .write =3D nvdimm_dsm_write, +static const MemoryRegionOps nvdimm_method_ops =3D { + .read =3D nvdimm_method_read, + .write =3D nvdimm_method_write, .endianness =3D DEVICE_LITTLE_ENDIAN, .valid =3D { .min_access_size =3D 4, @@ -899,12 +972,12 @@ void nvdimm_init_acpi_state(NVDIMMState *state, Memor= yRegion *io, FWCfgState *fw_cfg, Object *owner) { state->dsm_io =3D dsm_io; - memory_region_init_io(&state->io_mr, owner, &nvdimm_dsm_ops, state, + memory_region_init_io(&state->io_mr, owner, &nvdimm_method_ops, state, "nvdimm-acpi-io", dsm_io.bit_width >> 3); memory_region_add_subregion(io, dsm_io.address, &state->io_mr); =20 state->dsm_mem =3D g_array_new(false, true /* clear */, 1); - acpi_data_push(state->dsm_mem, sizeof(NvdimmDsmIn)); + acpi_data_push(state->dsm_mem, sizeof(NvdimmMthdIn)); fw_cfg_add_file(fw_cfg, NVDIMM_DSM_MEM_FILE, state->dsm_mem->data, state->dsm_mem->len); =20 @@ -918,13 +991,22 @@ void nvdimm_init_acpi_state(NVDIMMState *state, Memor= yRegion *io, #define NVDIMM_DSM_IOPORT "NPIO" =20 #define NVDIMM_DSM_NOTIFY "NTFI" +#define NVDIMM_DSM_METHOD "MTHD" #define NVDIMM_DSM_HANDLE "HDLE" #define NVDIMM_DSM_REVISION "REVS" #define NVDIMM_DSM_FUNCTION "FUNC" #define NVDIMM_DSM_ARG3 "FARG" =20 -#define NVDIMM_DSM_OUT_BUF_SIZE "RLEN" -#define NVDIMM_DSM_OUT_BUF "ODAT" +#define NVDIMM_DSM_OFFSET "OFST" +#define NVDIMM_DSM_TRANS_LEN "TRSL" +#define NVDIMM_DSM_IN_BUFF "IDAT" + +#define NVDIMM_DSM_OUT_BUF_SIZE "RLEN" +#define NVDIMM_DSM_OUT_BUF "ODAT" +#define NVDIMM_DSM_OUT_STATUS "STUS" +#define NVDIMM_DSM_OUT_LSA_SIZE "SIZE" +#define NVDIMM_DSM_OUT_MAX_TRANS "MAXT" + =20 #define NVDIMM_DSM_RFIT_STATUS "RSTA" =20 @@ -938,7 +1020,6 @@ static void nvdimm_build_common_dsm(Aml *dev, Aml *pckg, *pckg_index, *pckg_buf, *field, *dsm_out_buf, *dsm_out_buf_= size; Aml *whilectx, *offset; uint8_t byte_list[1]; - AmlRegionSpace rs; =20 method =3D aml_method(NVDIMM_COMMON_DSM, 5, AML_SERIALIZED); uuid =3D aml_arg(0); @@ -949,37 +1030,15 @@ static void nvdimm_build_common_dsm(Aml *dev, =20 aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), dsm_mem)); =20 - if (nvdimm_state->dsm_io.space_id =3D=3D AML_AS_SYSTEM_IO) { - rs =3D AML_SYSTEM_IO; - } else { - rs =3D AML_SYSTEM_MEMORY; - } - - /* map DSM memory and IO into ACPI namespace. */ - aml_append(method, aml_operation_region(NVDIMM_DSM_IOPORT, rs, - aml_int(nvdimm_state->dsm_io.address), - nvdimm_state->dsm_io.bit_width >> 3)); aml_append(method, aml_operation_region(NVDIMM_DSM_MEMORY, - AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmDsmIn))); - - /* - * DSM notifier: - * NVDIMM_DSM_NOTIFY: write the address of DSM memory and notify QEMU = to - * emulate the access. - * - * It is the IO port so that accessing them will cause VM-exit, the - * control will be transferred to QEMU. - */ - field =3D aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK, - AML_PRESERVE); - aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY, - nvdimm_state->dsm_io.bit_width)); - aml_append(method, field); + AML_SYSTEM_MEMORY, dsm_mem, sizeof(NvdimmMthdIn))); =20 /* * DSM input: * NVDIMM_DSM_HANDLE: store device's handle, it's zero if the _DSM call * happens on NVDIMM Root Device. + * NVDIMM_DSM_METHOD: ACPI method indicator, to distinguish _DSM and + * other ACPI methods. * NVDIMM_DSM_REVISION: store the Arg1 of _DSM call. * NVDIMM_DSM_FUNCTION: store the Arg2 of _DSM call. * NVDIMM_DSM_ARG3: store the Arg3 of _DSM call which is a Package @@ -991,13 +1050,16 @@ static void nvdimm_build_common_dsm(Aml *dev, field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, AML_PRESERVE); aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, - sizeof(typeof_field(NvdimmDsmIn, handle)) * BITS_PER_BYTE)); + sizeof(typeof_field(NvdimmMthdIn, handle)) * BITS_PER_BYTE)= ); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * BITS_PER_BYTE)= ); aml_append(field, aml_named_field(NVDIMM_DSM_REVISION, sizeof(typeof_field(NvdimmDsmIn, revision)) * BITS_PER_BYTE= )); aml_append(field, aml_named_field(NVDIMM_DSM_FUNCTION, sizeof(typeof_field(NvdimmDsmIn, function)) * BITS_PER_BYTE= )); aml_append(field, aml_named_field(NVDIMM_DSM_ARG3, - (sizeof(NvdimmDsmIn) - offsetof(NvdimmDsmIn, arg3)) * BITS_PER_BY= TE)); + (sizeof(NvdimmMthdIn) - offsetof(NvdimmMthdIn, args) - + offsetof(NvdimmDsmIn, arg3)) * BITS_PER_BYTE)); aml_append(method, field); =20 /* @@ -1065,6 +1127,7 @@ static void nvdimm_build_common_dsm(Aml *dev, * it reserves 0 for root device and is the handle for NVDIMM devices. * See the comments in nvdimm_slot_to_handle(). */ + aml_append(method, aml_store(aml_int(0), aml_name(NVDIMM_DSM_METHOD))); aml_append(method, aml_store(handle, aml_name(NVDIMM_DSM_HANDLE))); aml_append(method, aml_store(aml_arg(1), aml_name(NVDIMM_DSM_REVISION)= )); aml_append(method, aml_store(function, aml_name(NVDIMM_DSM_FUNCTION))); @@ -1250,6 +1313,7 @@ static void nvdimm_build_fit(Aml *dev) static void nvdimm_build_nvdimm_devices(Aml *root_dev, uint32_t ram_slots) { uint32_t slot; + Aml *method, *pkg, *field; =20 for (slot =3D 0; slot < ram_slots; slot++) { uint32_t handle =3D nvdimm_slot_to_handle(slot); @@ -1266,6 +1330,155 @@ static void nvdimm_build_nvdimm_devices(Aml *root_d= ev, uint32_t ram_slots) * table NFIT or _FIT. */ aml_append(nvdimm_dev, aml_name_decl("_ADR", aml_int(handle))); + aml_append(nvdimm_dev, aml_operation_region(NVDIMM_DSM_MEMORY, + AML_SYSTEM_MEMORY, aml_name(NVDIMM_ACPI_MEM_ADDR), + sizeof(NvdimmMthdIn))); + + /* ACPI 6.4: 6.5.10 NVDIMM Label Methods, _LS{I,R,W} */ + + /* Begin of _LSI Block */ + method =3D aml_method("_LSI", 0, AML_SERIALIZED); + /* _LSI Input field */ + field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, + sizeof(typeof_field(NvdimmMthdIn, handle)) * BITS_PER_B= YTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * BITS_PER_B= YTE)); + aml_append(method, field); + + /* _LSI Output field */ + field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, len)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_STATUS, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, + func_ret_status)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_LSA_SIZE, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, label_si= ze)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_MAX_TRANS, + sizeof(typeof_field(NvdimmFuncGetLabelSizeOut, max_xfer= )) * + BITS_PER_BYTE)); + aml_append(method, field); + + aml_append(method, aml_store(aml_int(handle), + aml_name(NVDIMM_DSM_HANDLE))); + aml_append(method, aml_store(aml_int(0x100), + aml_name(NVDIMM_DSM_METHOD))); + aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), + aml_name(NVDIMM_DSM_NOTIFY))); + + pkg =3D aml_package(3); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_STATUS)); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_LSA_SIZE)); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_MAX_TRANS)); + + aml_append(method, aml_name_decl("RPKG", pkg)); + + aml_append(method, aml_return(aml_name("RPKG"))); + aml_append(nvdimm_dev, method); /* End of _LSI Block */ + + + /* Begin of _LSR Block */ + method =3D aml_method("_LSR", 2, AML_SERIALIZED); + + /* _LSR Input field */ + field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, + sizeof(typeof_field(NvdimmMthdIn, handle)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OFFSET, + sizeof(typeof_field(NvdimmFuncGetLabelDataIn, offset)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_TRANS_LEN, + sizeof(typeof_field(NvdimmFuncGetLabelDataIn, length)) * + BITS_PER_BYTE)); + aml_append(method, field); + + /* _LSR Output field */ + field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE, + sizeof(typeof_field(NvdimmFuncGetLabelDataOut, len)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_STATUS, + sizeof(typeof_field(NvdimmFuncGetLabelDataOut, + func_ret_status)) * BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF, + (NVDIMM_DSM_MEMORY_SIZE - + offsetof(NvdimmFuncGetLabelDataOut, out_buf)) * + BITS_PER_BYTE)); + aml_append(method, field); + + aml_append(method, aml_store(aml_int(handle), + aml_name(NVDIMM_DSM_HANDLE))); + aml_append(method, aml_store(aml_int(0x101), + aml_name(NVDIMM_DSM_METHOD))); + aml_append(method, aml_store(aml_arg(0), aml_name(NVDIMM_DSM_OFFSE= T))); + aml_append(method, aml_store(aml_arg(1), + aml_name(NVDIMM_DSM_TRANS_LEN))); + aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), + aml_name(NVDIMM_DSM_NOTIFY))); + + aml_append(method, aml_store(aml_shiftleft(aml_arg(1), aml_int(3)), + aml_local(1))); + aml_append(method, aml_create_field(aml_name(NVDIMM_DSM_OUT_BUF), + aml_int(0), aml_local(1), "OBUF")); + + pkg =3D aml_package(2); + aml_append(pkg, aml_name(NVDIMM_DSM_OUT_STATUS)); + aml_append(pkg, aml_name("OBUF")); + aml_append(method, aml_name_decl("RPKG", pkg)); + + aml_append(method, aml_return(aml_name("RPKG"))); + aml_append(nvdimm_dev, method); /* End of _LSR Block */ + + /* Begin of _LSW Block */ + method =3D aml_method("_LSW", 3, AML_SERIALIZED); + /* _LSW Input field */ + field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_HANDLE, + sizeof(typeof_field(NvdimmMthdIn, handle)) * BITS_PER_B= YTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_METHOD, + sizeof(typeof_field(NvdimmMthdIn, method)) * BITS_PER_B= YTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OFFSET, + sizeof(typeof_field(NvdimmFuncSetLabelDataIn, offset)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_TRANS_LEN, + sizeof(typeof_field(NvdimmFuncSetLabelDataIn, length)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_IN_BUFF, 32640)); + aml_append(method, field); + + /* _LSW Output field */ + field =3D aml_field(NVDIMM_DSM_MEMORY, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_BUF_SIZE, + sizeof(typeof_field(NvdimmDsmFuncNoPayloadOut, len)) * + BITS_PER_BYTE)); + aml_append(field, aml_named_field(NVDIMM_DSM_OUT_STATUS, + sizeof(typeof_field(NvdimmDsmFuncNoPayloadOut, + func_ret_status)) * BITS_PER_BYTE)); + aml_append(method, field); + + aml_append(method, aml_store(aml_int(handle), aml_name(NVDIMM_DSM_= HANDLE))); + aml_append(method, aml_store(aml_int(0x102), aml_name(NVDIMM_DSM_M= ETHOD))); + aml_append(method, aml_store(aml_arg(0), aml_name(NVDIMM_DSM_OFFSE= T))); + aml_append(method, aml_store(aml_arg(1), aml_name(NVDIMM_DSM_TRANS= _LEN))); + aml_append(method, aml_store(aml_arg(2), aml_name(NVDIMM_DSM_IN_BU= FF))); + aml_append(method, aml_store(aml_name(NVDIMM_ACPI_MEM_ADDR), + aml_name(NVDIMM_DSM_NOTIFY))); + + aml_append(method, aml_return(aml_name(NVDIMM_DSM_OUT_STATUS))); + aml_append(nvdimm_dev, method); /* End of _LSW Block */ =20 nvdimm_build_device_dsm(nvdimm_dev, handle); aml_append(root_dev, nvdimm_dev); @@ -1278,7 +1491,8 @@ static void nvdimm_build_ssdt(GArray *table_offsets, = GArray *table_data, uint32_t ram_slots, const char *oem_id) { int mem_addr_offset; - Aml *ssdt, *sb_scope, *dev; + Aml *ssdt, *sb_scope, *dev, *field; + AmlRegionSpace rs; AcpiTable table =3D { .sig =3D "SSDT", .rev =3D 1, .oem_id =3D oem_id, .oem_table_id =3D "NVDIMM" }; =20 @@ -1286,6 +1500,9 @@ static void nvdimm_build_ssdt(GArray *table_offsets, = GArray *table_data, =20 acpi_table_begin(&table, table_data); ssdt =3D init_aml_allocator(); + + mem_addr_offset =3D build_append_named_dword(table_data, + NVDIMM_ACPI_MEM_ADDR); sb_scope =3D aml_scope("\\_SB"); =20 dev =3D aml_device("NVDR"); @@ -1303,6 +1520,31 @@ static void nvdimm_build_ssdt(GArray *table_offsets,= GArray *table_data, */ aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0012"))); =20 + if (nvdimm_state->dsm_io.space_id =3D=3D AML_AS_SYSTEM_IO) { + rs =3D AML_SYSTEM_IO; + } else { + rs =3D AML_SYSTEM_MEMORY; + } + + /* map DSM memory and IO into ACPI namespace. */ + aml_append(dev, aml_operation_region(NVDIMM_DSM_IOPORT, rs, + aml_int(nvdimm_state->dsm_io.address), + nvdimm_state->dsm_io.bit_width >> 3)); + + /* + * DSM notifier: + * NVDIMM_DSM_NOTIFY: write the address of DSM memory and notify QEMU = to + * emulate the access. + * + * It is the IO port so that accessing them will cause VM-exit, the + * control will be transferred to QEMU. + */ + field =3D aml_field(NVDIMM_DSM_IOPORT, AML_DWORD_ACC, AML_NOLOCK, + AML_PRESERVE); + aml_append(field, aml_named_field(NVDIMM_DSM_NOTIFY, + nvdimm_state->dsm_io.bit_width)); + aml_append(dev, field); + nvdimm_build_common_dsm(dev, nvdimm_state); =20 /* 0 is reserved for root device. */ @@ -1316,12 +1558,10 @@ static void nvdimm_build_ssdt(GArray *table_offsets= , GArray *table_data, =20 /* copy AML table into ACPI tables blob and patch header there */ g_array_append_vals(table_data, ssdt->buf->data, ssdt->buf->len); - mem_addr_offset =3D build_append_named_dword(table_data, - NVDIMM_ACPI_MEM_ADDR); =20 bios_linker_loader_alloc(linker, NVDIMM_DSM_MEM_FILE, nvdimm_state->dsm_mem, - sizeof(NvdimmDsmIn), false /* high memory */); + sizeof(NvdimmMthdIn), false /* high memory */= ); bios_linker_loader_add_pointer(linker, ACPI_BUILD_TABLE_FILE, mem_addr_offset, sizeof(uint32_t), NVDIMM_DSM_MEM_FILE, 0); diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index cf8f59be44..0206b6125b 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -37,6 +37,12 @@ } \ } while (0) =20 +/* NVDIMM ACPI Methods */ +#define NVDIMM_METHOD_DSM 0 +#define NVDIMM_METHOD_LSI 0x100 +#define NVDIMM_METHOD_LSR 0x101 +#define NVDIMM_METHOD_LSW 0x102 + /* * The minimum label data size is required by NVDIMM Namespace * specification, see the chapter 2 Namespaces: --=20 2.31.1 From nobody Thu May 16 00:23:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; a=rsa-sha256; t=1653882400; cv=none; d=zohomail.com; s=zohoarc; b=jvioDdCBAN9VSjYVKZIiLlCJmcHCDbvZrlXyYigD5B7uW/DnV8GqKIxSMj/2zRVth7v/lIxQLoW+/37oZ4jAyfsxUnvoId8r5N9JYXEyEU7hXD2I+XkxbqorWS/VF9n1w4Wbz4K6s8Dvf35B05vYT8l4h+o5HG5Yq2wFJWyWWEM= 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[QEMU PATCH v2 5/6] test/acpi/bios-tables-test: SSDT: update golden master binaries Date: Mon, 30 May 2022 11:40:46 +0800 Message-Id: <20220530034047.730356-6-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1653882401642100001 Content-Type: text/plain; charset="utf-8" Diff in disassembled ASL files @@ -1,100 +1,103 @@ /* * Intel ACPI Component Architecture * AML/ASL+ Disassembler version 20190509 (64-bit version) * Copyright (c) 2000 - 2019 Intel Corporation * * Disassembling to symbolic ASL+ operators * - * Disassembly of tests/data/acpi/q35/SSDT.dimmpxm, Wed May 25 11:02:18 20= 22 + * Disassembly of /tmp/aml-U0ONM1, Wed May 25 11:02:18 2022 * * Original Table Header: * Signature "SSDT" - * Length 0x000002DE (734) + * Length 0x00000725 (1829) * Revision 0x01 - * Checksum 0x46 + * Checksum 0xEA * OEM ID "BOCHS " * OEM Table ID "NVDIMM" * OEM Revision 0x00000001 (1) * Compiler ID "BXPC" * Compiler Version 0x00000001 (1) */ DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) { + Name (MEMA, 0x07FFF000) Scope (\_SB) { Device (NVDR) { Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Har= dware ID + OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + Method (NCAL, 5, Serialized) { Local6 =3D MEMA /* \MEMA */ - OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) OperationRegion (NRAM, SystemMemory, Local6, 0x1000) - Field (NPIO, DWordAcc, NoLock, Preserve) - { - NTFI, 32 - } - Field (NRAM, DWordAcc, NoLock, Preserve) { HDLE, 32, + MTHD, 32, REVS, 32, FUNC, 32, - FARG, 32672 + FARG, 32640 } Field (NRAM, DWordAcc, NoLock, Preserve) { RLEN, 32, ODAT, 32736 } If ((Arg4 =3D=3D Zero)) { Local0 =3D ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75c= ba") } ElseIf ((Arg4 =3D=3D 0x00010000)) { Local0 =3D ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd= 62") } Else { Local0 =3D ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a= 66") } - If (((Local6 =3D=3D Zero) | (Arg0 !=3D Local0))) + If (((Local6 =3D=3D Zero) || (Arg0 !=3D Local0))) { If ((Arg2 =3D=3D Zero)) { Return (Buffer (One) { 0x00 = // . }) } Return (Buffer (One) { 0x01 = // . }) } + MTHD =3D Zero HDLE =3D Arg4 REVS =3D Arg1 FUNC =3D Arg2 - If (((ObjectType (Arg3) =3D=3D 0x04) & (SizeOf (Arg3) =3D= =3D One))) + If (((ObjectType (Arg3) =3D=3D 0x04) && (SizeOf (Arg3) =3D= =3D One))) { Local2 =3D Arg3 [Zero] Local3 =3D DerefOf (Local2) FARG =3D Local3 } NTFI =3D Local6 Local1 =3D (RLEN - 0x04) If ((Local1 < 0x08)) { Local2 =3D Zero Name (TBUF, Buffer (One) { 0x00 = // . }) Local7 =3D Buffer (Zero){} @@ -161,45 +164,304 @@ Else { If ((Local1 =3D=3D Zero)) { Return (Local2) } Local3 +=3D Local1 Concatenate (Local2, Local0, Local2) } } } Device (NV00) { Name (_ADR, One) // _ADR: Address + OperationRegion (NRAM, SystemMemory, MEMA, 0x1000) + Method (_LSI, 0, Serialized) // _LSI: Label Storage Infor= mation + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + SIZE, 32, + MAXT, 32 + } + + HDLE =3D One + MTHD =3D 0x0100 + NTFI =3D MEMA /* \MEMA */ + Name (RPKG, Package (0x03) + { + STUS, + SIZE, + MAXT + }) + Return (RPKG) /* \_SB_.NVDR.NV00._LSI.RPKG */ + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + ODAT, 32704 + } + + HDLE =3D One + MTHD =3D 0x0101 + OFST =3D Arg0 + TRSL =3D Arg1 + NTFI =3D MEMA /* \MEMA */ + Local1 =3D (Arg1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Name (RPKG, Package (0x02) + { + STUS, + OBUF + }) + Return (RPKG) /* \_SB_.NVDR.NV00._LSR.RPKG */ + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32, + IDAT, 32640 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32 + } + + HDLE =3D One + MTHD =3D 0x0102 + OFST =3D Arg0 + TRSL =3D Arg1 + IDAT =3D Arg2 + NTFI =3D MEMA /* \MEMA */ + Return (STUS) /* \_SB_.NVDR.NV00._LSW.STUS */ + } + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific = Method { Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) } } Device (NV01) { Name (_ADR, 0x02) // _ADR: Address + OperationRegion (NRAM, SystemMemory, MEMA, 0x1000) + Method (_LSI, 0, Serialized) // _LSI: Label Storage Infor= mation + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + SIZE, 32, + MAXT, 32 + } + + HDLE =3D 0x02 + MTHD =3D 0x0100 + NTFI =3D MEMA /* \MEMA */ + Name (RPKG, Package (0x03) + { + STUS, + SIZE, + MAXT + }) + Return (RPKG) /* \_SB_.NVDR.NV01._LSI.RPKG */ + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + ODAT, 32704 + } + + HDLE =3D 0x02 + MTHD =3D 0x0101 + OFST =3D Arg0 + TRSL =3D Arg1 + NTFI =3D MEMA /* \MEMA */ + Local1 =3D (Arg1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Name (RPKG, Package (0x02) + { + STUS, + OBUF + }) + Return (RPKG) /* \_SB_.NVDR.NV01._LSR.RPKG */ + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32, + IDAT, 32640 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32 + } + + HDLE =3D 0x02 + MTHD =3D 0x0102 + OFST =3D Arg0 + TRSL =3D Arg1 + IDAT =3D Arg2 + NTFI =3D MEMA /* \MEMA */ + Return (STUS) /* \_SB_.NVDR.NV01._LSW.STUS */ + } + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific = Method { Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) } } Device (NV02) { Name (_ADR, 0x03) // _ADR: Address + OperationRegion (NRAM, SystemMemory, MEMA, 0x1000) + Method (_LSI, 0, Serialized) // _LSI: Label Storage Infor= mation + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + SIZE, 32, + MAXT, 32 + } + + HDLE =3D 0x03 + MTHD =3D 0x0100 + NTFI =3D MEMA /* \MEMA */ + Name (RPKG, Package (0x03) + { + STUS, + SIZE, + MAXT + }) + Return (RPKG) /* \_SB_.NVDR.NV02._LSI.RPKG */ + } + + Method (_LSR, 2, Serialized) // _LSR: Label Storage Read + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32, + ODAT, 32704 + } + + HDLE =3D 0x03 + MTHD =3D 0x0101 + OFST =3D Arg0 + TRSL =3D Arg1 + NTFI =3D MEMA /* \MEMA */ + Local1 =3D (Arg1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Name (RPKG, Package (0x02) + { + STUS, + OBUF + }) + Return (RPKG) /* \_SB_.NVDR.NV02._LSR.RPKG */ + } + + Method (_LSW, 3, Serialized) // _LSW: Label Storage Write + { + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + MTHD, 32, + OFST, 32, + TRSL, 32, + IDAT, 32640 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + STUS, 32 + } + + HDLE =3D 0x03 + MTHD =3D 0x0102 + OFST =3D Arg0 + TRSL =3D Arg1 + IDAT =3D Arg2 + NTFI =3D MEMA /* \MEMA */ + Return (STUS) /* \_SB_.NVDR.NV02._LSW.STUS */ + } + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific = Method { Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) } } } } - - Name (MEMA, 0x07FFF000) } Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- tests/data/acpi/pc/SSDT.dimmpxm | Bin 734 -> 1829 bytes tests/data/acpi/q35/SSDT.dimmpxm | Bin 734 -> 1829 bytes tests/qtest/bios-tables-test-allowed-diff.h | 2 -- 3 files changed, 2 deletions(-) diff --git a/tests/data/acpi/pc/SSDT.dimmpxm b/tests/data/acpi/pc/SSDT.dimm= pxm index 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z1`%ITKW9fD-U44&U&plQ2EPDLe@1QzE-n@zJIK+OA&r|sAi9woB+l#?;^wIk-6#W+ zVD@nFaa9O%4GUIq3-xnWaB~cDZ}>HFVU~qt?c_9uNs}`Y7#46&&SF?1$jk^P7z=3DVh zdI~Z@nhLT&x)#V(Pwva+Vwv2Y&B(CXozaCcO~x#h4L$E9tlZYUyG#3*@-UuSkj3Lj=3D0rDgd!-xOu0Hgy@&Hw-a diff --git a/tests/qtest/bios-tables-test-allowed-diff.h b/tests/qtest/bios= -tables-test-allowed-diff.h index eb8bae1407..dfb8523c8b 100644 --- a/tests/qtest/bios-tables-test-allowed-diff.h +++ b/tests/qtest/bios-tables-test-allowed-diff.h @@ -1,3 +1 @@ /* List of comma-separated changed AML files to ignore */ -"tests/data/acpi/pc/SSDT.dimmpxm", -"tests/data/acpi/q35/SSDT.dimmpxm", --=20 2.31.1 From nobody Thu May 16 00:23:13 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass header.i=@intel.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linux.intel.com ARC-Seal: i=1; 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X-IronPort-AV: E=Sophos;i="5.91,261,1647327600"; d="scan'208";a="528993841" From: Robert Hoo To: imammedo@redhat.com, mst@redhat.com, xiaoguangrong.eric@gmail.com, ani@anisinha.ca, dan.j.williams@intel.com, jingqi.liu@intel.com Cc: qemu-devel@nongnu.org, robert.hu@intel.com Subject: [QEMU PATCH v2 6/6] acpi/nvdimm: Define trace events for NVDIMM and substitute nvdimm_debug() Date: Mon, 30 May 2022 11:40:47 +0800 Message-Id: <20220530034047.730356-7-robert.hu@linux.intel.com> X-Mailer: git-send-email 2.31.1 In-Reply-To: <20220530034047.730356-1-robert.hu@linux.intel.com> References: <20220530034047.730356-1-robert.hu@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: none client-ip=192.55.52.115; envelope-from=robert.hu@linux.intel.com; helo=mga14.intel.com X-Spam_score_int: -70 X-Spam_score: -7.1 X-Spam_bar: ------- X-Spam_report: (-7.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_HI=-5, SPF_HELO_NONE=0.001, SPF_NONE=0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @intel.com) X-ZM-MESSAGEID: 1653882407671100001 Signed-off-by: Robert Hoo Reviewed-by: Jingqi Liu --- hw/acpi/nvdimm.c | 38 ++++++++++++++++++-------------------- hw/acpi/trace-events | 14 ++++++++++++++ include/hw/mem/nvdimm.h | 8 -------- 3 files changed, 32 insertions(+), 28 deletions(-) diff --git a/hw/acpi/nvdimm.c b/hw/acpi/nvdimm.c index 50ee85866b..fc777990e6 100644 --- a/hw/acpi/nvdimm.c +++ b/hw/acpi/nvdimm.c @@ -35,6 +35,7 @@ #include "hw/nvram/fw_cfg.h" #include "hw/mem/nvdimm.h" #include "qemu/nvdimm-utils.h" +#include "trace.h" =20 /* * define Byte Addressable Persistent Memory (PM) Region according to @@ -558,8 +559,8 @@ static void nvdimm_dsm_func_read_fit(NVDIMMState *state= , NvdimmDsmIn *in, =20 fit =3D fit_buf->fit; =20 - nvdimm_debug("Read FIT: offset 0x%x FIT size 0x%x Dirty %s.\n", - read_fit->offset, fit->len, fit_buf->dirty ? "Yes" : "No"= ); + trace_acpi_nvdimm_read_fit(read_fit->offset, fit->len, + fit_buf->dirty ? "Yes" : "No"); =20 if (read_fit->offset > fit->len) { func_ret_status =3D NVDIMM_DSM_RET_STATUS_INVALID; @@ -667,7 +668,7 @@ static void nvdimm_dsm_label_size(NVDIMMDevice *nvdimm,= hwaddr dsm_mem_addr) label_size =3D nvdimm->label_size; mxfer =3D nvdimm_get_max_xfer_label_size(); =20 - nvdimm_debug("label_size 0x%x, max_xfer 0x%x.\n", label_size, mxfer); + trace_acpi_nvdimm_label_info(label_size, mxfer); =20 label_size_out.func_ret_status =3D cpu_to_le32(NVDIMM_DSM_RET_STATUS_S= UCCESS); label_size_out.label_size =3D cpu_to_le32(label_size); @@ -683,20 +684,18 @@ static uint32_t nvdimm_rw_label_data_check(NVDIMMDevi= ce *nvdimm, uint32_t ret =3D NVDIMM_DSM_RET_STATUS_INVALID; =20 if (offset + length < offset) { - nvdimm_debug("offset 0x%x + length 0x%x is overflow.\n", offset, - length); + trace_acpi_nvdimm_label_overflow(offset, length); return ret; } =20 if (nvdimm->label_size < offset + length) { - nvdimm_debug("position 0x%x is beyond label data (len =3D %" PRIx6= 4 ").\n", - offset + length, nvdimm->label_size); + trace_acpi_nvdimm_label_oversize(offset + length, nvdimm->label_si= ze); return ret; } =20 if (length > nvdimm_get_max_xfer_label_size()) { - nvdimm_debug("length (0x%x) is larger than max_xfer (0x%x).\n", - length, nvdimm_get_max_xfer_label_size()); + trace_acpi_nvdimm_label_xfer_exceed(length, + nvdimm_get_max_xfer_label_size= ()); return ret; } =20 @@ -718,8 +717,8 @@ static void nvdimm_dsm_get_label_data(NVDIMMDevice *nvd= imm, get_label_data->offset =3D le32_to_cpu(get_label_data->offset); get_label_data->length =3D le32_to_cpu(get_label_data->length); =20 - nvdimm_debug("Read Label Data: offset 0x%x length 0x%x.\n", - get_label_data->offset, get_label_data->length); + trace_acpi_nvdimm_read_label(get_label_data->offset, + get_label_data->length); =20 status =3D nvdimm_rw_label_data_check(nvdimm, get_label_data->offset, get_label_data->length); @@ -755,8 +754,8 @@ static void nvdimm_dsm_set_label_data(NVDIMMDevice *nvd= imm, set_label_data->offset =3D le32_to_cpu(set_label_data->offset); set_label_data->length =3D le32_to_cpu(set_label_data->length); =20 - nvdimm_debug("Write Label Data: offset 0x%x length 0x%x.\n", - set_label_data->offset, set_label_data->length); + trace_acpi_nvdimm_write_label(set_label_data->offset, + set_label_data->length); =20 status =3D nvdimm_rw_label_data_check(nvdimm, set_label_data->offset, set_label_data->length); @@ -833,7 +832,7 @@ static void nvdimm_dsm_device(uint32_t nv_handle, Nvdim= mDsmIn *dsm_in, static uint64_t nvdimm_method_read(void *opaque, hwaddr addr, unsigned size) { - nvdimm_debug("BUG: we never read NVDIMM Method IO Port.\n"); + trace_acpi_nvdimm_read_io_port(); return 0; } =20 @@ -843,20 +842,19 @@ nvdimm_dsm_handle(void *opaque, NvdimmMthdIn *method_= in, hwaddr dsm_mem_addr) NVDIMMState *state =3D opaque; NvdimmDsmIn *dsm_in =3D (NvdimmDsmIn *)method_in->args; =20 - nvdimm_debug("dsm memory address 0x%" HWADDR_PRIx ".\n", dsm_mem_addr); + trace_acpi_nvdimm_dsm_mem_addr(dsm_mem_addr); =20 dsm_in->revision =3D le32_to_cpu(dsm_in->revision); dsm_in->function =3D le32_to_cpu(dsm_in->function); =20 - nvdimm_debug("Revision 0x%x Handler 0x%x Function 0x%x.\n", - dsm_in->revision, method_in->handle, dsm_in->function); + trace_acpi_nvdimm_dsm_info(dsm_in->revision, + method_in->handle, dsm_in->function); /* * Current NVDIMM _DSM Spec supports Rev1 and Rev2 * Intel=C2=AE OptanePersistent Memory Module DSM Interface, Revision = 2.0 */ if (dsm_in->revision !=3D 0x1 && dsm_in->revision !=3D 0x2) { - nvdimm_debug("Revision 0x%x is not supported, expect 0x1 or 0x2.\n= ", - dsm_in->revision); + trace_acpi_nvdimm_invalid_revision(dsm_in->revision); nvdimm_dsm_no_payload(NVDIMM_DSM_RET_STATUS_UNSUPPORT, dsm_mem_add= r); return; } @@ -943,7 +941,7 @@ nvdimm_method_write(void *opaque, hwaddr addr, uint64_t= val, unsigned size) nvdimm_lsw_handle(method_in->handle, method_in->args, dsm_mem_addr= ); break; default: - nvdimm_debug("%s: Unkown method 0x%x\n", __func__, method_in->meth= od); + trace_acpi_nvdimm_invalid_method(method_in->method); break; } =20 diff --git a/hw/acpi/trace-events b/hw/acpi/trace-events index 2250126a22..db4c69009f 100644 --- a/hw/acpi/trace-events +++ b/hw/acpi/trace-events @@ -70,3 +70,17 @@ acpi_erst_reset_out(unsigned record_count) "record_count= %u" acpi_erst_post_load(void *header, unsigned slot_size) "header: 0x%p slot_s= ize %u" acpi_erst_class_init_in(void) acpi_erst_class_init_out(void) + +# nvdimm.c +acpi_nvdimm_read_fit(uint32_t offset, uint32_t len, const char *dirty) "Re= ad FIT: offset 0x%" PRIx32 " FIT size 0x%" PRIx32 " Dirty %s" +acpi_nvdimm_label_info(uint32_t label_size, uint32_t mxfer) "label_size 0x= %" PRIx32 ", max_xfer 0x%" PRIx32 +acpi_nvdimm_label_overflow(uint32_t offset, uint32_t length) "offset 0x%" = PRIx32 " + length 0x%" PRIx32 " is overflow" +acpi_nvdimm_label_oversize(uint32_t pos, uint64_t size) "position 0x%" PRI= x32 " is beyond label data (len =3D %" PRIu64 ")" +acpi_nvdimm_label_xfer_exceed(uint32_t length, uint32_t max_xfer) "length = (0x%" PRIx32 ") is larger than max_xfer (0x%" PRIx32 ")" +acpi_nvdimm_read_label(uint32_t offset, uint32_t length) "Read Label Data:= offset 0x%" PRIx32 " length 0x%" PRIx32 +acpi_nvdimm_write_label(uint32_t offset, uint32_t length) "Write Label Dat= a: offset 0x%" PRIx32 " length 0x%" PRIx32 +acpi_nvdimm_read_io_port(void) "Alert: we never read NVDIMM Method IO Port" +acpi_nvdimm_dsm_mem_addr(uint64_t dsm_mem_addr) "dsm memory address 0x%" P= RIx64 +acpi_nvdimm_dsm_info(uint32_t revision, uint32_t handle, uint32_t function= ) "Revision 0x%" PRIx32 " Handle 0x%" PRIx32 " Function 0x%" PRIx32 +acpi_nvdimm_invalid_revision(uint32_t revision) "Revision 0x%" PRIx32 " is= not supported, expect 0x1 or 0x2" +acpi_nvdimm_invalid_method(uint32_t method) "Unkown method %" PRId32 diff --git a/include/hw/mem/nvdimm.h b/include/hw/mem/nvdimm.h index 0206b6125b..c83e273829 100644 --- a/include/hw/mem/nvdimm.h +++ b/include/hw/mem/nvdimm.h @@ -29,14 +29,6 @@ #include "hw/acpi/aml-build.h" #include "qom/object.h" =20 -#define NVDIMM_DEBUG 0 -#define nvdimm_debug(fmt, ...) \ - do { \ - if (NVDIMM_DEBUG) { \ - fprintf(stderr, "nvdimm: " fmt, ## __VA_ARGS__); \ - } \ - } while (0) - /* NVDIMM ACPI Methods */ #define NVDIMM_METHOD_DSM 0 #define NVDIMM_METHOD_LSI 0x100 --=20 2.31.1