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([171.76.94.60]) by smtp.gmail.com with ESMTPSA id x26-20020aa793ba000000b0050dc76281e5sm1020126pff.191.2022.05.26.03.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LWf2NPD9mnY7XjfGUCe+V1G8egaLFjPiPXaI0jytoaU=; b=aYhdYFqW7bDVe67gs4UKkfnNiU34zbGUAHGq5ssQtYNrNalRctwDps6/u8V9VmXOUU 6qPCYyzk3NDD3HvSZx7yJ4cVQSADp0LVJ9sLx94x7ZHYSoBosByv9PW1JrL2FTeDDSFa Q65wITo1fQzo+gT3cTue+Y64c+9kgK12Y32m12dXNtOZ1XuFfIV5E3/TTVQ6Bu16PosA 9Jkq0Opo8+j/0E2sn5rOi9peYnE3G6Jf2PquG6frR94zJvr56J+KP4Ddw5JwB/XCxwL1 nn/tUn9gD2bzVgnH4gzStPnAd5hHRV9dUli7eDTP9pMg5EENpZuzhHuNVxJyHcNfMAvM fvZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LWf2NPD9mnY7XjfGUCe+V1G8egaLFjPiPXaI0jytoaU=; b=18js9cJiWW4UYfuUUE3hBHX4Jd/Y3yeVzdI07aF/4CIR1i2pkTWmdJLrN3qAoerL66 eh8EFNYMjWr1gK527PiakvYYdqA3x84Tb0GxkXPWVDDDlPaWAnUFAIxDKlliUJI+EURP QYUcBZ6yMvXCPxhzMKuZxshd+RIfzMEZAju5QOvrZwB+w8ILWG0nUu1ZoCdZTw1PrxqD g3Wr6dvnNFJNvasYc6FI9BadbClWttI1/fxZP6cYl0HNjpnmnnmpac5MmiSoayh1g5Bp EAz3rMo0w5T8N5IAL44aJMLYMJ+yvcGSxcRPfaRqEx+FwzSdyZKBN/po1p+i6X940lpu pCGg== X-Gm-Message-State: AOAM532g8FBuhJmWzaz1Nd7aB9YvagBUdg4MGoT/PBnnPHWMi5R52Hap j3ouA80UPlseqVDIDvRGs4rWvA== X-Google-Smtp-Source: ABdhPJy34YhOzDqrvRhU+y0ydanlQAKLoH+/bEz2ylJWBdaB5Bq139jsNFcl3Gj9QWjUFgufnjtruw== X-Received: by 2002:a17:902:ccc1:b0:15a:24df:a7cc with SMTP id z1-20020a170902ccc100b0015a24dfa7ccmr37324112ple.42.1653559551117; Thu, 26 May 2022 03:05:51 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Atish Patra Subject: [PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest Date: Thu, 26 May 2022 15:35:33 +0530 Message-Id: <20220526100536.49672-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220526100536.49672-1-apatel@ventanamicro.com> References: <20220526100536.49672-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1653559758119100001 Content-Type: text/plain; charset="utf-8" The riscv_cpu_realize() sets priv spec verion to v1.12 when it is when "env->priv_ver =3D=3D 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec !=3D NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a91253d4bd..b086eb25da 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -169,6 +169,8 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv32_sifive_u_cpu_init(Object *obj) @@ -509,7 +513,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D 0; + int priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -533,10 +537,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (priv_version) { + if (priv_version >=3D PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } =20 if (cpu->cfg.mmu) { --=20 2.34.1