From nobody Thu May 16 06:43:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1653559757; cv=none; d=zohomail.com; s=zohoarc; b=Dn6AMQacUKtQKzCYyfj1R5kib3VTqCmCKGVT4h5uygweK/1u3wVisoDx5Mur6nmE+i7e5PKgoYXmrczPdKiNZY5Jj+q9ulnRrvNNsy4Hm47rkkyxh/JVHh4sfvRULCSERuTdobXWbQBtIAG8fwFTF+gt5QUuQF4208/IqMlvHBA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1653559757; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LWf2NPD9mnY7XjfGUCe+V1G8egaLFjPiPXaI0jytoaU=; b=XDQIKcF/hCKESQGRBMypVEplfQtOHMzdM//HWg7Q54Cg+zvqlmkeBQ7oRNUrgMtqE02p4tB60NGUT/x1yUbUjJjuffZqgqXYzDbmiuM6tyMR0m+Fz9oC7TmPVcMBRs/R1xyMFBInIs2b6JYru7WvyFh14s3EZ8KBke8AOCMx9ww= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653559757190487.54022186711234; Thu, 26 May 2022 03:09:17 -0700 (PDT) Received: from localhost ([::1]:47918 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nuAQe-0002XG-5N for importer@patchew.org; Thu, 26 May 2022 06:09:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48912) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nuANN-0007UC-TW for qemu-devel@nongnu.org; Thu, 26 May 2022 06:05:58 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:45589) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nuANM-0000sF-Df for qemu-devel@nongnu.org; Thu, 26 May 2022 06:05:53 -0400 Received: by mail-pj1-x102d.google.com with SMTP id w2-20020a17090ac98200b001e0519fe5a8so1314436pjt.4 for ; Thu, 26 May 2022 03:05:52 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.94.60]) by smtp.gmail.com with ESMTPSA id x26-20020aa793ba000000b0050dc76281e5sm1020126pff.191.2022.05.26.03.05.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:05:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LWf2NPD9mnY7XjfGUCe+V1G8egaLFjPiPXaI0jytoaU=; b=aYhdYFqW7bDVe67gs4UKkfnNiU34zbGUAHGq5ssQtYNrNalRctwDps6/u8V9VmXOUU 6qPCYyzk3NDD3HvSZx7yJ4cVQSADp0LVJ9sLx94x7ZHYSoBosByv9PW1JrL2FTeDDSFa Q65wITo1fQzo+gT3cTue+Y64c+9kgK12Y32m12dXNtOZ1XuFfIV5E3/TTVQ6Bu16PosA 9Jkq0Opo8+j/0E2sn5rOi9peYnE3G6Jf2PquG6frR94zJvr56J+KP4Ddw5JwB/XCxwL1 nn/tUn9gD2bzVgnH4gzStPnAd5hHRV9dUli7eDTP9pMg5EENpZuzhHuNVxJyHcNfMAvM fvZw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LWf2NPD9mnY7XjfGUCe+V1G8egaLFjPiPXaI0jytoaU=; b=18js9cJiWW4UYfuUUE3hBHX4Jd/Y3yeVzdI07aF/4CIR1i2pkTWmdJLrN3qAoerL66 eh8EFNYMjWr1gK527PiakvYYdqA3x84Tb0GxkXPWVDDDlPaWAnUFAIxDKlliUJI+EURP QYUcBZ6yMvXCPxhzMKuZxshd+RIfzMEZAju5QOvrZwB+w8ILWG0nUu1ZoCdZTw1PrxqD g3Wr6dvnNFJNvasYc6FI9BadbClWttI1/fxZP6cYl0HNjpnmnnmpac5MmiSoayh1g5Bp EAz3rMo0w5T8N5IAL44aJMLYMJ+yvcGSxcRPfaRqEx+FwzSdyZKBN/po1p+i6X940lpu pCGg== X-Gm-Message-State: AOAM532g8FBuhJmWzaz1Nd7aB9YvagBUdg4MGoT/PBnnPHWMi5R52Hap j3ouA80UPlseqVDIDvRGs4rWvA== X-Google-Smtp-Source: ABdhPJy34YhOzDqrvRhU+y0ydanlQAKLoH+/bEz2ylJWBdaB5Bq139jsNFcl3Gj9QWjUFgufnjtruw== X-Received: by 2002:a17:902:ccc1:b0:15a:24df:a7cc with SMTP id z1-20020a170902ccc100b0015a24dfa7ccmr37324112ple.42.1653559551117; Thu, 26 May 2022 03:05:51 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis , Atish Patra Subject: [PATCH v3 1/4] target/riscv: Don't force update priv spec version to latest Date: Thu, 26 May 2022 15:35:33 +0530 Message-Id: <20220526100536.49672-2-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220526100536.49672-1-apatel@ventanamicro.com> References: <20220526100536.49672-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1653559758119100001 Content-Type: text/plain; charset="utf-8" The riscv_cpu_realize() sets priv spec verion to v1.12 when it is when "env->priv_ver =3D=3D 0" (i.e. default v1.10) because the enum value of priv spec v1.10 is zero. Due to above issue, the sifive_u machine will see priv spec v1.12 instead of priv spec v1.10. To fix this issue, we set latest priv spec version (i.e. v1.12) for base rv64/rv32 cpu and riscv_cpu_realize() will override priv spec version only when "cpu->cfg.priv_spec !=3D NULL". Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Reviewed-by: Atish Patra --- target/riscv/cpu.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a91253d4bd..b086eb25da 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -169,6 +169,8 @@ static void rv64_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV64, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv64_sifive_u_cpu_init(Object *obj) @@ -204,6 +206,8 @@ static void rv32_base_cpu_init(Object *obj) CPURISCVState *env =3D &RISCV_CPU(obj)->env; /* We set this in the realise function */ set_misa(env, MXL_RV32, 0); + /* Set latest version of privileged specification */ + set_priv_version(env, PRIV_VERSION_1_12_0); } =20 static void rv32_sifive_u_cpu_init(Object *obj) @@ -509,7 +513,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error *= *errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D 0; + int priv_version =3D -1; Error *local_err =3D NULL; =20 cpu_exec_realizefn(cs, &local_err); @@ -533,10 +537,8 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) } } =20 - if (priv_version) { + if (priv_version >=3D PRIV_VERSION_1_10_0) { set_priv_version(env, priv_version); - } else if (!env->priv_ver) { - set_priv_version(env, PRIV_VERSION_1_12_0); } =20 if (cpu->cfg.mmu) { --=20 2.34.1 From nobody Thu May 16 06:43:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1653560012; cv=none; d=zohomail.com; s=zohoarc; b=AcYgD1YUA52xG2EEM0+CiBX8nWg++yGrQpvcuxqd8kxy4PMe6AsbbsPFsHLfChQGr/HXGgUrQU1YD5OFR8zxsekK+WoeUnKASj8RmqqC+EhS6Wl+l7XUXJvqbCjGBMC/aRQyvEFdlczE7puH9AASXw9Evz9QtSeKEZKsUQdmQxc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1653560012; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=w6MrD6bzN19Je1Xt3JmYim4uIDMcK9Yyrc6qTYo17mM=; b=gYMzriYhfSaCAE8m4gv3uNxx8JTdXWbxNLieqpgt6wLHgj/2mJu1nadohIKaSKQ3sdDxRHLvYYvhChpGmMRX323WZm3g6SrX4qJXAqYjdLycthdXXsU6UZvu4GdSMOfKbb6ljsbL+fyml3JD6lwWXNx3pVQekFkfG8IsruRFEjE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653560012218869.2900815632208; Thu, 26 May 2022 03:13:32 -0700 (PDT) Received: from localhost ([::1]:54314 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nuAUl-0007Mi-3A for importer@patchew.org; Thu, 26 May 2022 06:13:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:48952) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nuANS-0007Uq-Dx for qemu-devel@nongnu.org; Thu, 26 May 2022 06:06:00 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:45589) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nuANQ-0000sF-OK for qemu-devel@nongnu.org; Thu, 26 May 2022 06:05:57 -0400 Received: by mail-pj1-x102d.google.com with SMTP id w2-20020a17090ac98200b001e0519fe5a8so1314436pjt.4 for ; Thu, 26 May 2022 03:05:55 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.94.60]) by smtp.gmail.com with ESMTPSA id x26-20020aa793ba000000b0050dc76281e5sm1020126pff.191.2022.05.26.03.05.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:05:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=w6MrD6bzN19Je1Xt3JmYim4uIDMcK9Yyrc6qTYo17mM=; b=NvNlvCI6HhMSLd19YYvZUNNq9a4yomNfspgfywybPYrVo+JXqa9zoWpZ3mZpJmQd2y yh9DrXL7YdthjrAwKzz2Nznjj/FgC8klHoLhGs5OeJur5crw2Sh43/kNXKH7ZbF5q5nV tvElxTFjKHPCoYfVdqDVbbI/j/ZIoIMg6CAiEzXU17pUKotifxTOBr8TqHyb2FAIG2NU 5nHVojnryvbBPKWEQ425OHRjkxO9rk50YIW1IJoo2KWG/LFbsSLQeEVnZeQiyiLpS6Xp KOAegreZ+0Rqc/mhQhj501T5sbuPzEgDLOnglnTbnGtBhdx61KmvGmDqe7zn0fd6Jl05 gEFA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=w6MrD6bzN19Je1Xt3JmYim4uIDMcK9Yyrc6qTYo17mM=; b=r+Uajq1xOW21rEDYZera11l5u4lQnEGAwJ6XW/NZDvTvzCG24XoV3n1vtFze6//xlH whxZCpEBxH3s2zAsoA+h/dHBsozCtrMZY81hDKuwdZGT5oF2HW4C1Dfer5ftksxwE6dT +l2isEal45+byRFJ6PPgG7NMMZTFggitsAwaRa2PGcywGk9WoGWtRLUew+bcVG7NuSy0 0pz48q9cAV9TFn2aX9NNcbWi1hBlMyhVwMp5YbaG5d57rkIOXoZlT1XulEjWUhmPBmCT /Vd/a1ZAjQu1fjF9ockBl1XLOMdSJ6oCFN+UMGE3Ns/pxGoSyxDl72XWUV4I6bCqHTa0 gzMg== X-Gm-Message-State: AOAM530PVv+UeoljBvh36JEXzvm1MqrcQiekaxMUxbNcpei2VV6IW321 Cb15K5rq0p8lHc4PMfMdhKtnmw== X-Google-Smtp-Source: ABdhPJwOb1/CNA4rVlWexFr84+a/gp9IWX5EjX6DR9l6j3fLLU4YGdzf78BeuDayscnSFUzLxpdB4g== X-Received: by 2002:a17:902:ef45:b0:156:1858:71fc with SMTP id e5-20020a170902ef4500b00156185871fcmr36439276plx.23.1653559555520; Thu, 26 May 2022 03:05:55 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel , Frank Chang , Alistair Francis Subject: [PATCH v3 2/4] target/riscv: Add dummy mcountinhibit CSR for priv spec v1.11 or higher Date: Thu, 26 May 2022 15:35:34 +0530 Message-Id: <20220526100536.49672-3-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220526100536.49672-1-apatel@ventanamicro.com> References: <20220526100536.49672-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=apatel@ventanamicro.com; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1653560013881100001 Content-Type: text/plain; charset="utf-8" The mcountinhibit CSR is mandatory for priv spec v1.11 or higher. For implementation that don't want to implement can simply have a dummy mcountinhibit which always zero. Fixes: a4b2fa433125 ("target/riscv: Introduce privilege version field in the CSR ops.") Signed-off-by: Anup Patel Reviewed-by: Frank Chang Reviewed-by: Alistair Francis --- target/riscv/cpu_bits.h | 3 +++ target/riscv/csr.c | 2 ++ 2 files changed, 5 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 4d04b20d06..4a55c6a709 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -159,6 +159,9 @@ #define CSR_MTVEC 0x305 #define CSR_MCOUNTEREN 0x306 =20 +/* Machine Counter Setup */ +#define CSR_MCOUNTINHIBIT 0x320 + /* 32-bit only */ #define CSR_MSTATUSH 0x310 =20 diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 6dbe9b541f..409a209f14 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -3391,6 +3391,8 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_MIE] =3D { "mie", any, NULL, NULL, rmw_mie= }, [CSR_MTVEC] =3D { "mtvec", any, read_mtvec, write_m= tvec }, [CSR_MCOUNTEREN] =3D { "mcounteren", any, read_mcounteren, write_m= counteren }, + [CSR_MCOUNTINHIBIT] =3D { "mcountinhibit", any, read_zero, write_ignor= e, + .min_priv_ver =3D PRIV_VERSIO= N_1_11_0 }, =20 [CSR_MSTATUSH] =3D { "mstatush", any32, read_mstatush, write_m= statush }, =20 --=20 2.34.1 From nobody Thu May 16 06:43:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1653560050; cv=none; d=zohomail.com; s=zohoarc; b=acE98vSpi4mD/0hVNkhHYZABtSqduOk0NqDyAmRsCYHPnLZxsb6Q0QLoaemZtkNSK5V8964wkprDN+lrGWq7wnvK8oy18OzWn8cdUmWU767gZbFw3NY9qbIL1YRxH4+U0/ecyUWctu2ejKDfp77fzCk3k722Ij/xJy1CfdeoKa0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1653560050; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3FXVciCsDQ0NVe8Dif4r5zSia1aQoEXMdMJSauSwOS8=; b=mVW9DzG1raVkP6TSB9m8CLD8bhs15SEtCI2k9jO+9yKtFcR+U/IJXWP5RVPcsQAZKmAK/hCTxXQ5H6Z7cKa36QLOwGlth5pkmd0dIadSiTT4+mSvIwzLM+Q+2OPUsRjmLUxo6NMJlezUdNfwbKeFG5zuJRL2yrB7EZ6qbmM/uMU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653560050881493.56456590433913; Thu, 26 May 2022 03:14:10 -0700 (PDT) Received: from localhost ([::1]:56492 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nuAVN-0000UH-MI for importer@patchew.org; Thu, 26 May 2022 06:14:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49054) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nuANY-0007Wu-5T for qemu-devel@nongnu.org; Thu, 26 May 2022 06:06:10 -0400 Received: from mail-pl1-x636.google.com ([2607:f8b0:4864:20::636]:38873) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nuANV-0000tK-UF for qemu-devel@nongnu.org; Thu, 26 May 2022 06:06:03 -0400 Received: by mail-pl1-x636.google.com with SMTP id n18so1054994plg.5 for ; Thu, 26 May 2022 03:06:00 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.94.60]) by smtp.gmail.com with ESMTPSA id x26-20020aa793ba000000b0050dc76281e5sm1020126pff.191.2022.05.26.03.05.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:05:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3FXVciCsDQ0NVe8Dif4r5zSia1aQoEXMdMJSauSwOS8=; b=l06M5ypS4DV8ZXCVl/Ax/bx6Zxx1yCA7xXYYPhxdJsaagTTnuRFCtn7RLvg0jHCZId LxJ3Xn/LpQsSOhLwMjwxkOKWaH2fgaHHWpOXClVVHA24GgHu54XNlm1PGhEdPJcArJxr yIC5Wb3Epulfz8AuOx0xCwlHqr3qhuhiyI87hSQ/V8ylcspbOuOEXda7uK1915usmoNX ygX2bI+MwW5p9/m/X4L9cOi7LQnITtkg0jEvhKy4ngHM3LG+XFbAWdCRn3rk/Q8njnun ncmEFzJQObTrXk46SWQ0f2gkRpp1zjxQF3qcSeQ6eZU3e/+jI6vXrh0W3hLg3RWvugul OrJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3FXVciCsDQ0NVe8Dif4r5zSia1aQoEXMdMJSauSwOS8=; b=rdwfLgT4y8R5HBJxWIRESqEo8KMly8YAxME5GmX+n+ykm4+ePUy3fVxJt8UL/61sFm 3BwfFD4ZXeh3ZVEkFYPiMrbbPcK8UljsswzYrruuDIuIcfRykISiky1khRVCKO4RrP/F IF+GJBo7QSR+niNM+4xF/tcZyf8Bl4NcQFG3gP2OawEWi6bFcM4c6VhrQk2WCTt4YoEW TDUPmMqUZz6YMxLp5Bhc9BlWUVzMpIzIuJqmcbifI6o4VM0pDPdZ4SZZi01XMEPDZ16C ER0GWiN7oF1SMgyFssWukV+ltOmoyrd9eXjuWdh2VLLSXzgPKF/NIVwyeHS519R/r83J GuEw== X-Gm-Message-State: AOAM5305ze4dQRqvfd6tPddv9QjDBfSz8aaDMqazS8WdMXn/rwi4Kor7 6KUskO+LhkTYHgPfa7V15tvS0w== X-Google-Smtp-Source: ABdhPJx0TpooiiT3CmLuDK42YDfdb6SUOEbNClIZ8RxrBwxhQKwAWfouUoSNvA4KsC0fv+b8s5UlMQ== X-Received: by 2002:a17:90b:1d87:b0:1dc:a9c0:3d49 with SMTP id pf7-20020a17090b1d8700b001dca9c03d49mr1865011pjb.12.1653559559605; Thu, 26 May 2022 03:05:59 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v3 3/4] target/riscv: Update [m|h]tinst CSR in riscv_cpu_do_interrupt() Date: Thu, 26 May 2022 15:35:35 +0530 Message-Id: <20220526100536.49672-4-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220526100536.49672-1-apatel@ventanamicro.com> References: <20220526100536.49672-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1653560052135100001 Content-Type: text/plain; charset="utf-8" We should write transformed instruction encoding of the trapped instruction in [m|h]tinst CSR at time of taking trap as defined by the RISC-V privileged specification v1.12. Signed-off-by: Anup Patel Reviewed-by: Alistair Francis --- target/riscv/cpu_helper.c | 210 +++++++++++++++++++++++++++++++++++++- target/riscv/instmap.h | 43 ++++++++ 2 files changed, 249 insertions(+), 4 deletions(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index d99fac9d2d..2a2b6776fb 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -22,6 +22,7 @@ #include "qemu/main-loop.h" #include "cpu.h" #include "exec/exec-all.h" +#include "instmap.h" #include "tcg/tcg-op.h" #include "trace.h" #include "semihosting/common-semi.h" @@ -1316,6 +1317,200 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address= , int size, =20 return true; } + +static target_ulong riscv_transformed_insn(CPURISCVState *env, + target_ulong insn) +{ + bool xinsn_has_addr_offset =3D false; + target_ulong xinsn =3D 0; + + /* + * Only Quadrant 0 and Quadrant 2 of RVC instruction space need to + * be uncompressed. The Quadrant 1 of RVC instruction space need + * not be transformed because these instructions won't generate + * any load/store trap. + */ + + if ((insn & 0x3) !=3D 0x3) { + /* Transform 16bit instruction into 32bit instruction */ + switch (GET_C_OP(insn)) { + case OPC_RISC_C_OP_QUAD0: /* Quadrant 0 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLD_LQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLD (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + case OPC_RISC_C_FUNC_LW: /* C.LW */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + xinsn_has_addr_offset =3D true; + break; + case OPC_RISC_C_FUNC_FLW_LD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLW (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_I_IMM(xinsn, GET_C_LW_IMM(insn)); + xinsn_has_addr_offset =3D true; + } else { /* C.LD (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_I_IMM(xinsn, GET_C_LD_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + case OPC_RISC_C_FUNC_FSD_SQ: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSD (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + case OPC_RISC_C_FUNC_SW: /* C.SW */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + xinsn_has_addr_offset =3D true; + break; + case OPC_RISC_C_FUNC_FSW_SD: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSW (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_S_IMM(xinsn, GET_C_SW_IMM(insn)); + xinsn_has_addr_offset =3D true; + } else { /* C.SD (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2S(insn)); + xinsn =3D SET_RS1(xinsn, GET_C_RS1S(insn)); + xinsn =3D SET_S_IMM(xinsn, GET_C_SD_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + default: + break; + } + break; + case OPC_RISC_C_OP_QUAD2: /* Quadrant 2 */ + switch (GET_C_FUNC(insn)) { + case OPC_RISC_C_FUNC_FLDSP_LQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FLDSP (RV32/64) */ + xinsn =3D OPC_RISC_FLD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + case OPC_RISC_C_FUNC_LWSP: /* C.LWSP */ + xinsn =3D OPC_RISC_LW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + break; + case OPC_RISC_C_FUNC_FLWSP_LDSP: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FLWSP (RV32) */ + xinsn =3D OPC_RISC_FLW; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_I_IMM(xinsn, GET_C_LWSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + } else { /* C.LDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_LD; + xinsn =3D SET_RD(xinsn, GET_C_RD(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_I_IMM(xinsn, GET_C_LDSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + case OPC_RISC_C_FUNC_FSDSP_SQSP: + if (riscv_cpu_xlen(env) !=3D 128) { /* C.FSDSP (RV32/64) */ + xinsn =3D OPC_RISC_FSD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + case OPC_RISC_C_FUNC_SWSP: /* C.SWSP */ + xinsn =3D OPC_RISC_SW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + break; + case 7: + if (riscv_cpu_xlen(env) =3D=3D 32) { /* C.FSWSP (RV32) */ + xinsn =3D OPC_RISC_FSW; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_S_IMM(xinsn, GET_C_SWSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + } else { /* C.SDSP (RV64/RV128) */ + xinsn =3D OPC_RISC_SD; + xinsn =3D SET_RS2(xinsn, GET_C_RS2(insn)); + xinsn =3D SET_RS1(xinsn, 2); + xinsn =3D SET_S_IMM(xinsn, GET_C_SDSP_IMM(insn)); + xinsn_has_addr_offset =3D true; + } + break; + default: + break; + } + break; + default: + break; + } + + /* + * Clear Bit1 of transformed instruction to indicate that + * original insruction was a 16bit instruction + */ + xinsn &=3D ~((target_ulong)0x2); + } else { + /* No need to transform 32bit (or wider) instructions */ + xinsn =3D insn; + + /* Check for instructions which need address offset */ + switch (MASK_OP_MAJOR(insn)) { + case OPC_RISC_LOAD: + case OPC_RISC_STORE: + case OPC_RISC_ATOMIC: + case OPC_RISC_FP_LOAD: + case OPC_RISC_FP_STORE: + xinsn_has_addr_offset =3D true; + break; + case OPC_RISC_SYSTEM: + if (MASK_OP_SYSTEM(insn) =3D=3D OPC_RISC_HLVHSV) { + xinsn_has_addr_offset =3D true; + } + break; + } + } + + if (xinsn_has_addr_offset) { + /* + * The "Addr. Offset" field in transformed instruction is non-zero + * only for misaligned load/store traps which are very unlikely on + * QEMU so for now always set "Addr. Offset" to zero. + */ + xinsn =3D SET_RS1(xinsn, 0); + } + + return xinsn; +} #endif /* !CONFIG_USER_ONLY */ =20 /* @@ -1340,6 +1535,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) target_ulong cause =3D cs->exception_index & RISCV_EXCP_INT_MASK; uint64_t deleg =3D async ? env->mideleg : env->medeleg; target_ulong tval =3D 0; + target_ulong tinst =3D 0; target_ulong htval =3D 0; target_ulong mtval2 =3D 0; =20 @@ -1355,18 +1551,22 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (!async) { /* set tval to badaddr for traps with address information */ switch (cause) { - case RISCV_EXCP_INST_GUEST_PAGE_FAULT: case RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT: case RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_ADDR_MIS: - case RISCV_EXCP_INST_ACCESS_FAULT: case RISCV_EXCP_LOAD_ADDR_MIS: case RISCV_EXCP_STORE_AMO_ADDR_MIS: case RISCV_EXCP_LOAD_ACCESS_FAULT: case RISCV_EXCP_STORE_AMO_ACCESS_FAULT: - case RISCV_EXCP_INST_PAGE_FAULT: case RISCV_EXCP_LOAD_PAGE_FAULT: case RISCV_EXCP_STORE_PAGE_FAULT: + write_gva =3D env->two_stage_lookup; + tval =3D env->badaddr; + tinst =3D riscv_transformed_insn(env, env->bins); + break; + case RISCV_EXCP_INST_GUEST_PAGE_FAULT: + case RISCV_EXCP_INST_ADDR_MIS: + case RISCV_EXCP_INST_ACCESS_FAULT: + case RISCV_EXCP_INST_PAGE_FAULT: write_gva =3D env->two_stage_lookup; tval =3D env->badaddr; break; @@ -1448,6 +1648,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->sepc =3D env->pc; env->stval =3D tval; env->htval =3D htval; + env->htinst =3D tinst; env->pc =3D (env->stvec >> 2 << 2) + ((async && (env->stvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_S); @@ -1478,6 +1679,7 @@ void riscv_cpu_do_interrupt(CPUState *cs) env->mepc =3D env->pc; env->mtval =3D tval; env->mtval2 =3D mtval2; + env->mtinst =3D tinst; env->pc =3D (env->mtvec >> 2 << 2) + ((async && (env->mtvec & 3) =3D=3D 1) ? cause * 4 : 0); riscv_cpu_set_mode(env, PRV_M); diff --git a/target/riscv/instmap.h b/target/riscv/instmap.h index 40b6d2b64d..f564a69d90 100644 --- a/target/riscv/instmap.h +++ b/target/riscv/instmap.h @@ -184,6 +184,8 @@ enum { OPC_RISC_CSRRWI =3D OPC_RISC_SYSTEM | (0x5 << 12), OPC_RISC_CSRRSI =3D OPC_RISC_SYSTEM | (0x6 << 12), OPC_RISC_CSRRCI =3D OPC_RISC_SYSTEM | (0x7 << 12), + + OPC_RISC_HLVHSV =3D OPC_RISC_SYSTEM | (0x4 << 12), }; =20 #define MASK_OP_FP_LOAD(op) (MASK_OP_MAJOR(op) | (op & (0x7 << 12))) @@ -316,6 +318,12 @@ enum { #define GET_RS2(inst) extract32(inst, 20, 5) #define GET_RD(inst) extract32(inst, 7, 5) #define GET_IMM(inst) sextract64(inst, 20, 12) +#define SET_RS1(inst, val) deposit32(inst, 15, 5, val) +#define SET_RS2(inst, val) deposit32(inst, 20, 5, val) +#define SET_RD(inst, val) deposit32(inst, 7, 5, val) +#define SET_I_IMM(inst, val) deposit32(inst, 20, 12, val) +#define SET_S_IMM(inst, val) \ + deposit32(deposit32(inst, 7, 5, val), 25, 7, (val) >> 5) =20 /* RVC decoding macros */ #define GET_C_IMM(inst) (extract32(inst, 2, 5) \ @@ -346,6 +354,8 @@ enum { | (extract32(inst, 5, 1) << 6)) #define GET_C_LD_IMM(inst) ((extract16(inst, 10, 3) << 3) \ | (extract16(inst, 5, 2) << 6)) +#define GET_C_SW_IMM(inst) GET_C_LW_IMM(inst) +#define GET_C_SD_IMM(inst) GET_C_LD_IMM(inst) #define GET_C_J_IMM(inst) ((extract32(inst, 3, 3) << 1) \ | (extract32(inst, 11, 1) << 4) \ | (extract32(inst, 2, 1) << 5) \ @@ -366,4 +376,37 @@ enum { #define GET_C_RS1S(inst) (8 + extract16(inst, 7, 3)) #define GET_C_RS2S(inst) (8 + extract16(inst, 2, 3)) =20 +#define GET_C_FUNC(inst) extract32(inst, 13, 3) +#define GET_C_OP(inst) extract32(inst, 0, 2) + +enum { + /* RVC Quadrants */ + OPC_RISC_C_OP_QUAD0 =3D 0x0, + OPC_RISC_C_OP_QUAD1 =3D 0x1, + OPC_RISC_C_OP_QUAD2 =3D 0x2 +}; + +enum { + /* RVC Quadrant 0 */ + OPC_RISC_C_FUNC_ADDI4SPN =3D 0x0, + OPC_RISC_C_FUNC_FLD_LQ =3D 0x1, + OPC_RISC_C_FUNC_LW =3D 0x2, + OPC_RISC_C_FUNC_FLW_LD =3D 0x3, + OPC_RISC_C_FUNC_FSD_SQ =3D 0x5, + OPC_RISC_C_FUNC_SW =3D 0x6, + OPC_RISC_C_FUNC_FSW_SD =3D 0x7 +}; + +enum { + /* RVC Quadrant 2 */ + OPC_RISC_C_FUNC_SLLI_SLLI64 =3D 0x0, + OPC_RISC_C_FUNC_FLDSP_LQSP =3D 0x1, + OPC_RISC_C_FUNC_LWSP =3D 0x2, + OPC_RISC_C_FUNC_FLWSP_LDSP =3D 0x3, + OPC_RISC_C_FUNC_JR_MV_EBREAK_JALR_ADD =3D 0x4, + OPC_RISC_C_FUNC_FSDSP_SQSP =3D 0x5, + OPC_RISC_C_FUNC_SWSP =3D 0x6, + OPC_RISC_C_FUNC_FSWSP_SDSP =3D 0x7 +}; + #endif --=20 2.34.1 From nobody Thu May 16 06:43:52 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org ARC-Seal: i=1; a=rsa-sha256; t=1653559957; cv=none; d=zohomail.com; s=zohoarc; b=EzhEdIKFMYoPXH6MK5k8wugQrn5xOtYkcSCw7PHIzZCoCJ/o/rvYdk29a8jridwes9iy6VmsrRTGDl1DUuk5tPIAGfaLrZyHDOJ4xBIUs43pk4uYphj1jLyiTHaPmbEGMox4O6Na2sSwDL9crgUkbIRCr59LVD87GEPaNb1TACY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1653559957; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LdhJ+CzqwO9act42e+Xaxnx8iyy+fkBBxBLgmWQJtgQ=; b=e6CnEY3TOdt/5l1VjSd6OQzwxY2Q2FJPD/Ygh/AzoP2FBnWRSAS3zUFmlBSmrRyK/gZz/rVANQkGV9BeuL1/WWCGVWk8lIFxVoSj1KRRhk8oXE42WNk6ZquY+M0Ll8tCrOMER5991ksqSVkPLpb7oHbnZMWAtBGBTxA1c7rVawk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653559957781629.1281890822651; Thu, 26 May 2022 03:12:37 -0700 (PDT) Received: from localhost ([::1]:52814 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nuATs-0006ES-KW for importer@patchew.org; Thu, 26 May 2022 06:12:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49090) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nuANa-0007Wz-MO for qemu-devel@nongnu.org; Thu, 26 May 2022 06:06:12 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:46787) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nuANZ-0000tw-6J for qemu-devel@nongnu.org; Thu, 26 May 2022 06:06:06 -0400 Received: by mail-pl1-x633.google.com with SMTP id w3so1029985plp.13 for ; Thu, 26 May 2022 03:06:04 -0700 (PDT) Received: from anup-ubuntu64-vm.. ([171.76.94.60]) by smtp.gmail.com with ESMTPSA id x26-20020aa793ba000000b0050dc76281e5sm1020126pff.191.2022.05.26.03.05.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 26 May 2022 03:06:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ventanamicro.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LdhJ+CzqwO9act42e+Xaxnx8iyy+fkBBxBLgmWQJtgQ=; b=Vh4rBeHncB9dp6KVTnDRxwLLBVmQbFdHpi/+2q4Ho19sQqiIjD3rebIK8ASzTS4Nvw b/sJAARUR/WPMz9Ew3pDmuJV/cMub7Y7xNADQFeevkAajP3fffxeEotvNtv/PbKNCYD7 YVv0OrQLi09Y/tKJ2Y/rZY0neqQtMaKePk1LJqqe5+qRg69zurkJECDJUDdckT8WgOl4 6H/khiFcSasnlDdFYtqnkHC5Ji9yFR9cVPQgWlJVe2CvKNe+ZzGGxZqQVOP8+VHyWOET CEW3eS+nQ/UTjPhG+S5ZV1HFP7MARV5Zw3nMwWmKKpcPGlhmlp5rAEHbAvgaKzF20wRY GJOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LdhJ+CzqwO9act42e+Xaxnx8iyy+fkBBxBLgmWQJtgQ=; b=Ezk1s6JMTouTv7TIMNoTUxVOnHpAHu8cxexu8LmnOaI9skvAyCT1nTRc1pAHL7q8VB /w4LtdjlfnFoXbc4lVhKBA5vKML1VDqogZuj+3uYl4Di7JIHBaYHNLi0Wp4288LOGbc9 gIW402A/XUSEmUwMApAEZPN6WQhvm7OsjcHhJ4Cu7S6APBuB8zE4hu3hULorXtqAak8A muMzmKhuixQCGVqYpgiFqrKAym2ekAWxp3O3g1cmeEX4KlgbDyCNIAaw8J9s7/BZDEbK Y3Q8pimoIrLyGh5KVSQhTUYCkk2FI+WBdvGBVAvLYibSGgOCCJjFGM84ZZ1f7xxi61Ti MvLA== X-Gm-Message-State: AOAM532gZJZ3tSdamUsKo/0DphAGDk/IhbJndk2eFud17UfVJq4K0hmV uPwlmvEQVT/5gK7//EJnxt1xXw== X-Google-Smtp-Source: ABdhPJyR2+IC2JnyWqD1D91aE7QlZAaCwEjL0+eFJWq7DkRJX9QBRE2B0bQNh44Ll3zXdLI0HI7wDQ== X-Received: by 2002:a17:902:bf04:b0:149:c5a5:5323 with SMTP id bi4-20020a170902bf0400b00149c5a55323mr37265235plb.97.1653559563812; Thu, 26 May 2022 03:06:03 -0700 (PDT) From: Anup Patel To: Peter Maydell , Palmer Dabbelt , Alistair Francis , Sagar Karandikar Cc: Atish Patra , Anup Patel , qemu-riscv@nongnu.org, qemu-devel@nongnu.org, Anup Patel Subject: [PATCH v3 4/4] target/riscv: Force disable extensions if priv spec version does not match Date: Thu, 26 May 2022 15:35:36 +0530 Message-Id: <20220526100536.49672-5-apatel@ventanamicro.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220526100536.49672-1-apatel@ventanamicro.com> References: <20220526100536.49672-1-apatel@ventanamicro.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=apatel@ventanamicro.com; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @ventanamicro.com) X-ZM-MESSAGEID: 1653559959667100001 Content-Type: text/plain; charset="utf-8" We should disable extensions in riscv_cpu_realize() if minimum required priv spec version is not satisfied. This also ensures that machines with priv spec v1.11 (or lower) cannot enable H, V, and various multi-letter extensions. Fixes: a775398be2e ("target/riscv: Add isa extenstion strings to the device tree") Signed-off-by: Anup Patel --- target/riscv/cpu.c | 56 +++++++++++++++++++++++++++++++++++++++++----- 1 file changed, 51 insertions(+), 5 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index b086eb25da..e6e878ceb3 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -43,9 +43,13 @@ static const char riscv_single_letter_exts[] =3D "IEMAFD= QCPVH"; =20 struct isa_ext_data { const char *name; - bool enabled; + int min_version; + bool *enabled; }; =20 +#define ISA_EDATA_ENTRY(name, prop) {#name, PRIV_VERSION_1_10_0, &cpu->cfg= .prop} +#define ISA_EDATA_ENTRY2(name, min_ver, prop) {#name, min_ver, &cpu->cfg.p= rop} + const char * const riscv_int_regnames[] =3D { "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", @@ -513,8 +517,42 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) CPURISCVState *env =3D &cpu->env; RISCVCPUClass *mcc =3D RISCV_CPU_GET_CLASS(dev); CPUClass *cc =3D CPU_CLASS(mcc); - int priv_version =3D -1; + int i, priv_version =3D -1; Error *local_err =3D NULL; + struct isa_ext_data isa_edata_arr[] =3D { + ISA_EDATA_ENTRY2(h, PRIV_VERSION_1_12_0, ext_h), + ISA_EDATA_ENTRY2(v, PRIV_VERSION_1_12_0, ext_v), + ISA_EDATA_ENTRY2(zicsr, PRIV_VERSION_1_10_0, ext_icsr), + ISA_EDATA_ENTRY2(zifencei, PRIV_VERSION_1_10_0, ext_ifencei), + ISA_EDATA_ENTRY2(zfh, PRIV_VERSION_1_12_0, ext_zfh), + ISA_EDATA_ENTRY2(zfhmin, PRIV_VERSION_1_12_0, ext_zfhmin), + ISA_EDATA_ENTRY2(zfinx, PRIV_VERSION_1_12_0, ext_zfinx), + ISA_EDATA_ENTRY2(zdinx, PRIV_VERSION_1_12_0, ext_zdinx), + ISA_EDATA_ENTRY2(zba, PRIV_VERSION_1_12_0, ext_zba), + ISA_EDATA_ENTRY2(zbb, PRIV_VERSION_1_12_0, ext_zbb), + ISA_EDATA_ENTRY2(zbc, PRIV_VERSION_1_12_0, ext_zbc), + ISA_EDATA_ENTRY2(zbkb, PRIV_VERSION_1_12_0, ext_zbkb), + ISA_EDATA_ENTRY2(zbkc, PRIV_VERSION_1_12_0, ext_zbkc), + ISA_EDATA_ENTRY2(zbkx, PRIV_VERSION_1_12_0, ext_zbkx), + ISA_EDATA_ENTRY2(zbs, PRIV_VERSION_1_12_0, ext_zbs), + ISA_EDATA_ENTRY2(zk, PRIV_VERSION_1_12_0, ext_zk), + ISA_EDATA_ENTRY2(zkn, PRIV_VERSION_1_12_0, ext_zkn), + ISA_EDATA_ENTRY2(zknd, PRIV_VERSION_1_12_0, ext_zknd), + ISA_EDATA_ENTRY2(zkne, PRIV_VERSION_1_12_0, ext_zkne), + ISA_EDATA_ENTRY2(zknh, PRIV_VERSION_1_12_0, ext_zknh), + ISA_EDATA_ENTRY2(zkr, PRIV_VERSION_1_12_0, ext_zkr), + ISA_EDATA_ENTRY2(zks, PRIV_VERSION_1_12_0, ext_zks), + ISA_EDATA_ENTRY2(zksed, PRIV_VERSION_1_12_0, ext_zksed), + ISA_EDATA_ENTRY2(zksh, PRIV_VERSION_1_12_0, ext_zksh), + ISA_EDATA_ENTRY2(zkt, PRIV_VERSION_1_12_0, ext_zkt), + ISA_EDATA_ENTRY2(zve32f, PRIV_VERSION_1_12_0, ext_zve32f), + ISA_EDATA_ENTRY2(zve64f, PRIV_VERSION_1_12_0, ext_zve64f), + ISA_EDATA_ENTRY2(zhinx, PRIV_VERSION_1_12_0, ext_zhinx), + ISA_EDATA_ENTRY2(zhinxmin, PRIV_VERSION_1_12_0, ext_zhinxmin), + ISA_EDATA_ENTRY2(svinval, PRIV_VERSION_1_12_0, ext_svinval), + ISA_EDATA_ENTRY2(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), + ISA_EDATA_ENTRY2(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + }; =20 cpu_exec_realizefn(cs, &local_err); if (local_err !=3D NULL) { @@ -541,6 +579,16 @@ static void riscv_cpu_realize(DeviceState *dev, Error = **errp) set_priv_version(env, priv_version); } =20 + /* Force disable extensions if priv spec version does not match */ + for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { + if (*isa_edata_arr[i].enabled && + (env->priv_ver < isa_edata_arr[i].min_version)) { + *isa_edata_arr[i].enabled =3D false; + warn_report("privilege spec version does not match for %s exte= nsion", + isa_edata_arr[i].name); + } + } + if (cpu->cfg.mmu) { riscv_set_feature(env, RISCV_FEATURE_MMU); } @@ -1005,8 +1053,6 @@ static void riscv_cpu_class_init(ObjectClass *c, void= *data) device_class_set_props(dc, riscv_cpu_properties); } =20 -#define ISA_EDATA_ENTRY(name, prop) {#name, cpu->cfg.prop} - static void riscv_isa_string_ext(RISCVCPU *cpu, char **isa_str, int max_st= r_len) { char *old =3D *isa_str; @@ -1064,7 +1110,7 @@ static void riscv_isa_string_ext(RISCVCPU *cpu, char = **isa_str, int max_str_len) }; =20 for (i =3D 0; i < ARRAY_SIZE(isa_edata_arr); i++) { - if (isa_edata_arr[i].enabled) { + if (*isa_edata_arr[i].enabled) { new =3D g_strconcat(old, "_", isa_edata_arr[i].name, NULL); g_free(old); old =3D new; --=20 2.34.1