From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165349535263456.89875408603143; Wed, 25 May 2022 09:15:52 -0700 (PDT) Received: from localhost ([::1]:53144 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttfr-0006gy-IP for importer@patchew.org; Wed, 25 May 2022 12:15:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36434) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSM-00073E-Kg; Wed, 25 May 2022 12:01:59 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:58825) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSK-00048Y-JO; Wed, 25 May 2022 12:01:54 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRF2d46z4xDK; Thu, 26 May 2022 02:01:45 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRC26Bhz4xXj; Thu, 26 May 2022 02:01:43 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 01/15] docs: add minibmc section in aspeed document Date: Wed, 25 May 2022 18:01:22 +0200 Message-Id: <20220525160136.556277-2-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495354210100001 From: Jamin Lin Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220506031521.13254-2-jamin_lin@aspeedtech.com> Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 61 ++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 60ed94f18759..6f2e4fb53d49 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -120,3 +120,64 @@ FMC chip and a bigger (64M) SPI chip, use : .. code-block:: bash =20 -M ast2500-evb,fmc-model=3Dmx25l25635e,spi-model=3Dmx66u51235f + + +Aspeed minibmc family boards (``ast1030-evb``) +=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D + +The QEMU Aspeed machines model mini BMCs of various Aspeed evaluation +boards. They are based on different releases of the +Aspeed SoC : the AST1030 integrating an ARM Cortex M4F CPU (200MHz). + +The SoC comes with SRAM, SPI, I2C, etc. + +AST1030 SoC based machines : + +- ``ast1030-evb`` Aspeed AST1030 Evaluation board (Cortex-M4F) + +Supported devices +----------------- + + * SMP (for the AST1030 Cortex-M4F) + * Interrupt Controller (VIC) + * Timer Controller + * I2C Controller + * System Control Unit (SCU) + * SRAM mapping + * Static Memory Controller (SMC or FMC) - Only SPI Flash support + * SPI Memory Controller + * USB 2.0 Controller + * Watchdog Controller + * GPIO Controller (Master only) + * UART + * LPC Peripheral Controller (a subset of subdevices are supported) + * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA + * ADC + + +Missing devices +--------------- + + * PWM and Fan Controller + * Slave GPIO Controller + * PECI Controller + * Mailbox Controller + * Virtual UART + * eSPI Controller + * I3C Controller + +Boot options +------------ + +The Aspeed machines can be started using the ``-kernel`` to load a +Zephyr OS or from a firmware. Images can be downloaded from the +ASPEED GitHub release repository : + + https://github.com/AspeedTech-BMC/zephyr/releases + +To boot a kernel directly from a Zephyr build tree: + +.. code-block:: bash + + $ qemu-system-arm -M ast1030-evb -nographic \ + -kernel zephyr.elf --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495793356473.3209958182598; Wed, 25 May 2022 09:23:13 -0700 (PDT) Received: from localhost ([::1]:44304 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttmy-0003Sg-B7 for importer@patchew.org; Wed, 25 May 2022 12:23:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36478) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSR-000743-Oz; Wed, 25 May 2022 12:02:05 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:47725 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSM-00048f-IF; Wed, 25 May 2022 12:01:56 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRH5gtWz4xbt; Thu, 26 May 2022 02:01:47 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRF6Hsmz4xXj; Thu, 26 May 2022 02:01:45 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 02/15] hw/arm/aspeed: Add fby35 machine type Date: Wed, 25 May 2022 18:01:23 +0200 Message-Id: <20220525160136.556277-3-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495794509100001 From: Peter Delevoryas Add the 'fby35-bmc' machine type based on the kernel DTS[1] and userspace i2c setup scripts[2]. Undefined values are inherited from the AST2600-EVB. Reference images can be found in Facebook OpenBMC Github Release assets as "fby35.mtd". [3] You can boot the reference images as follows (fby35 uses dual-flash): qemu-system-arm -machine fby35-bmc \ -drive file=3Dfby35.mtd,format=3Draw,if=3Dmtd \ -drive file=3Dfby35.mtd,format=3Draw,if=3Dmtd \ -nographic [1] https://github.com/facebook/openbmc-linux/blob/412d5053258007117e94b1e3= 6015aefc1301474b/arch/arm/boot/dts/aspeed-bmc-facebook-fby35.dts [2] https://github.com/facebook/openbmc/blob/e2294ff5d31dd65c248fe396a38528= 6d6d5c463d/meta-facebook/meta-fby35/recipes-fby35/plat-utils/files/setup-de= v.sh [3] https://github.com/facebook/openbmc/releases Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220503225925.1798324-2-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 63 +++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 63 insertions(+) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a74c13ab0fbc..725c169488dc 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -21,6 +21,7 @@ #include "hw/misc/led.h" #include "hw/qdev-properties.h" #include "sysemu/block-backend.h" +#include "sysemu/reset.h" #include "hw/loader.h" #include "qemu/error-report.h" #include "qemu/units.h" @@ -951,6 +952,35 @@ static void bletchley_bmc_i2c_init(AspeedMachineState = *bmc) i2c_slave_create_simple(i2c[12], TYPE_PCA9552, 0x67); } =20 +static void fby35_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc =3D &bmc->soc; + I2CBus *i2c[16]; + + for (int i =3D 0; i < 16; i++) { + i2c[i] =3D aspeed_i2c_get_bus(&soc->i2c, i); + } + + i2c_slave_create_simple(i2c[2], TYPE_LM75, 0x4f); + i2c_slave_create_simple(i2c[8], TYPE_TMP421, 0x1f); + /* Hotswap controller is actually supposed to be mp5920 or ltc4282. */ + i2c_slave_create_simple(i2c[11], "adm1272", 0x44); + i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4e); + i2c_slave_create_simple(i2c[12], TYPE_LM75, 0x4f); + + aspeed_eeprom_init(i2c[4], 0x51, 128 * KiB); + aspeed_eeprom_init(i2c[6], 0x51, 128 * KiB); + aspeed_eeprom_init(i2c[8], 0x50, 32 * KiB); + aspeed_eeprom_init(i2c[11], 0x51, 128 * KiB); + aspeed_eeprom_init(i2c[11], 0x54, 128 * KiB); + + /* + * TODO: There is a multi-master i2c connection to an AST1030 MiniBMC = on + * buses 0, 1, 2, 3, and 9. Source address 0x10, target address 0x20 on + * each. + */ +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -1293,6 +1323,35 @@ static void aspeed_machine_bletchley_class_init(Obje= ctClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); } =20 +static void fby35_reset(MachineState *state) +{ + AspeedMachineState *bmc =3D ASPEED_MACHINE(state); + AspeedGPIOState *gpio =3D &bmc->soc.gpio; + + qemu_devices_reset(); + + /* Board ID */ + object_property_set_bool(OBJECT(gpio), "gpioV4", true, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioV5", true, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioV6", true, &error_fatal); + object_property_set_bool(OBJECT(gpio), "gpioV7", false, &error_fatal); +} + +static void aspeed_machine_fby35_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc =3D MACHINE_CLASS(oc); + AspeedMachineClass *amc =3D ASPEED_MACHINE_CLASS(oc); + + mc->desc =3D "Facebook fby35 BMC (Cortex-A7)"; + mc->reset =3D fby35_reset; + amc->fmc_model =3D "mx66l1g45g"; + amc->num_cs =3D 2; + amc->macs_mask =3D ASPEED_MAC3_ON; + amc->i2c_init =3D fby35_i2c_init; + /* FIXME: Replace this macro with something more general */ + mc->default_ram_size =3D FUJI_BMC_RAM_SIZE; +} + #define AST1030_INTERNAL_FLASH_SIZE (1024 * 1024) /* Main SYSCLK frequency in Hz (200MHz) */ #define SYSCLK_FRQ 200000000ULL @@ -1411,6 +1470,10 @@ static const TypeInfo aspeed_machine_types[] =3D { .name =3D MACHINE_TYPE_NAME("bletchley-bmc"), .parent =3D TYPE_ASPEED_MACHINE, .class_init =3D aspeed_machine_bletchley_class_init, + }, { + .name =3D MACHINE_TYPE_NAME("fby35-bmc"), + .parent =3D MACHINE_TYPE_NAME("ast2600-evb"), + .class_init =3D aspeed_machine_fby35_class_init, }, { .name =3D MACHINE_TYPE_NAME("ast1030-evb"), .parent =3D TYPE_ASPEED_MACHINE, --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495157981808.6291320272823; Wed, 25 May 2022 09:12:37 -0700 (PDT) Received: from localhost ([::1]:46272 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttci-0001aD-Fr for importer@patchew.org; Wed, 25 May 2022 12:12:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36462) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSO-00073J-HF; Wed, 25 May 2022 12:01:59 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:35487) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSL-00048m-L9; Wed, 25 May 2022 12:01:55 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRL1889z4ySg; Thu, 26 May 2022 02:01:50 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRJ27zyz4xXj; Thu, 26 May 2022 02:01:48 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 03/15] docs: aspeed: Add fby35 board Date: Wed, 25 May 2022 18:01:24 +0200 Message-Id: <20220525160136.556277-4-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495159082100001 From: Peter Delevoryas Add fby35 to the list of Aspeed boards. Signed-off-by: Peter Delevoryas Message-Id: <20220506193354.990532-2-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- docs/system/arm/aspeed.rst | 1 + 1 file changed, 1 insertion(+) diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 6f2e4fb53d49..5d0a7865d3a6 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -31,6 +31,7 @@ AST2600 SoC based machines : - ``tacoma-bmc`` OpenPOWER Witherspoon POWER9 AST2600 BMC - ``rainier-bmc`` IBM Rainier POWER10 BMC - ``fuji-bmc`` Facebook Fuji BMC +- ``fby35-bmc`` Facebook fby35 BMC =20 Supported devices ----------------- --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495114121602.1635783664872; Wed, 25 May 2022 09:11:54 -0700 (PDT) Received: from localhost ([::1]:44428 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttc0-0000Mh-NS for importer@patchew.org; Wed, 25 May 2022 12:11:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSR-000742-OL; Wed, 25 May 2022 12:02:02 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:40143 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSN-00048z-F3; Wed, 25 May 2022 12:01:57 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRP08MHz4ySn; Thu, 26 May 2022 02:01:53 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRL4qmFz4xXj; Thu, 26 May 2022 02:01:50 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Iris Chen , Thomas Huth , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Francisco Iglesias Subject: [PULL 04/15] hw: m25p80: allow write_enable latch get/set Date: Wed, 25 May 2022 18:01:25 +0200 Message-Id: <20220525160136.556277-5-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495116477100001 From: Iris Chen The write_enable latch property is not currently exposed. This commit makes it a modifiable property. Signed-off-by: Iris Chen Acked-by: Thomas Huth Reviewed-by: C=C3=A9dric Le Goater Reviewed-by: Francisco Iglesias Message-Id: <20220513055022.951759-1-irischenlj@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- tests/qtest/libqtest.h | 22 +++++++++++++++++ hw/block/m25p80.c | 1 + tests/qtest/aspeed_gpio-test.c | 40 +++++++------------------------ tests/qtest/aspeed_smc-test.c | 43 ++++++++++++++++++++++++++++++++++ tests/qtest/libqtest.c | 24 +++++++++++++++++++ 5 files changed, 98 insertions(+), 32 deletions(-) diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h index 4ab0cad3266d..94b187837d3f 100644 --- a/tests/qtest/libqtest.h +++ b/tests/qtest/libqtest.h @@ -783,4 +783,26 @@ QTestState *qtest_inproc_init(QTestState **s, bool log= , const char* arch, void (*send)(void*, const char*)); =20 void qtest_client_inproc_recv(void *opaque, const char *str); + +/** + * qtest_qom_set_bool: + * @s: QTestState instance to operate on. + * @path: Path to the property being set. + * @property: Property being set. + * @value: Value to set the property. + * + * Set the property with passed in value. + */ +void qtest_qom_set_bool(QTestState *s, const char *path, const char *prope= rty, + bool value); + +/** + * qtest_qom_get_bool: + * @s: QTestState instance to operate on. + * @path: Path to the property being retrieved. + * @property: Property from where the value is being retrieved. + * + * Returns: Value retrieved from property. + */ +bool qtest_qom_get_bool(QTestState *s, const char *path, const char *prope= rty); #endif diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 7d3d8b12e01f..81ba3da4df10 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -1533,6 +1533,7 @@ static int m25p80_pre_save(void *opaque) =20 static Property m25p80_properties[] =3D { /* This is default value for Micron flash */ + DEFINE_PROP_BOOL("write-enable", Flash, write_enable, false), DEFINE_PROP_UINT32("nonvolatile-cfg", Flash, nonvolatile_cfg, 0x8FFF), DEFINE_PROP_UINT8("spansion-cr1nv", Flash, spansion_cr1nv, 0x0), DEFINE_PROP_UINT8("spansion-cr2nv", Flash, spansion_cr2nv, 0x8), diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c index c1003f2d1bc4..bac63e8742f4 100644 --- a/tests/qtest/aspeed_gpio-test.c +++ b/tests/qtest/aspeed_gpio-test.c @@ -28,30 +28,6 @@ #include "qapi/qmp/qdict.h" #include "libqtest-single.h" =20 -static bool qom_get_bool(QTestState *s, const char *path, const char *prop= erty) -{ - QDict *r; - bool b; - - r =3D qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " - "{ 'path': %s, 'property': %s } }", path, property); - b =3D qdict_get_bool(r, "return"); - qobject_unref(r); - - return b; -} - -static void qom_set_bool(QTestState *s, const char *path, const char *prop= erty, - bool value) -{ - QDict *r; - - r =3D qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': " - "{ 'path': %s, 'property': %s, 'value': %i } }", - path, property, value); - qobject_unref(r); -} - static void test_set_colocated_pins(const void *data) { QTestState *s =3D (QTestState *)data; @@ -60,14 +36,14 @@ static void test_set_colocated_pins(const void *data) * gpioV4-7 occupy bits within a single 32-bit value, so we want to ma= ke * sure that modifying one doesn't affect the other. */ - qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); - qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); - qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); - qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); - g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); - g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); - g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); - g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); + qtest_qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); + g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); + g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); + g_assert(qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); + g_assert(!qtest_qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); } =20 int main(int argc, char **argv) diff --git a/tests/qtest/aspeed_smc-test.c b/tests/qtest/aspeed_smc-test.c index 87b40a0ef186..ec233315e6c6 100644 --- a/tests/qtest/aspeed_smc-test.c +++ b/tests/qtest/aspeed_smc-test.c @@ -26,6 +26,7 @@ #include "qemu/osdep.h" #include "qemu/bswap.h" #include "libqtest-single.h" +#include "qemu/bitops.h" =20 /* * ASPEED SPI Controller registers @@ -40,6 +41,7 @@ #define CTRL_FREADMODE 0x1 #define CTRL_WRITEMODE 0x2 #define CTRL_USERMODE 0x3 +#define SR_WEL BIT(1) =20 #define ASPEED_FMC_BASE 0x1E620000 #define ASPEED_FLASH_BASE 0x20000000 @@ -49,6 +51,8 @@ */ enum { JEDEC_READ =3D 0x9f, + RDSR =3D 0x5, + WRDI =3D 0x4, BULK_ERASE =3D 0xc7, READ =3D 0x03, PP =3D 0x02, @@ -348,6 +352,44 @@ static void test_write_page_mem(void) flash_reset(); } =20 +static void test_read_status_reg(void) +{ + uint8_t r; + + spi_conf(CONF_ENABLE_W0); + + spi_ctrl_start_user(); + writeb(ASPEED_FLASH_BASE, RDSR); + r =3D readb(ASPEED_FLASH_BASE); + spi_ctrl_stop_user(); + + g_assert_cmphex(r & SR_WEL, =3D=3D, 0); + g_assert(!qtest_qom_get_bool + (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl= e")); + + spi_ctrl_start_user(); + writeb(ASPEED_FLASH_BASE, WREN); + writeb(ASPEED_FLASH_BASE, RDSR); + r =3D readb(ASPEED_FLASH_BASE); + spi_ctrl_stop_user(); + + g_assert_cmphex(r & SR_WEL, =3D=3D, SR_WEL); + g_assert(qtest_qom_get_bool + (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl= e")); + + spi_ctrl_start_user(); + writeb(ASPEED_FLASH_BASE, WRDI); + writeb(ASPEED_FLASH_BASE, RDSR); + r =3D readb(ASPEED_FLASH_BASE); + spi_ctrl_stop_user(); + + g_assert_cmphex(r & SR_WEL, =3D=3D, 0); + g_assert(!qtest_qom_get_bool + (global_qtest, "/machine/soc/fmc/ssi.0/child[0]", "write-enabl= e")); + + flash_reset(); +} + static char tmp_path[] =3D "/tmp/qtest.m25p80.XXXXXX"; =20 int main(int argc, char **argv) @@ -373,6 +415,7 @@ int main(int argc, char **argv) qtest_add_func("/ast2400/smc/write_page", test_write_page); qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem); qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem); + qtest_add_func("/ast2400/smc/read_status_reg", test_read_status_reg); =20 ret =3D g_test_run(); =20 diff --git a/tests/qtest/libqtest.c b/tests/qtest/libqtest.c index 2e496184549d..8c159eacf5ed 100644 --- a/tests/qtest/libqtest.c +++ b/tests/qtest/libqtest.c @@ -1440,3 +1440,27 @@ void qtest_client_inproc_recv(void *opaque, const ch= ar *str) g_string_append(qts->rx, str); return; } + +void qtest_qom_set_bool(QTestState *s, const char *path, const char *prope= rty, + bool value) +{ + QDict *r; + + r =3D qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': " + "{ 'path': %s, 'property': %s, 'value': %i } }", + path, property, value); + qobject_unref(r); +} + +bool qtest_qom_get_bool(QTestState *s, const char *path, const char *prope= rty) +{ + QDict *r; + bool b; + + r =3D qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " + "{ 'path': %s, 'property': %s } }", path, property); + b =3D qdict_get_bool(r, "return"); + qobject_unref(r); + + return b; +} --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495598182856.4343079712603; Wed, 25 May 2022 09:19:58 -0700 (PDT) Received: from localhost ([::1]:35698 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttjm-0005v3-TB for importer@patchew.org; Wed, 25 May 2022 12:19:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36510) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSV-00074a-Lr; Wed, 25 May 2022 12:02:07 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:48649 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSR-00049O-L0; Wed, 25 May 2022 12:02:03 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRR44pYz4xDK; Thu, 26 May 2022 02:01:55 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRP3qNdz4xXj; Thu, 26 May 2022 02:01:53 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= , Jamin Lin , Peter Delevoryas Subject: [PULL 05/15] aspeed: Introduce a get_irq AspeedSoCClass method Date: Wed, 25 May 2022 18:01:26 +0200 Message-Id: <20220525160136.556277-6-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495599236100001 and make routine aspeed_soc_get_irq() common to all SoCs. This will be useful to share code. Cc: Jamin Lin Cc: Peter Delevoryas Reviewed-by: Peter Delevoryas Signed-off-by: C=C3=A9dric Le Goater Message-Id: <20220516055620.2380197-1-clg@kaod.org> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 3 +++ hw/arm/aspeed_ast10x0.c | 5 +++-- hw/arm/aspeed_ast2600.c | 5 +++-- hw/arm/aspeed_soc.c | 13 ++++++++++--- 4 files changed, 19 insertions(+), 7 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index e13af374b923..3789f38603e5 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -94,6 +94,7 @@ struct AspeedSoCClass { const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; + qemu_irq (*get_irq)(AspeedSoCState *s, int dev); }; =20 =20 @@ -153,4 +154,6 @@ enum { ASPEED_DEV_I3C, }; =20 +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); + #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 427154928254..9ae9efaac144 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -61,11 +61,11 @@ static const int aspeed_soc_ast1030_irqmap[] =3D { [ASPEED_DEV_KCS] =3D 138, /* 138 -> 142 */ }; =20 -static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) +static qemu_irq aspeed_soc_ast1030_get_irq(AspeedSoCState *s, int dev) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); =20 - return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ctrl]); + return qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[dev]); } =20 static void aspeed_soc_ast1030_init(Object *obj) @@ -280,6 +280,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *= klass, void *data) sc->irqmap =3D aspeed_soc_ast1030_irqmap; sc->memmap =3D aspeed_soc_ast1030_memmap; sc->num_cpus =3D 1; + sc->get_irq =3D aspeed_soc_ast1030_get_irq; } =20 static const TypeInfo aspeed_soc_ast1030_type_info =3D { diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index eedda7badc37..4161a0cc4bbe 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -114,11 +114,11 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_I3C] =3D 102, /* 102 -> 107 */ }; =20 -static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) +static qemu_irq aspeed_soc_ast2600_get_irq(AspeedSoCState *s, int dev) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); =20 - return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ctrl]); + return qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[dev]); } =20 static void aspeed_soc_ast2600_init(Object *obj) @@ -572,6 +572,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *= oc, void *data) sc->irqmap =3D aspeed_soc_ast2600_irqmap; sc->memmap =3D aspeed_soc_ast2600_memmap; sc->num_cpus =3D 2; + sc->get_irq =3D aspeed_soc_ast2600_get_irq; } =20 static const TypeInfo aspeed_soc_ast2600_type_info =3D { diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 58714cb2a01d..c339b5c74de5 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -121,11 +121,11 @@ static const int aspeed_soc_ast2400_irqmap[] =3D { =20 #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap =20 -static qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int ctrl) +static qemu_irq aspeed_soc_ast2400_get_irq(AspeedSoCState *s, int dev) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); =20 - return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[ctrl]); + return qdev_get_gpio_in(DEVICE(&s->vic), sc->irqmap[dev]); } =20 static void aspeed_soc_init(Object *obj) @@ -487,6 +487,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) sc->irqmap =3D aspeed_soc_ast2400_irqmap; sc->memmap =3D aspeed_soc_ast2400_memmap; sc->num_cpus =3D 1; + sc->get_irq =3D aspeed_soc_ast2400_get_irq; } =20 static const TypeInfo aspeed_soc_ast2400_type_info =3D { @@ -512,6 +513,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) sc->irqmap =3D aspeed_soc_ast2500_irqmap; sc->memmap =3D aspeed_soc_ast2500_memmap; sc->num_cpus =3D 1; + sc->get_irq =3D aspeed_soc_ast2400_get_irq; } =20 static const TypeInfo aspeed_soc_ast2500_type_info =3D { @@ -528,4 +530,9 @@ static void aspeed_soc_register_types(void) type_register_static(&aspeed_soc_ast2500_type_info); }; =20 -type_init(aspeed_soc_register_types) +type_init(aspeed_soc_register_types); + +qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) +{ + return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); +} --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653496096490620.524209648751; Wed, 25 May 2022 09:28:16 -0700 (PDT) Received: from localhost ([::1]:52688 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttrr-0001F6-Gk for importer@patchew.org; Wed, 25 May 2022 12:28:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36532) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSX-00074j-IX; Wed, 25 May 2022 12:02:07 -0400 Received: from gandalf.ozlabs.org ([150.107.74.76]:57471) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttST-00049Z-Ss; Wed, 25 May 2022 12:02:04 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRT6BYCz4xZv; Thu, 26 May 2022 02:01:57 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRS0dmYz4xXj; Thu, 26 May 2022 02:01:55 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 06/15] hw: aspeed: Add missing UART's Date: Wed, 25 May 2022 18:01:27 +0200 Message-Id: <20220525160136.556277-7-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=150.107.74.76; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653496097244100001 From: Peter Delevoryas This adds the missing UART memory and IRQ mappings for the AST2400, AST2500, AST2600, and AST1030. This also includes the new UART interfaces added in the AST2600 and AST1030 from UART6 to UART13. The addresses and interrupt numbers for these two later chips are identical. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220516062328.298336-2-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 8 ++++++++ hw/arm/aspeed_ast10x0.c | 24 ++++++++++++++++++++++++ hw/arm/aspeed_ast2600.c | 19 +++++++++++++++++++ hw/arm/aspeed_soc.c | 6 ++++++ 4 files changed, 57 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 3789f38603e5..709a78285b59 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -105,6 +105,14 @@ enum { ASPEED_DEV_UART3, ASPEED_DEV_UART4, ASPEED_DEV_UART5, + ASPEED_DEV_UART6, + ASPEED_DEV_UART7, + ASPEED_DEV_UART8, + ASPEED_DEV_UART9, + ASPEED_DEV_UART10, + ASPEED_DEV_UART11, + ASPEED_DEV_UART12, + ASPEED_DEV_UART13, ASPEED_DEV_VUART, ASPEED_DEV_FMC, ASPEED_DEV_SPI1, diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 9ae9efaac144..fa2cc4406c0d 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -33,14 +33,38 @@ static const hwaddr aspeed_soc_ast1030_memmap[] =3D { [ASPEED_DEV_SBC] =3D 0x7E6F2000, [ASPEED_DEV_GPIO] =3D 0x7E780000, [ASPEED_DEV_TIMER1] =3D 0x7E782000, + [ASPEED_DEV_UART1] =3D 0x7E783000, + [ASPEED_DEV_UART2] =3D 0x7E78D000, + [ASPEED_DEV_UART3] =3D 0x7E78E000, + [ASPEED_DEV_UART4] =3D 0x7E78F000, [ASPEED_DEV_UART5] =3D 0x7E784000, + [ASPEED_DEV_UART6] =3D 0x7E790000, + [ASPEED_DEV_UART7] =3D 0x7E790100, + [ASPEED_DEV_UART8] =3D 0x7E790200, + [ASPEED_DEV_UART9] =3D 0x7E790300, + [ASPEED_DEV_UART10] =3D 0x7E790400, + [ASPEED_DEV_UART11] =3D 0x7E790500, + [ASPEED_DEV_UART12] =3D 0x7E790600, + [ASPEED_DEV_UART13] =3D 0x7E790700, [ASPEED_DEV_WDT] =3D 0x7E785000, [ASPEED_DEV_LPC] =3D 0x7E789000, [ASPEED_DEV_I2C] =3D 0x7E7B0000, }; =20 static const int aspeed_soc_ast1030_irqmap[] =3D { + [ASPEED_DEV_UART1] =3D 47, + [ASPEED_DEV_UART2] =3D 48, + [ASPEED_DEV_UART3] =3D 49, + [ASPEED_DEV_UART4] =3D 50, [ASPEED_DEV_UART5] =3D 8, + [ASPEED_DEV_UART6] =3D 57, + [ASPEED_DEV_UART7] =3D 58, + [ASPEED_DEV_UART8] =3D 59, + [ASPEED_DEV_UART9] =3D 60, + [ASPEED_DEV_UART10] =3D 61, + [ASPEED_DEV_UART11] =3D 62, + [ASPEED_DEV_UART12] =3D 63, + [ASPEED_DEV_UART13] =3D 64, [ASPEED_DEV_GPIO] =3D 11, [ASPEED_DEV_TIMER1] =3D 16, [ASPEED_DEV_TIMER2] =3D 17, diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index 4161a0cc4bbe..f3ecc0f3b7c0 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -61,7 +61,18 @@ static const hwaddr aspeed_soc_ast2600_memmap[] =3D { [ASPEED_DEV_IBT] =3D 0x1E789140, [ASPEED_DEV_I2C] =3D 0x1E78A000, [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART2] =3D 0x1E78D000, + [ASPEED_DEV_UART3] =3D 0x1E78E000, + [ASPEED_DEV_UART4] =3D 0x1E78F000, [ASPEED_DEV_UART5] =3D 0x1E784000, + [ASPEED_DEV_UART6] =3D 0x1E790000, + [ASPEED_DEV_UART7] =3D 0x1E790100, + [ASPEED_DEV_UART8] =3D 0x1E790200, + [ASPEED_DEV_UART9] =3D 0x1E790300, + [ASPEED_DEV_UART10] =3D 0x1E790400, + [ASPEED_DEV_UART11] =3D 0x1E790500, + [ASPEED_DEV_UART12] =3D 0x1E790600, + [ASPEED_DEV_UART13] =3D 0x1E790700, [ASPEED_DEV_VUART] =3D 0x1E787000, [ASPEED_DEV_I3C] =3D 0x1E7A0000, [ASPEED_DEV_SDRAM] =3D 0x80000000, @@ -78,6 +89,14 @@ static const int aspeed_soc_ast2600_irqmap[] =3D { [ASPEED_DEV_UART3] =3D 49, [ASPEED_DEV_UART4] =3D 50, [ASPEED_DEV_UART5] =3D 8, + [ASPEED_DEV_UART6] =3D 57, + [ASPEED_DEV_UART7] =3D 58, + [ASPEED_DEV_UART8] =3D 59, + [ASPEED_DEV_UART9] =3D 60, + [ASPEED_DEV_UART10] =3D 61, + [ASPEED_DEV_UART11] =3D 62, + [ASPEED_DEV_UART12] =3D 63, + [ASPEED_DEV_UART13] =3D 64, [ASPEED_DEV_VUART] =3D 8, [ASPEED_DEV_FMC] =3D 39, [ASPEED_DEV_SDMC] =3D 0, diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index c339b5c74de5..96bc060680c9 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -48,6 +48,9 @@ static const hwaddr aspeed_soc_ast2400_memmap[] =3D { [ASPEED_DEV_ETH1] =3D 0x1E660000, [ASPEED_DEV_ETH2] =3D 0x1E680000, [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART2] =3D 0x1E78D000, + [ASPEED_DEV_UART3] =3D 0x1E78E000, + [ASPEED_DEV_UART4] =3D 0x1E78F000, [ASPEED_DEV_UART5] =3D 0x1E784000, [ASPEED_DEV_VUART] =3D 0x1E787000, [ASPEED_DEV_SDRAM] =3D 0x40000000, @@ -80,6 +83,9 @@ static const hwaddr aspeed_soc_ast2500_memmap[] =3D { [ASPEED_DEV_ETH1] =3D 0x1E660000, [ASPEED_DEV_ETH2] =3D 0x1E680000, [ASPEED_DEV_UART1] =3D 0x1E783000, + [ASPEED_DEV_UART2] =3D 0x1E78D000, + [ASPEED_DEV_UART3] =3D 0x1E78E000, + [ASPEED_DEV_UART4] =3D 0x1E78F000, [ASPEED_DEV_UART5] =3D 0x1E784000, [ASPEED_DEV_VUART] =3D 0x1E787000, [ASPEED_DEV_SDRAM] =3D 0x80000000, --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495598582330.36239999083637; Wed, 25 May 2022 09:19:58 -0700 (PDT) Received: from localhost ([::1]:35898 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttjo-00064I-ES for importer@patchew.org; Wed, 25 May 2022 12:19:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36566) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSb-00076f-9T; Wed, 25 May 2022 12:02:10 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:51697 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSU-00049r-IW; Wed, 25 May 2022 12:02:08 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRX19Rtz4xbt; Thu, 26 May 2022 02:02:00 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRV2jprz4xXj; Thu, 26 May 2022 02:01:58 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 07/15] hw: aspeed: Add uarts_num SoC attribute Date: Wed, 25 May 2022 18:01:28 +0200 Message-Id: <20220525160136.556277-8-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495599236100002 From: Peter Delevoryas AST2400 and AST2500 have 5 UART's, while the AST2600 and AST1030 have 13. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220516062328.298336-3-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast10x0.c | 1 + hw/arm/aspeed_ast2600.c | 1 + hw/arm/aspeed_soc.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 709a78285b59..669bc4985571 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -91,6 +91,7 @@ struct AspeedSoCClass { int ehcis_num; int wdts_num; int macs_num; + int uarts_num; const int *irqmap; const hwaddr *memmap; uint32_t num_cpus; diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index fa2cc4406c0d..bb8177e86c87 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -301,6 +301,7 @@ static void aspeed_soc_ast1030_class_init(ObjectClass *= klass, void *data) sc->ehcis_num =3D 0; sc->wdts_num =3D 4; sc->macs_num =3D 1; + sc->uarts_num =3D 13; sc->irqmap =3D aspeed_soc_ast1030_irqmap; sc->memmap =3D aspeed_soc_ast1030_memmap; sc->num_cpus =3D 1; diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index f3ecc0f3b7c0..a9523074a089 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -588,6 +588,7 @@ static void aspeed_soc_ast2600_class_init(ObjectClass *= oc, void *data) sc->ehcis_num =3D 2; sc->wdts_num =3D 4; sc->macs_num =3D 4; + sc->uarts_num =3D 13; sc->irqmap =3D aspeed_soc_ast2600_irqmap; sc->memmap =3D aspeed_soc_ast2600_memmap; sc->num_cpus =3D 2; diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 96bc060680c9..7008cd1af716 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -490,6 +490,7 @@ static void aspeed_soc_ast2400_class_init(ObjectClass *= oc, void *data) sc->ehcis_num =3D 1; sc->wdts_num =3D 2; sc->macs_num =3D 2; + sc->uarts_num =3D 5; sc->irqmap =3D aspeed_soc_ast2400_irqmap; sc->memmap =3D aspeed_soc_ast2400_memmap; sc->num_cpus =3D 1; @@ -516,6 +517,7 @@ static void aspeed_soc_ast2500_class_init(ObjectClass *= oc, void *data) sc->ehcis_num =3D 2; sc->wdts_num =3D 3; sc->macs_num =3D 2; + sc->uarts_num =3D 5; sc->irqmap =3D aspeed_soc_ast2500_irqmap; sc->memmap =3D aspeed_soc_ast2500_memmap; sc->num_cpus =3D 1; --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495388632105.32735864636129; Wed, 25 May 2022 09:16:28 -0700 (PDT) Received: from localhost ([::1]:54436 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttgQ-0007ZB-HY for importer@patchew.org; Wed, 25 May 2022 12:16:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36546) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSZ-000757-Gb; Wed, 25 May 2022 12:02:08 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:57957 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSW-0004A3-Pi; Wed, 25 May 2022 12:02:06 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRZ3LnXz4ySb; Thu, 26 May 2022 02:02:02 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRX4p4mz4xXj; Thu, 26 May 2022 02:02:00 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 08/15] hw: aspeed: Ensure AST1030 respects uart-default Date: Wed, 25 May 2022 18:01:29 +0200 Message-Id: <20220525160136.556277-9-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495390182100001 From: Peter Delevoryas The AST1030 machine initialization was not respecting the Aspeed SoC property "uart-default", which specifies which UART should be connected to the first serial device, it was just always connecting UART5. This doesn't change any behavior, because the default value for "uart-default" is UART5, but it makes it possible to override this in new machine definitions using the AST1030. Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220516062328.298336-4-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index bb8177e86c87..faafb800f386 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -215,9 +215,9 @@ static void aspeed_soc_ast1030_realize(DeviceState *dev= _soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 - /* UART5 - attach an 8250 to the IO space as our UART */ - serial_mm_init(get_system_memory(), sc->memmap[ASPEED_DEV_UART5], 2, - aspeed_soc_get_irq(s, ASPEED_DEV_UART5), + /* UART - attach an 8250 to the IO space as our UART */ + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, + aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); =20 /* Timer */ --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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Thu, 26 May 2022 02:02:04 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRZ6xMjz4xXj; Thu, 26 May 2022 02:02:02 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 09/15] hw: aspeed: Introduce common UART init function Date: Wed, 25 May 2022 18:01:30 +0200 Message-Id: <20220525160136.556277-10-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495398343100001 From: Peter Delevoryas Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220516062328.298336-5-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/arm/aspeed_soc.h | 1 + hw/arm/aspeed_ast10x0.c | 7 ++----- hw/arm/aspeed_ast2600.c | 7 ++----- hw/arm/aspeed_soc.c | 16 ++++++++++++---- 4 files changed, 17 insertions(+), 14 deletions(-) diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 669bc4985571..02a5a9ffcbd3 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -164,5 +164,6 @@ enum { }; =20 qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev); +void aspeed_soc_uart_init(AspeedSoCState *s); =20 #endif /* ASPEED_SOC_H */ diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index faafb800f386..938615d55f4a 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -15,7 +15,6 @@ #include "sysemu/sysemu.h" #include "hw/qdev-clock.h" #include "hw/misc/unimp.h" -#include "hw/char/serial.h" #include "hw/arm/aspeed_soc.h" =20 #define ASPEED_SOC_IOMEM_SIZE 0x00200000 @@ -215,10 +214,8 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) qdev_get_gpio_in(DEVICE(&s->armv7m), sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kc= s_4)); =20 - /* UART - attach an 8250 to the IO space as our UART */ - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, - aspeed_soc_get_irq(s, s->uart_default), - 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); + /* UART */ + aspeed_soc_uart_init(s); =20 /* Timer */ object_property_set_link(OBJECT(&s->timerctrl), "scu", OBJECT(&s->scu), diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index a9523074a089..b0a4199b6960 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -11,7 +11,6 @@ #include "qapi/error.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" -#include "hw/char/serial.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -372,10 +371,8 @@ static void aspeed_soc_ast2600_realize(DeviceState *de= v, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 - /* UART - attach an 8250 to the IO space as our UART */ - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, - aspeed_soc_get_irq(s, s->uart_default), 38400, - serial_hd(0), DEVICE_LITTLE_ENDIAN); + /* UART */ + aspeed_soc_uart_init(s); =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 7008cd1af716..912798a9c92f 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -303,10 +303,8 @@ static void aspeed_soc_realize(DeviceState *dev, Error= **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->adc), 0, aspeed_soc_get_irq(s, ASPEED_DEV_ADC)); =20 - /* UART - attach an 8250 to the IO space as our UART */ - serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, - aspeed_soc_get_irq(s, s->uart_default), 38400, - serial_hd(0), DEVICE_LITTLE_ENDIAN); + /* UART */ + aspeed_soc_uart_init(s); =20 /* I2C */ object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(s->dram_mr), @@ -544,3 +542,13 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) { return ASPEED_SOC_GET_CLASS(s)->get_irq(s, dev); } + +void aspeed_soc_uart_init(AspeedSoCState *s) +{ + AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + + /* Attach an 8250 to the IO space as our UART */ + serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, + aspeed_soc_get_irq(s, s->uart_default), 38400, + serial_hd(0), DEVICE_LITTLE_ENDIAN); +} --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495547515825.5781701706596; Wed, 25 May 2022 09:19:07 -0700 (PDT) Received: from localhost ([::1]:33182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttj0-0004BC-Am for importer@patchew.org; Wed, 25 May 2022 12:19:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36596) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSf-000793-7C; Wed, 25 May 2022 12:02:13 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:44733 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSb-0004AX-Ds; Wed, 25 May 2022 12:02:12 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRg0dqXz4ySr; Thu, 26 May 2022 02:02:07 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRd26T9z4xXj; Thu, 26 May 2022 02:02:05 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Peter Delevoryas , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 10/15] hw: aspeed: Init all UART's with serial devices Date: Wed, 25 May 2022 18:01:31 +0200 Message-Id: <20220525160136.556277-11-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495549003100001 From: Peter Delevoryas Background: AspeedMachineClass.uart_default specifies the serial console UART, which usually corresponds to the "stdout-path" in the device tree. The default value is UART5, since most boards use UART5 for this: amc->uart_default =3D ASPEED_DEV_UART5; Users can override AspeedMachineClass.uart_default in their board's machine class init to specify something besides UART5. For example, for fuji-bmc: amc->uart_default =3D ASPEED_DEV_UART1; We only connect this one UART, of the 5 UART's on the AST2400 and AST2500 and the 13 UART's on the AST2600 and AST1030, to a serial device that QEMU users can use. None of the other UART's are initialized, and the only way to override this attribute is by creating a specialized board definition, requiring QEMU source code changes and rebuilding. The result of this is that if you want to get serial console output on a board that uses UART3, you need to add a board definition. This was encountered by Zev in OpenBMC. [1] Changes: This commit initializes all of the UART's present on each Aspeed chip with serial devices and allows the QEMU user to connect as many or few as they like to serial devices. For example, you can still run QEMU and just connect stdout to the machine's default UART, without specifying any additional serial devices: qemu-system-arm -machine fuji-bmc \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -nographic However, if you don't want to add a special machine definition, you can now manually configure UART1 to connect to stdout and get serial console output, even if the machine's default is UART5: qemu-system-arm -machine ast2600-evb \ -drive file=3Dfuji.mtd,format=3Draw,if=3Dmtd \ -serial null -serial mon:stdio -display none In the example above, the first "-serial null" argument is connected to UART5, and "-serial mon:stdio" is connected to UART1. Another example: you can get serial console output from Wedge100, which uses UART3, by reusing the palmetto AST2400 machine and rewiring the serial device arguments: qemu-system-arm -machine palmetto-bmc \ -drive file=3Dwedge100.mtd,format=3Draw,if=3Dmtd \ -serial null -serial null -serial null \ -serial mon:stdio -display none There is a slight change in behavior introduced with this change: now, each UART's memory-mapped IO region will have a serial device model connected to it. Previously, all reads and writes to those regions would be ineffective and return zero values, but now some values will be nonzero, even when the user doesn't connect a serial device backend (like a socket, file, etc). For example, the line status register might indicate that the transmit buffer is empty now, whereas previously it might have always indicated it was full. [1] https://lore.kernel.org/openbmc/YnzGnWjkYdMUUNyM@hatter.bewilderbeest.n= et/ [2] https://github.com/facebook/openbmc/releases/download/v2021.49.0/fuji.m= td [3] https://github.com/facebook/openbmc/releases/download/v2021.49.0/wedge1= 00.mtd Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220516062328.298336-6-pdel@fb.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_soc.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 912798a9c92f..30574d4276ab 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -546,9 +546,18 @@ qemu_irq aspeed_soc_get_irq(AspeedSoCState *s, int dev) void aspeed_soc_uart_init(AspeedSoCState *s) { AspeedSoCClass *sc =3D ASPEED_SOC_GET_CLASS(s); + int i, uart; =20 /* Attach an 8250 to the IO space as our UART */ serial_mm_init(get_system_memory(), sc->memmap[s->uart_default], 2, aspeed_soc_get_irq(s, s->uart_default), 38400, serial_hd(0), DEVICE_LITTLE_ENDIAN); + for (i =3D 1, uart =3D ASPEED_DEV_UART1; i < sc->uarts_num; i++, uart+= +) { + if (uart =3D=3D s->uart_default) { + uart++; + } + serial_mm_init(get_system_memory(), sc->memmap[uart], 2, + aspeed_soc_get_irq(s, uart), 38400, + serial_hd(i), DEVICE_LITTLE_ENDIAN); + } } --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653496321450763.4299468858981; Wed, 25 May 2022 09:32:01 -0700 (PDT) Received: from localhost ([::1]:60046 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttvU-0006KF-Fm for importer@patchew.org; Wed, 25 May 2022 12:32:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36616) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSh-0007Fj-MM; Wed, 25 May 2022 12:02:15 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:48649 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSd-00049O-9L; Wed, 25 May 2022 12:02:15 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRj2kGfz4xXj; Thu, 26 May 2022 02:02:09 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRg4J7kz4xDK; Thu, 26 May 2022 02:02:07 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 11/15] hw/gpio Add GPIO read/write trace event. Date: Wed, 25 May 2022 18:01:32 +0200 Message-Id: <20220525160136.556277-12-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653496323377100003 From: Jamin Lin Add GPIO read/write trace event for aspeed model. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220525053444.27228-2-jamin_lin@aspeedtech.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_gpio.c | 54 +++++++++++++++++++++++++++++++------------ hw/gpio/trace-events | 4 ++++ 2 files changed, 43 insertions(+), 15 deletions(-) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 9b736e7a9f26..4620ea8e8b83 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -15,6 +15,7 @@ #include "qapi/visitor.h" #include "hw/irq.h" #include "migration/vmstate.h" +#include "trace.h" =20 #define GPIOS_PER_GROUP 8 =20 @@ -523,11 +524,15 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr= offset, uint32_t size) uint64_t idx =3D -1; const AspeedGPIOReg *reg; GPIOSets *set; + uint32_t value =3D 0; + uint64_t debounce_value; =20 idx =3D offset >> 2; if (idx >=3D GPIO_DEBOUNCE_TIME_1 && idx <=3D GPIO_DEBOUNCE_TIME_3) { idx -=3D GPIO_DEBOUNCE_TIME_1; - return (uint64_t) s->debounce_regs[idx]; + debounce_value =3D (uint64_t) s->debounce_regs[idx]; + trace_aspeed_gpio_read(offset, debounce_value); + return debounce_value; } =20 reg =3D &agc->reg_table[idx]; @@ -540,38 +545,55 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr= offset, uint32_t size) set =3D &s->sets[reg->set_idx]; switch (reg->type) { case gpio_reg_data_value: - return set->data_value; + value =3D set->data_value; + break; case gpio_reg_direction: - return set->direction; + value =3D set->direction; + break; case gpio_reg_int_enable: - return set->int_enable; + value =3D set->int_enable; + break; case gpio_reg_int_sens_0: - return set->int_sens_0; + value =3D set->int_sens_0; + break; case gpio_reg_int_sens_1: - return set->int_sens_1; + value =3D set->int_sens_1; + break; case gpio_reg_int_sens_2: - return set->int_sens_2; + value =3D set->int_sens_2; + break; case gpio_reg_int_status: - return set->int_status; + value =3D set->int_status; + break; case gpio_reg_reset_tolerant: - return set->reset_tol; + value =3D set->reset_tol; + break; case gpio_reg_debounce_1: - return set->debounce_1; + value =3D set->debounce_1; + break; case gpio_reg_debounce_2: - return set->debounce_2; + value =3D set->debounce_2; + break; case gpio_reg_cmd_source_0: - return set->cmd_source_0; + value =3D set->cmd_source_0; + break; case gpio_reg_cmd_source_1: - return set->cmd_source_1; + value =3D set->cmd_source_1; + break; case gpio_reg_data_read: - return set->data_read; + value =3D set->data_read; + break; case gpio_reg_input_mask: - return set->input_mask; + value =3D set->input_mask; + break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" HWADDR_PRIx"\n", __func__, offset); return 0; } + + trace_aspeed_gpio_read(offset, value); + return value; } =20 static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, @@ -585,6 +607,8 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, GPIOSets *set; uint32_t cleared; =20 + trace_aspeed_gpio_write(offset, data); + idx =3D offset >> 2; if (idx >=3D GPIO_DEBOUNCE_TIME_1 && idx <=3D GPIO_DEBOUNCE_TIME_3) { idx -=3D GPIO_DEBOUNCE_TIME_1; diff --git a/hw/gpio/trace-events b/hw/gpio/trace-events index 1dab99c5604d..9736b362ac18 100644 --- a/hw/gpio/trace-events +++ b/hw/gpio/trace-events @@ -27,3 +27,7 @@ sifive_gpio_read(uint64_t offset, uint64_t r) "offset 0x%= " PRIx64 " value 0x%" P sifive_gpio_write(uint64_t offset, uint64_t value) "offset 0x%" PRIx64 " v= alue 0x%" PRIx64 sifive_gpio_set(int64_t line, int64_t value) "line %" PRIi64 " value %" PR= Ii64 sifive_gpio_update_output_irq(int64_t line, int64_t value) "line %" PRIi64= " value %" PRIi64 + +# aspeed_gpio.c +aspeed_gpio_read(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " v= alue 0x%" PRIx64 +aspeed_gpio_write(uint64_t offset, uint64_t value) "offset: 0x%" PRIx64 " = value 0x%" PRIx64 --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653495600812804.6914569638144; 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Thu, 26 May 2022 02:02:09 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 12/15] hw/gpio: Add ASPEED GPIO model for AST1030 Date: Wed, 25 May 2022 18:01:33 +0200 Message-Id: <20220525160136.556277-13-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495601261100005 From: Jamin Lin AST1030 integrates one set of Parallel GPIO Controller with maximum 151 control pins, which are 21 groups (A~U, exclude pin: M6 M7 Q5 Q6 Q7 R0 R1 R4 R5 R6 R7 S0 S3 S4 S5 S6 S7 ) and the group T and U are input only. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220525053444.27228-3-jamin_lin@aspeedtech.com> Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed_ast10x0.c | 11 +++++++++++ hw/gpio/aspeed_gpio.c | 27 +++++++++++++++++++++++++++ 2 files changed, 38 insertions(+) diff --git a/hw/arm/aspeed_ast10x0.c b/hw/arm/aspeed_ast10x0.c index 938615d55f4a..d53454168403 100644 --- a/hw/arm/aspeed_ast10x0.c +++ b/hw/arm/aspeed_ast10x0.c @@ -136,6 +136,9 @@ static void aspeed_soc_ast1030_init(Object *obj) snprintf(typename, sizeof(typename), "aspeed.wdt-%s", socname); object_initialize_child(obj, "wdt[*]", &s->wdt[i], typename); } + + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); + object_initialize_child(obj, "gpio", &s->gpio, typename); } =20 static void aspeed_soc_ast1030_realize(DeviceState *dev_soc, Error **errp) @@ -281,6 +284,14 @@ static void aspeed_soc_ast1030_realize(DeviceState *de= v_soc, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->wdt[i]), 0, sc->memmap[ASPEED_DEV_WDT] + i * awc->offset); } + + /* GPIO */ + if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->memmap[ASPEED_DEV_GPI= O]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_GPIO)); } =20 static void aspeed_soc_ast1030_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 4620ea8e8b83..5138fe812b9e 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -819,6 +819,15 @@ static GPIOSetProperties ast2600_1_8v_set_props[ASPEED= _GPIO_MAX_NR_SETS] =3D { [1] =3D {0x0000000f, 0x0000000f, {"18E"} }, }; =20 +static GPIOSetProperties ast1030_set_props[ASPEED_GPIO_MAX_NR_SETS] =3D { + [0] =3D {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, + [1] =3D {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, + [2] =3D {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, + [3] =3D {0xffffff3f, 0xffffff3f, {"M", "N", "O", "P"} }, + [4] =3D {0xff060c1f, 0x00060c1f, {"Q", "R", "S", "T"} }, + [5] =3D {0x000000ff, 0x00000000, {"U"} }, +}; + static const MemoryRegionOps aspeed_gpio_ops =3D { .read =3D aspeed_gpio_read, .write =3D aspeed_gpio_write, @@ -971,6 +980,16 @@ static void aspeed_gpio_ast2600_1_8v_class_init(Object= Class *klass, void *data) agc->reg_table =3D aspeed_1_8v_gpios; } =20 +static void aspeed_gpio_1030_class_init(ObjectClass *klass, void *data) +{ + AspeedGPIOClass *agc =3D ASPEED_GPIO_CLASS(klass); + + agc->props =3D ast1030_set_props; + agc->nr_gpio_pins =3D 151; + agc->nr_gpio_sets =3D 6; + agc->reg_table =3D aspeed_3_3v_gpios; +} + static const TypeInfo aspeed_gpio_info =3D { .name =3D TYPE_ASPEED_GPIO, .parent =3D TYPE_SYS_BUS_DEVICE, @@ -1008,6 +1027,13 @@ static const TypeInfo aspeed_gpio_ast2600_1_8v_info = =3D { .instance_init =3D aspeed_gpio_init, }; =20 +static const TypeInfo aspeed_gpio_ast1030_info =3D { + .name =3D TYPE_ASPEED_GPIO "-ast1030", + .parent =3D TYPE_ASPEED_GPIO, + .class_init =3D aspeed_gpio_1030_class_init, + .instance_init =3D aspeed_gpio_init, +}; + static void aspeed_gpio_register_types(void) { type_register_static(&aspeed_gpio_info); @@ -1015,6 +1041,7 @@ static void aspeed_gpio_register_types(void) type_register_static(&aspeed_gpio_ast2500_info); type_register_static(&aspeed_gpio_ast2600_3_3v_info); type_register_static(&aspeed_gpio_ast2600_1_8v_info); + type_register_static(&aspeed_gpio_ast1030_info); } =20 type_init(aspeed_gpio_register_types); --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165349655316996.12495303287562; Wed, 25 May 2022 09:35:53 -0700 (PDT) Received: from localhost ([::1]:38182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttzD-0002KR-R8 for importer@patchew.org; Wed, 25 May 2022 12:35:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36676) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSm-0007RJ-F7; Wed, 25 May 2022 12:02:20 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:44733 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSj-0004AX-14; Wed, 25 May 2022 12:02:20 -0400 Received: from gandalf.ozlabs.org (mail.ozlabs.org [IPv6:2404:9400:2221:ea00::3]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRn6sKYz4xbt; Thu, 26 May 2022 02:02:13 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRm1Hwtz4xDK; Thu, 26 May 2022 02:02:11 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 13/15] hw/gpio support GPIO index mode for write operation. Date: Wed, 25 May 2022 18:01:34 +0200 Message-Id: <20220525160136.556277-14-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653496555044100001 From: Jamin Lin It did not support GPIO index mode for read operation. Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220525053444.27228-4-jamin_lin@aspeedtech.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/gpio/aspeed_gpio.h | 14 +++ hw/gpio/aspeed_gpio.c | 168 ++++++++++++++++++++++++++++++++++ 2 files changed, 182 insertions(+) diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 6dee3cd43893..41b36524d062 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -50,6 +50,20 @@ enum GPIORegType { gpio_reg_input_mask, }; =20 +/* GPIO index mode */ +enum GPIORegIndexType { + gpio_reg_idx_data =3D 0, + gpio_reg_idx_direction, + gpio_reg_idx_interrupt, + gpio_reg_idx_debounce, + gpio_reg_idx_tolerance, + gpio_reg_idx_cmd_src, + gpio_reg_idx_input_mask, + gpio_reg_idx_reserved, + gpio_reg_idx_new_w_cmd_src, + gpio_reg_idx_new_r_cmd_src, +}; + typedef struct AspeedGPIOReg { uint16_t set_idx; enum GPIORegType type; diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index 5138fe812b9e..c834bf19f5ce 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -16,6 +16,7 @@ #include "hw/irq.h" #include "migration/vmstate.h" #include "trace.h" +#include "hw/registerfields.h" =20 #define GPIOS_PER_GROUP 8 =20 @@ -204,6 +205,28 @@ #define GPIO_1_8V_MEM_SIZE 0x1D8 #define GPIO_1_8V_REG_ARRAY_SIZE (GPIO_1_8V_MEM_SIZE >> 2) =20 +/* + * GPIO index mode support + * It only supports write operation + */ +REG32(GPIO_INDEX_REG, 0x2AC) + FIELD(GPIO_INDEX_REG, NUMBER, 0, 8) + FIELD(GPIO_INDEX_REG, COMMAND, 12, 1) + FIELD(GPIO_INDEX_REG, TYPE, 16, 4) + FIELD(GPIO_INDEX_REG, DATA_VALUE, 20, 1) + FIELD(GPIO_INDEX_REG, DIRECTION, 20, 1) + FIELD(GPIO_INDEX_REG, INT_ENABLE, 20, 1) + FIELD(GPIO_INDEX_REG, INT_SENS_0, 21, 1) + FIELD(GPIO_INDEX_REG, INT_SENS_1, 22, 1) + FIELD(GPIO_INDEX_REG, INT_SENS_2, 23, 1) + FIELD(GPIO_INDEX_REG, INT_STATUS, 24, 1) + FIELD(GPIO_INDEX_REG, DEBOUNCE_1, 20, 1) + FIELD(GPIO_INDEX_REG, DEBOUNCE_2, 21, 1) + FIELD(GPIO_INDEX_REG, RESET_TOLERANT, 20, 1) + FIELD(GPIO_INDEX_REG, COMMAND_SRC_0, 20, 1) + FIELD(GPIO_INDEX_REG, COMMAND_SRC_1, 21, 1) + FIELD(GPIO_INDEX_REG, INPUT_MASK, 20, 1) + static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpi= o) { uint32_t falling_edge =3D 0, rising_edge =3D 0; @@ -596,6 +619,144 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr= offset, uint32_t size) return value; } =20 +static void aspeed_gpio_write_index_mode(void *opaque, hwaddr offset, + uint64_t data, uint32_t si= ze) +{ + + AspeedGPIOState *s =3D ASPEED_GPIO(opaque); + AspeedGPIOClass *agc =3D ASPEED_GPIO_GET_CLASS(s); + const GPIOSetProperties *props; + GPIOSets *set; + uint32_t reg_idx_number =3D FIELD_EX32(data, GPIO_INDEX_REG, NUMBER); + uint32_t reg_idx_type =3D FIELD_EX32(data, GPIO_INDEX_REG, TYPE); + uint32_t reg_idx_command =3D FIELD_EX32(data, GPIO_INDEX_REG, COMMAND); + uint32_t set_idx =3D reg_idx_number / ASPEED_GPIOS_PER_SET; + uint32_t pin_idx =3D reg_idx_number % ASPEED_GPIOS_PER_SET; + uint32_t group_idx =3D pin_idx / GPIOS_PER_GROUP; + uint32_t reg_value =3D 0; + uint32_t cleared; + + set =3D &s->sets[set_idx]; + props =3D &agc->props[set_idx]; + + if (reg_idx_command) + qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" + PRIx64 "index mode wrong command 0x%x\n", + __func__, offset, data, reg_idx_command); + + switch (reg_idx_type) { + case gpio_reg_idx_data: + reg_value =3D set->data_read; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, DATA_VALUE)= ); + reg_value &=3D props->output; + reg_value =3D update_value_control_source(set, set->data_value, + reg_value); + set->data_read =3D reg_value; + aspeed_gpio_update(s, set, reg_value); + return; + case gpio_reg_idx_direction: + reg_value =3D set->direction; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, DIRECTION)); + /* + * where data is the value attempted to be written to the pin: + * pin type | input mask | output mask | expected value + * ------------------------------------------------------------ + * bidirectional | 1 | 1 | data + * input only | 1 | 0 | 0 + * output only | 0 | 1 | 1 + * no pin | 0 | 0 | 0 + * + * which is captured by: + * data =3D ( data | ~input) & output; + */ + reg_value =3D (reg_value | ~props->input) & props->output; + set->direction =3D update_value_control_source(set, set->direction, + reg_value); + break; + case gpio_reg_idx_interrupt: + reg_value =3D set->int_enable; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, INT_ENABLE)= ); + set->int_enable =3D update_value_control_source(set, set->int_enab= le, + reg_value); + reg_value =3D set->int_sens_0; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_0)= ); + set->int_sens_0 =3D update_value_control_source(set, set->int_sens= _0, + reg_value); + reg_value =3D set->int_sens_1; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_1)= ); + set->int_sens_1 =3D update_value_control_source(set, set->int_sens= _1, + reg_value); + reg_value =3D set->int_sens_2; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, INT_SENS_2)= ); + set->int_sens_2 =3D update_value_control_source(set, set->int_sens= _2, + reg_value); + /* set interrupt status */ + reg_value =3D set->int_status; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, INT_STATUS)= ); + cleared =3D ctpop32(reg_value & set->int_status); + if (s->pending && cleared) { + assert(s->pending >=3D cleared); + s->pending -=3D cleared; + } + set->int_status &=3D ~reg_value; + break; + case gpio_reg_idx_debounce: + reg_value =3D set->debounce_1; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_1)= ); + set->debounce_1 =3D update_value_control_source(set, set->debounce= _1, + reg_value); + reg_value =3D set->debounce_2; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, DEBOUNCE_2)= ); + set->debounce_2 =3D update_value_control_source(set, set->debounce= _2, + reg_value); + return; + case gpio_reg_idx_tolerance: + reg_value =3D set->reset_tol; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, RESET_TOLER= ANT)); + set->reset_tol =3D update_value_control_source(set, set->reset_tol, + reg_value); + return; + case gpio_reg_idx_cmd_src: + reg_value =3D set->cmd_source_0; + reg_value =3D deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC= _0)); + set->cmd_source_0 =3D reg_value & ASPEED_CMD_SRC_MASK; + reg_value =3D set->cmd_source_1; + reg_value =3D deposit32(reg_value, GPIOS_PER_GROUP * group_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, COMMAND_SRC= _1)); + set->cmd_source_1 =3D reg_value & ASPEED_CMD_SRC_MASK; + return; + case gpio_reg_idx_input_mask: + reg_value =3D set->input_mask; + reg_value =3D deposit32(reg_value, pin_idx, 1, + FIELD_EX32(data, GPIO_INDEX_REG, INPUT_MASK)= ); + /* + * feeds into interrupt generation + * 0: read from data value reg will be updated + * 1: read from data value reg will not be updated + */ + set->input_mask =3D reg_value & props->input; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: offset 0x%" PRIx64 "data 0x%" + PRIx64 "index mode wrong type 0x%x\n", + __func__, offset, data, reg_idx_type); + return; + } + aspeed_gpio_update(s, set, set->data_value); + return; +} + static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, uint32_t size) { @@ -610,6 +771,13 @@ static void aspeed_gpio_write(void *opaque, hwaddr off= set, uint64_t data, trace_aspeed_gpio_write(offset, data); =20 idx =3D offset >> 2; + + /* check gpio index mode */ + if (idx =3D=3D R_GPIO_INDEX_REG) { + aspeed_gpio_write_index_mode(opaque, offset, data, size); + return; + } + if (idx >=3D GPIO_DEBOUNCE_TIME_1 && idx <=3D GPIO_DEBOUNCE_TIME_3) { idx -=3D GPIO_DEBOUNCE_TIME_1; s->debounce_regs[idx] =3D (uint32_t) data; --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16534957634537.698640349436687; Wed, 25 May 2022 09:22:43 -0700 (PDT) Received: from localhost ([::1]:42766 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nttmT-0002Ro-Sh for importer@patchew.org; Wed, 25 May 2022 12:22:41 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSm-0007QH-1l; Wed, 25 May 2022 12:02:20 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:48649 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttSj-00049O-9C; Wed, 25 May 2022 12:02:19 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRr1qgTz4ySb; Thu, 26 May 2022 02:02:16 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRp3Ndgz4xDK; Thu, 26 May 2022 02:02:14 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Jamin Lin , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 14/15] hw/gpio: replace HWADDR_PRIx with PRIx64 Date: Wed, 25 May 2022 18:01:35 +0200 Message-Id: <20220525160136.556277-15-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653495764367100001 From: Jamin Lin 1. replace HWADDR_PRIx with PRIx64 2. fix indent issue Signed-off-by: Jamin Lin Reviewed-by: C=C3=A9dric Le Goater Message-Id: <20220525053444.27228-5-jamin_lin@aspeedtech.com> Signed-off-by: C=C3=A9dric Le Goater --- include/hw/gpio/aspeed_gpio.h | 2 +- hw/gpio/aspeed_gpio.c | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h index 41b36524d062..904eecf62c4c 100644 --- a/include/hw/gpio/aspeed_gpio.h +++ b/include/hw/gpio/aspeed_gpio.h @@ -67,7 +67,7 @@ enum GPIORegIndexType { typedef struct AspeedGPIOReg { uint16_t set_idx; enum GPIORegType type; - } AspeedGPIOReg; +} AspeedGPIOReg; =20 struct AspeedGPIOClass { SysBusDevice parent_obj; diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index c834bf19f5ce..a62a673857c2 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -561,7 +561,7 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr o= ffset, uint32_t size) reg =3D &agc->reg_table[idx]; if (reg->set_idx >=3D agc->nr_gpio_sets) { qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" - HWADDR_PRIx"\n", __func__, offset); + PRIx64"\n", __func__, offset); return 0; } =20 @@ -611,7 +611,7 @@ static uint64_t aspeed_gpio_read(void *opaque, hwaddr o= ffset, uint32_t size) break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" - HWADDR_PRIx"\n", __func__, offset); + PRIx64"\n", __func__, offset); return 0; } =20 @@ -787,7 +787,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, reg =3D &agc->reg_table[idx]; if (reg->set_idx >=3D agc->nr_gpio_sets) { qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" - HWADDR_PRIx"\n", __func__, offset); + PRIx64"\n", __func__, offset); return; } =20 @@ -872,7 +872,7 @@ static void aspeed_gpio_write(void *opaque, hwaddr offs= et, uint64_t data, break; default: qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" - HWADDR_PRIx"\n", __func__, offset); + PRIx64"\n", __func__, offset); return; } aspeed_gpio_update(s, set, set->data_value); --=20 2.35.3 From nobody Sat May 18 19:24:28 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1653496672243543.3438971473062; Wed, 25 May 2022 09:37:52 -0700 (PDT) Received: from localhost ([::1]:44890 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1ntu19-00071B-5r for importer@patchew.org; Wed, 25 May 2022 12:37:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:36762) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttT7-0008Fz-AK; Wed, 25 May 2022 12:02:41 -0400 Received: from mail.ozlabs.org ([2404:9400:2221:ea00::3]:53757 helo=gandalf.ozlabs.org) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nttT5-0004B6-HX; Wed, 25 May 2022 12:02:41 -0400 Received: from gandalf.ozlabs.org (gandalf.ozlabs.org [150.107.74.76]) by gandalf.ozlabs.org (Postfix) with ESMTP id 4L7bRt3vsrz4ySg; Thu, 26 May 2022 02:02:18 +1000 (AEST) Received: from authenticated.ozlabs.org (localhost [127.0.0.1]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mail.ozlabs.org (Postfix) with ESMTPSA id 4L7bRr5SjGz4xDK; Thu, 26 May 2022 02:02:16 +1000 (AEST) From: =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: Peter Maydell , Howard Chiu , =?UTF-8?q?C=C3=A9dric=20Le=20Goater?= Subject: [PULL 15/15] hw/arm/aspeed: Add i2c devices for AST2600 EVB Date: Wed, 25 May 2022 18:01:36 +0200 Message-Id: <20220525160136.556277-16-clg@kaod.org> X-Mailer: git-send-email 2.35.3 In-Reply-To: <20220525160136.556277-1-clg@kaod.org> References: <20220525160136.556277-1-clg@kaod.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2404:9400:2221:ea00::3; envelope-from=SRS0=Lufh=WB=kaod.org=clg@ozlabs.org; helo=gandalf.ozlabs.org X-Spam_score_int: -16 X-Spam_score: -1.7 X-Spam_bar: - X-Spam_report: (-1.7 / 5.0 requ) BAYES_00=-1.9, HEADER_FROM_DIFFERENT_DOMAINS=0.249, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1653496673992100001 From: Howard Chiu Add EEPROM and LM75 temperature sensor according to hardware schematic Signed-off-by: Howard Chiu Reviewed-by: C=C3=A9dric Le Goater Signed-off-by: C=C3=A9dric Le Goater --- hw/arm/aspeed.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 725c169488dc..98dc185acd9a 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -527,8 +527,15 @@ static void ast2500_evb_i2c_init(AspeedMachineState *b= mc) =20 static void ast2600_evb_i2c_init(AspeedMachineState *bmc) { - /* Start with some devices on our I2C busses */ - ast2500_evb_i2c_init(bmc); + AspeedSoCState *soc =3D &bmc->soc; + uint8_t *eeprom_buf =3D g_malloc0(8 * 1024); + + smbus_eeprom_init_one(aspeed_i2c_get_bus(&soc->i2c, 7), 0x50, + eeprom_buf); + + /* LM75 is compatible with TMP105 driver */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), + TYPE_TMP105, 0x4d); } =20 static void romulus_bmc_i2c_init(AspeedMachineState *bmc) --=20 2.35.3