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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id e2-20020adfa742000000b0020c5253d8f2sm180183wrd.62.2022.05.19.10.37.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 19 May 2022 10:37:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=meQUJhRKZaTP1fZizivTTv8omOog8uzhP7A+DYadpWQ=; b=Y14yRL6yINm6csdwm+BOjUL4NNdyin0CgqLincXQZxcBJ0FZjKL1kzlEDsOo8wrcaT GU94QQaueqFUW/QSdQ71kE/PpQRKHIXv5gp8UDiuDN3lnbZnBJe0tFFVYna8ks3rh7vj ESXk6j9OFQoqQwDCTYM0N6uvMEtg0I7BJ+1PnGf0FmxrLrii+k4t+C4JFe9TZg0P3Heq isUZ0jeGs7jeUw2sGSVvYebys7p4d2Et8v07o8hZmAqCtH4uuGNbaqjJ7PghCG0phku7 sNEB1NZ24YZAiN8hC+g2exYwfVZmrO6ZWWy7waFhT9NQQ0FtM/QxkkyOC/NA9LGsqpJx mwIQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=meQUJhRKZaTP1fZizivTTv8omOog8uzhP7A+DYadpWQ=; b=IjbEweDw1ZvswWh0oolNRiutl1KlT8ss4Ihhpi+fLkw5289EbAg9OKc99TlbeNhTOs n/9iziVHN5mI1w84gocvB5VAze7Mu86zEH6d5lANvIXIq9gw8O7zQecgUHr+Kae4vrBt SwP5urqZw2uWDMUBEdqX8TBlB/tt8anUxUA8S7tJg3R5mMNwBssnqO4/CoxseQsoWsW3 FdsaFzFMG0bjvL5WkJuWYhcmXIin/iSd/t9S8cC/cNO3rdOM+VtS0xPGlh5Y+6kQbsk8 vfk4gtw9gpThRwpsx533t+XXA1xE0CWo6C/b+y2lByGWi6/jR89FF1sMw6RK7rZKyp8d vu0g== X-Gm-Message-State: AOAM531DJ2lG8rIconqKJ1XD1AgfxRfhSVTsdsPZZYw12Zx3YF4OuxTp iYBo4vVMTL2Q5MAYfmJPj/mVcXYAUpH+dg== X-Google-Smtp-Source: ABdhPJx2Lc0YDaZS8/+zpetvhcZnwdUm2XSvUk7Fzz7lQwYkfi8TByOMV6/wb1aD9iOz/Wb28SWHVA== X-Received: by 2002:a5d:6042:0:b0:20e:65c0:f69b with SMTP id j2-20020a5d6042000000b0020e65c0f69bmr5076252wrt.524.1652981831975; Thu, 19 May 2022 10:37:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/22] target/arm: Use FIELD definitions for CPACR, CPTR_ELx Date: Thu, 19 May 2022 18:36:51 +0100 Message-Id: <20220519173651.399295-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220519173651.399295-1-peter.maydell@linaro.org> References: <20220519173651.399295-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652983358202100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220517054850.177016-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 44 +++++++++++++++++++++++++++++++----- hw/arm/boot.c | 2 +- target/arm/cpu.c | 11 ++++++--- target/arm/helper.c | 54 ++++++++++++++++++++++----------------------- 4 files changed, 75 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index fac526a4905..c1865ad5dad 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1261,11 +1261,45 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 -#define CPTR_TCPAC (1U << 31) -#define CPTR_TTA (1U << 20) -#define CPTR_TFP (1U << 10) -#define CPTR_TZ (1U << 8) /* CPTR_EL2 */ -#define CPTR_EZ (1U << 8) /* CPTR_EL3 */ +/* Bit definitions for CPACR (AArch32 only) */ +FIELD(CPACR, CP10, 20, 2) +FIELD(CPACR, CP11, 22, 2) +FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ +FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ +FIELD(CPACR, ASEDIS, 31, 1) + +/* Bit definitions for CPACR_EL1 (AArch64 only) */ +FIELD(CPACR_EL1, ZEN, 16, 2) +FIELD(CPACR_EL1, FPEN, 20, 2) +FIELD(CPACR_EL1, SMEN, 24, 2) +FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ + +/* Bit definitions for HCPTR (AArch32 only) */ +FIELD(HCPTR, TCP10, 10, 1) +FIELD(HCPTR, TCP11, 11, 1) +FIELD(HCPTR, TASE, 15, 1) +FIELD(HCPTR, TTA, 20, 1) +FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ +FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ + +/* Bit definitions for CPTR_EL2 (AArch64 only) */ +FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ +FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ +FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ +FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ +FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ +FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ +FIELD(CPTR_EL2, TTA, 28, 1) +FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ +FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ + +/* Bit definitions for CPTR_EL3 (AArch64 only) */ +FIELD(CPTR_EL3, EZ, 8, 1) +FIELD(CPTR_EL3, TFP, 10, 1) +FIELD(CPTR_EL3, ESM, 12, 1) +FIELD(CPTR_EL3, TTA, 20, 1) +FIELD(CPTR_EL3, TAM, 30, 1) +FIELD(CPTR_EL3, TCPAC, 31, 1) =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a47f38dfc90..a8de33fd647 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -761,7 +761,7 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |=3D SCR_ATA; } if (cpu_isar_feature(aa64_sve, cpu)) { - env->cp15.cptr_el[3] |=3D CPTR_EZ; + env->cp15.cptr_el[3] |=3D R_CPTR_EL3_EZ_MASK; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 029f644768b..d2bd74c2ed4 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -201,9 +201,11 @@ static void arm_cpu_reset(DeviceState *dev) /* Trap on btype=3D3 for PACIxSP. */ env->cp15.sctlr_el[1] |=3D SCTLR_BT0; /* and to the FP/Neon instructions */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, FPEN, 3); /* and to the SVE instructions */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { env->vfp.zcr_el[1] =3D @@ -252,7 +254,10 @@ static void arm_cpu_reset(DeviceState *dev) } else { #if defined(CONFIG_USER_ONLY) /* Userspace expects access to cp10 and cp11 for FP/Neon */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR, CP10, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR, CP11, 3); #endif } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 7d983d7fffb..40da63913c9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -766,11 +766,14 @@ static void cpacr_write(CPUARMState *env, const ARMCP= RegInfo *ri, */ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); + mask |=3D R_CPACR_ASEDIS_MASK | + R_CPACR_D32DIS_MASK | + R_CPACR_CP11_MASK | + R_CPACR_CP10_MASK; =20 if (!arm_feature(env, ARM_FEATURE_NEON)) { /* ASEDIS [31] bit is RAO/WI */ - value |=3D (1 << 31); + value |=3D R_CPACR_ASEDIS_MASK; } =20 /* VFPv3 and upwards with NEON implement 32 double precision @@ -778,7 +781,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ - value |=3D (1 << 30); + value |=3D R_CPACR_D32DIS_MASK; } } value &=3D mask; @@ -790,8 +793,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); - value |=3D env->cp15.cpacr_el1 & (0xf << 20); + mask =3D R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; + value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); } =20 env->cp15.cpacr_el1 =3D value; @@ -807,7 +810,7 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMC= PRegInfo *ri) =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); + value =3D ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); } return value; } @@ -827,11 +830,11 @@ static CPAccessResult cpacr_access(CPUARMState *env, = const ARMCPRegInfo *ri, if (arm_feature(env, ARM_FEATURE_V8)) { /* Check if CPACR accesses are to be trapped to EL2 */ if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && - (env->cp15.cptr_el[2] & CPTR_TCPAC)) { + FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { return CP_ACCESS_TRAP_EL2; /* Check if CPACR accesses are to be trapped to EL3 */ } else if (arm_current_el(env) < 3 && - (env->cp15.cptr_el[3] & CPTR_TCPAC)) { + FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { return CP_ACCESS_TRAP_EL3; } } @@ -843,7 +846,8 @@ static CPAccessResult cptr_access(CPUARMState *env, con= st ARMCPRegInfo *ri, bool isread) { /* Check if CPTR accesses are set to trap to EL3 */ - if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { + if (arm_current_el(env) =3D=3D 2 && + FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { return CP_ACCESS_TRAP_EL3; } =20 @@ -5343,8 +5347,8 @@ static void cptr_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0x3 << 10); - value |=3D env->cp15.cptr_el[2] & (0x3 << 10); + uint64_t mask =3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; + value =3D (value & ~mask) | (env->cp15.cptr_el[2] & mask); } env->cp15.cptr_el[2] =3D value; } @@ -5359,7 +5363,7 @@ static uint64_t cptr_el2_read(CPUARMState *env, const= ARMCPRegInfo *ri) =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value |=3D 0x3 << 10; + value |=3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; } return value; } @@ -6147,8 +6151,7 @@ int sve_exception_el(CPUARMState *env, int el) uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); =20 if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - /* Check CPACR.ZEN. */ - switch (extract32(env->cp15.cpacr_el1, 16, 2)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { case 1: if (el !=3D 0) { break; @@ -6161,7 +6164,7 @@ int sve_exception_el(CPUARMState *env, int el) } =20 /* Check CPACR.FPEN. */ - switch (extract32(env->cp15.cpacr_el1, 20, 2)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { case 1: if (el !=3D 0) { break; @@ -6178,8 +6181,7 @@ int sve_exception_el(CPUARMState *env, int el) */ if (el <=3D 2) { if (hcr_el2 & HCR_E2H) { - /* Check CPTR_EL2.ZEN. */ - switch (extract32(env->cp15.cptr_el[2], 16, 2)) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: if (el !=3D 0 || !(hcr_el2 & HCR_TGE)) { break; @@ -6190,8 +6192,7 @@ int sve_exception_el(CPUARMState *env, int el) return 2; } =20 - /* Check CPTR_EL2.FPEN. */ - switch (extract32(env->cp15.cptr_el[2], 20, 2)) { + switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { case 1: if (el =3D=3D 2 || !(hcr_el2 & HCR_TGE)) { break; @@ -6202,10 +6203,10 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } } else if (arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (env->cp15.cptr_el[2] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { return 0; } } @@ -6213,7 +6214,7 @@ int sve_exception_el(CPUARMState *env, int el) =20 /* CPTR_EL3. Since EZ is negative we must check for EL3. */ if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { return 3; } #endif @@ -13396,7 +13397,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) * This register is ignored if E2H+TGE are both set. */ if ((hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { - int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + int fpen =3D FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); =20 switch (fpen) { case 0: @@ -13442,8 +13443,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) */ if (cur_el <=3D 2) { if (hcr_el2 & HCR_E2H) { - /* Check CPTR_EL2.FPEN. */ - switch (extract32(env->cp15.cptr_el[2], 20, 2)) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { case 1: if (cur_el !=3D 0 || !(hcr_el2 & HCR_TGE)) { break; @@ -13454,14 +13454,14 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 2; } } else if (arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { return 2; } } } =20 /* CPTR_EL3 : present in v8 */ - if (env->cp15.cptr_el[3] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { /* Trap all FP ops to EL3 */ return 3; } --=20 2.25.1