From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652767405; cv=none; d=zohomail.com; s=zohoarc; b=G+/eiLgP+8pFJ7yXodGesv/PuS4N/QV4nrfcKnEUngnTztE9uxn1lltJLMsUjAr1n7omK5krdvebBP84MvPep05q9w/TWasFOLFHeQBchDCqpzXW2KASqFly/RlFkXG6d0U5B7BOA2J1fB+OFhWWA5t9XHpK80hA+rmFqmO/CzQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652767405; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=xAd7na+2KxBtPMtY2na7BNVtRH2LfOqAnHHLmai2Ves=; b=DSGgnAJgvvKf5HOZRTuhv82IPkaQONG1X3ONgueCrfB/i19hsIwW6xQG0p/bVx0YA2aQc5yNvKckDlU9AEF9RHdkEIrIbKJWNuWT9Q7Uz2Tr/BRGAQF/ZotgAUN60VR4GA9Zla48cvEH0wcKJuQXaMCpngrSRO3UHMIIhsgJTaY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652767405398605.9238103452877; Mon, 16 May 2022 23:03:25 -0700 (PDT) Received: from localhost ([::1]:53606 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqqIm-0002mT-6S for importer@patchew.org; Tue, 17 May 2022 02:03:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqq4s-0000UC-Mi for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:04 -0400 Received: from mail-pf1-x429.google.com ([2607:f8b0:4864:20::429]:35615) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nqq4q-0007os-TW for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:02 -0400 Received: by mail-pf1-x429.google.com with SMTP id c14so15987144pfn.2 for ; Mon, 16 May 2022 22:48:58 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=xAd7na+2KxBtPMtY2na7BNVtRH2LfOqAnHHLmai2Ves=; b=iEnGoxrWBBUVFA9N55qcwl85lWxtXGeREh50OFGNEVw7WPltlQ+LpwjgR9LnmLZQ1i bShKbiPcLXXhOgQXEkw6Hq55SXAYlY9w+qT8yiHfYD817ZBceWGXIy6O6g/x+2XZ+4FZ rga9IUYiuQ6GscMoVoKxHkpllYKtwU6s+0KKAyHsOHTxknoVvhx9QBONLoArAo408APM UsWjJhrTZT3bcY+jozvLV3fYculJC7B+qoQ1pAoGxP2KvMzRGuX2yC0PFFEOAoWBKiqg aD13Fec+bspkiCLkdf6kE0yN48iYKCzJFpm7tB4X800lgJpo0VqJBDZsacr9JIsEtcC9 acLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=xAd7na+2KxBtPMtY2na7BNVtRH2LfOqAnHHLmai2Ves=; b=VZfwVFg16Xg4BdQxhL1kGbPC0mT+tpu56r/3w0ADVvlLy3utaggxIU9UE02pM4Fg3k kfSJcV1VnaVMgk72/mAsiscNfr366UPGAgzqUWUfrcu0VcPs//L/Tlb5jyFCTuU9yH4e m93Ff09rQgEQfPu+gLsulD5ArloGPI4n1NGOJ4vE7sS8u7zS/h0K1TuODDiPMBlGXRAO 9J+fT+w75+t3pGU9Mgjwt1Uw3hV6Vc1/OHL51o7dZ06AwD14zQZOvyo6SplC7yDCKsqJ mhinPt92pGGa1pVHalUlxIJpVpwozKEomvFfFcIATWFFbXRbizJ+gjHbswAU5Hcsud6V 3tsA== X-Gm-Message-State: AOAM530tJ4rSbyR9iHjCM4h/gFWNRQqMhcLXHGOShMdLzIxUOtBq+VSw UfkRTMNDNhpaMcPiS4WvH8+lFJI0D15kYw== X-Google-Smtp-Source: ABdhPJw6kiW8Qj9pGbcxDn/gmwHcUuBLndyTKfWcdxT1g/oe07NyruTJZ1PZ1AAeyb3r7RQ3HV4i/g== X-Received: by 2002:a63:1c4e:0:b0:3f2:6da7:5d90 with SMTP id c14-20020a631c4e000000b003f26da75d90mr7562874pgm.429.1652766532943; Mon, 16 May 2022 22:48:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 1/7] target/arm: Enable FEAT_HCX for -cpu max Date: Mon, 16 May 2022 22:48:44 -0700 Message-Id: <20220517054850.177016-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652767407391100001 Content-Type: text/plain; charset="utf-8" This feature adds a new register, HCRX_EL2, which controls many of the newer AArch64 features. So far the register is effectively RES0, because none of the new features are done. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 20 ++++++++++++++++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18ca61e8e2..b35b117fe7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -362,6 +362,7 @@ typedef struct CPUArchState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ + uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ uint64_t scr_el3; /* Secure configuration register. */ union { /* Fault status registers. */ struct { @@ -1543,6 +1544,19 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 +#define HCRX_ENAS0 (1ULL << 0) +#define HCRX_ENALS (1ULL << 1) +#define HCRX_ENASR (1ULL << 2) +#define HCRX_FNXS (1ULL << 3) +#define HCRX_FGTNXS (1ULL << 4) +#define HCRX_SMPME (1ULL << 5) +#define HCRX_TALLINT (1ULL << 6) +#define HCRX_VINMI (1ULL << 7) +#define HCRX_VFNMI (1ULL << 8) +#define HCRX_CMOW (1ULL << 9) +#define HCRX_MCE2 (1ULL << 10) +#define HCRX_MSCEN (1ULL << 11) + #define HPFAR_NS (1ULL << 63) =20 #define SCR_NS (1U << 0) @@ -2310,6 +2324,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *en= v) * Not included here is HCR_RW. */ uint64_t arm_hcr_el2_eff(CPUARMState *env); +uint64_t arm_hcrx_el2_eff(CPUARMState *env); =20 /* Return true if the specified exception level is running in AArch64 stat= e. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) @@ -3931,6 +3946,11 @@ static inline bool isar_feature_aa64_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; +} + static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 04427e073f..4ab1dcf2ef 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -910,6 +910,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; diff --git a/target/arm/helper.c b/target/arm/helper.c index 432bd81919..93ab552346 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5278,6 +5278,52 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + /* No features adding bits to HCRX are implemented. */ + + /* Clear RES0 bits. */ + env->cp15.hcrx_el2 =3D value & valid_mask; +} + +static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_HXEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo hcrx_el2_reginfo =3D { + .name =3D "HCRX_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 2, + .access =3D PL2_RW, .writefn =3D hcrx_write, .accessfn =3D access_hxen, + .fieldoffset =3D offsetof(CPUARMState, cp15.hcrx_el2), +}; + +/* Return the effective value of HCRX_EL2. */ +uint64_t arm_hcrx_el2_eff(CPUARMState *env) +{ + /* + * The bits in this register behave as 0 for all purposes other than + * direct reads of the register if: + * - EL2 is not enabled in the current security state, + * - SCR_EL3.HXEn is 0. + */ + if (!arm_is_el2_enabled(env) + || (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_HXEN))) { + return 0; + } + return env->cp15.hcrx_el2; +} + static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -8384,6 +8430,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, zcr_reginfo); } =20 + if (cpu_isar_feature(aa64_hcx, cpu)) { + define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); + } + #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); --=20 2.34.1 From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=6iXgfu3U31v7MEJyJm8Rq3CUs2tIrolz0tZM3iDqk8o=; b=LSvgDqQ//M1R8gx+SjYvFytOeeOAGlHcvzhTJgmr4zlliZ1OX7r8jYFDTWDqiAcja/ UwJVcIwDHywje5l+tB0YWb1+vdJQ9YdJOKle5g3XaYBiCarVTSO+cZ/9qm4aw4+wlPH5 Jt8Mf644qf7AMQw74m0QfFeVdRQ3FOBBHQz8y1c9TX8+aJZ3v1eyGoflkzLILhsjfV9/ SHWb8smbzs7LX6pZiaGBejhCk29xszWFhEGLbtdiixknll/2xS+TfAsVY94HRwM+jZC3 zXo6W1SLF96k5I0NNZjl1raSEClVaQyXfcGdO8zwXxb0LrNlpzFZJOrR3yXSmj7i7318 Fh1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6iXgfu3U31v7MEJyJm8Rq3CUs2tIrolz0tZM3iDqk8o=; b=j7A0ivC6tgst9CNuu12e5P/s7Xp1rEA8v4IWOyy/LqCD4S4x+02e2Y0NZ6rmkaAPxY 6uvg7DyTfA4iogjZbhfP/ODvj3zKVQZaXP77n72lFOjmhiAVj+P1k9BGucFaU/tuEgnr SpuailY0y6I6ol60gIjbau493X7fT9ZJLV73znvgNDZcnuGNxP/94IOqzTDLQVEk3bOs MQWH4kASfl8Xq8zOlMXS2SA5eevvGJV0FQbjKRB9YtYfGmmaQG0DxoOYQn5OalH0q/mK xKcPIn9KGS7x8XcFwjQCTbqsT12O7+fmS6pLP6c+NctyOer+o2vUFptyNIvd5oU+LBA/ ob5Q== X-Gm-Message-State: AOAM530o5hpOODx9iuvWHIjH6PA3N4bBsO8afVQ9lQhEgr/9fTfgUCne wcCz0iXRECDhHL5UmuQqxBumbSch2Jfo7Q== X-Google-Smtp-Source: ABdhPJztCQrC0WTubfP/KYUSvyB0FlTBPtJsQcSQtRJozJTyWdapwTNm2s/ciimAu5oDD5j6IvWSdA== X-Received: by 2002:a17:903:1c9:b0:161:89e8:229 with SMTP id e9-20020a17090301c900b0016189e80229mr6383982plh.106.1652766533651; Mon, 16 May 2022 22:48:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v2 2/7] target/arm: Use FIELD definitions for CPACR, CPTR_ELx Date: Mon, 16 May 2022 22:48:45 -0700 Message-Id: <20220517054850.177016-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652767338785100001 Content-Type: text/plain; charset="utf-8" We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 44 +++++++++++++++++++++++++++++++----- hw/arm/boot.c | 2 +- target/arm/cpu.c | 11 ++++++--- target/arm/helper.c | 54 ++++++++++++++++++++++----------------------- 4 files changed, 75 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b35b117fe7..d23b7b3ad4 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1259,11 +1259,45 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 -#define CPTR_TCPAC (1U << 31) -#define CPTR_TTA (1U << 20) -#define CPTR_TFP (1U << 10) -#define CPTR_TZ (1U << 8) /* CPTR_EL2 */ -#define CPTR_EZ (1U << 8) /* CPTR_EL3 */ +/* Bit definitions for CPACR (AArch32 only) */ +FIELD(CPACR, CP10, 20, 2) +FIELD(CPACR, CP11, 22, 2) +FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ +FIELD(CPACR, D32DIS, 30, 1) /* up to v7; RAZ in v8 */ +FIELD(CPACR, ASEDIS, 31, 1) + +/* Bit definitions for CPACR_EL1 (AArch64 only) */ +FIELD(CPACR_EL1, ZEN, 16, 2) +FIELD(CPACR_EL1, FPEN, 20, 2) +FIELD(CPACR_EL1, SMEN, 24, 2) +FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ + +/* Bit definitions for HCPTR (AArch32 only) */ +FIELD(HCPTR, TCP10, 10, 1) +FIELD(HCPTR, TCP11, 11, 1) +FIELD(HCPTR, TASE, 15, 1) +FIELD(HCPTR, TTA, 20, 1) +FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ +FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ + +/* Bit definitions for CPTR_EL2 (AArch64 only) */ +FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ +FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ +FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ +FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ +FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ +FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ +FIELD(CPTR_EL2, TTA, 28, 1) +FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ +FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ + +/* Bit definitions for CPTR_EL3 (AArch64 only) */ +FIELD(CPTR_EL3, EZ, 8, 1) +FIELD(CPTR_EL3, TFP, 10, 1) +FIELD(CPTR_EL3, ESM, 12, 1) +FIELD(CPTR_EL3, TTA, 20, 1) +FIELD(CPTR_EL3, TAM, 30, 1) +FIELD(CPTR_EL3, TCPAC, 31, 1) =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a47f38dfc9..a8de33fd64 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -761,7 +761,7 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |=3D SCR_ATA; } if (cpu_isar_feature(aa64_sve, cpu)) { - env->cp15.cptr_el[3] |=3D CPTR_EZ; + env->cp15.cptr_el[3] |=3D R_CPTR_EL3_EZ_MASK; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 029f644768..d2bd74c2ed 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -201,9 +201,11 @@ static void arm_cpu_reset(DeviceState *dev) /* Trap on btype=3D3 for PACIxSP. */ env->cp15.sctlr_el[1] |=3D SCTLR_BT0; /* and to the FP/Neon instructions */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, FPEN, 3); /* and to the SVE instructions */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { env->vfp.zcr_el[1] =3D @@ -252,7 +254,10 @@ static void arm_cpu_reset(DeviceState *dev) } else { #if defined(CONFIG_USER_ONLY) /* Userspace expects access to cp10 and cp11 for FP/Neon */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR, CP10, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR, CP11, 3); #endif } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 93ab552346..5fd64b742a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -767,11 +767,14 @@ static void cpacr_write(CPUARMState *env, const ARMCP= RegInfo *ri, */ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); + mask |=3D R_CPACR_ASEDIS_MASK | + R_CPACR_D32DIS_MASK | + R_CPACR_CP11_MASK | + R_CPACR_CP10_MASK; =20 if (!arm_feature(env, ARM_FEATURE_NEON)) { /* ASEDIS [31] bit is RAO/WI */ - value |=3D (1 << 31); + value |=3D R_CPACR_ASEDIS_MASK; } =20 /* VFPv3 and upwards with NEON implement 32 double precision @@ -779,7 +782,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ - value |=3D (1 << 30); + value |=3D R_CPACR_D32DIS_MASK; } } value &=3D mask; @@ -791,8 +794,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); - value |=3D env->cp15.cpacr_el1 & (0xf << 20); + mask =3D R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; + value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); } =20 env->cp15.cpacr_el1 =3D value; @@ -808,7 +811,7 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMC= PRegInfo *ri) =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); + value =3D ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); } return value; } @@ -828,11 +831,11 @@ static CPAccessResult cpacr_access(CPUARMState *env, = const ARMCPRegInfo *ri, if (arm_feature(env, ARM_FEATURE_V8)) { /* Check if CPACR accesses are to be trapped to EL2 */ if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && - (env->cp15.cptr_el[2] & CPTR_TCPAC)) { + FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { return CP_ACCESS_TRAP_EL2; /* Check if CPACR accesses are to be trapped to EL3 */ } else if (arm_current_el(env) < 3 && - (env->cp15.cptr_el[3] & CPTR_TCPAC)) { + FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { return CP_ACCESS_TRAP_EL3; } } @@ -844,7 +847,8 @@ static CPAccessResult cptr_access(CPUARMState *env, con= st ARMCPRegInfo *ri, bool isread) { /* Check if CPTR accesses are set to trap to EL3 */ - if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { + if (arm_current_el(env) =3D=3D 2 && + FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { return CP_ACCESS_TRAP_EL3; } =20 @@ -5333,8 +5337,8 @@ static void cptr_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0x3 << 10); - value |=3D env->cp15.cptr_el[2] & (0x3 << 10); + uint64_t mask =3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; + value =3D (value & ~mask) | (env->cp15.cptr_el[2] & mask); } env->cp15.cptr_el[2] =3D value; } @@ -5349,7 +5353,7 @@ static uint64_t cptr_el2_read(CPUARMState *env, const= ARMCPRegInfo *ri) =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value |=3D 0x3 << 10; + value |=3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; } return value; } @@ -6144,8 +6148,7 @@ int sve_exception_el(CPUARMState *env, int el) uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); =20 if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - /* Check CPACR.ZEN. */ - switch (extract32(env->cp15.cpacr_el1, 16, 2)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { case 1: if (el !=3D 0) { break; @@ -6158,7 +6161,7 @@ int sve_exception_el(CPUARMState *env, int el) } =20 /* Check CPACR.FPEN. */ - switch (extract32(env->cp15.cpacr_el1, 20, 2)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { case 1: if (el !=3D 0) { break; @@ -6175,8 +6178,7 @@ int sve_exception_el(CPUARMState *env, int el) */ if (el <=3D 2) { if (hcr_el2 & HCR_E2H) { - /* Check CPTR_EL2.ZEN. */ - switch (extract32(env->cp15.cptr_el[2], 16, 2)) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: if (el !=3D 0 || !(hcr_el2 & HCR_TGE)) { break; @@ -6187,8 +6189,7 @@ int sve_exception_el(CPUARMState *env, int el) return 2; } =20 - /* Check CPTR_EL2.FPEN. */ - switch (extract32(env->cp15.cptr_el[2], 20, 2)) { + switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { case 1: if (el =3D=3D 2 || !(hcr_el2 & HCR_TGE)) { break; @@ -6199,10 +6200,10 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } } else if (arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (env->cp15.cptr_el[2] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { return 0; } } @@ -6210,7 +6211,7 @@ int sve_exception_el(CPUARMState *env, int el) =20 /* CPTR_EL3. Since EZ is negative we must check for EL3. */ if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { return 3; } #endif @@ -13266,7 +13267,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) * This register is ignored if E2H+TGE are both set. */ if ((hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { - int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + int fpen =3D FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); =20 switch (fpen) { case 0: @@ -13312,8 +13313,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) */ if (cur_el <=3D 2) { if (hcr_el2 & HCR_E2H) { - /* Check CPTR_EL2.FPEN. */ - switch (extract32(env->cp15.cptr_el[2], 20, 2)) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { case 1: if (cur_el !=3D 0 || !(hcr_el2 & HCR_TGE)) { break; @@ -13324,14 +13324,14 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 2; } } else if (arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { return 2; } } } =20 /* CPTR_EL3 : present in v8 */ - if (env->cp15.cptr_el[3] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { /* Trap all FP ops to EL3 */ return 3; } --=20 2.34.1 From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652767703; cv=none; d=zohomail.com; s=zohoarc; b=Ryfa2TKMAOu1SyD7anXUMloRnJUnIHfnDhzON8KB02On76C3IyQEkiUCA0MMydQC/+zShh2lcBCQAeThIauF8QQ8sutrwOC0Dm6a9rZm9GlYXbG3tFvD71ePRynmnlJyheaYe9L50gtyxi5b5lT35qlwIM14HTQkmsdZDPVjK6s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652767703; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=9CQLR9+ZabdVBvj8yT9hoESiXzPxfvDoRGYhKlSAaF0=; b=g9NVIBNxBOs7h+rGvaCsnl91543TfeYp8BEcLEkBz2eLpPSlDIX3dLvPB15gdWnGl105TivXze/51l98ACd88WNYTuHu/QxLubuUB2o6svPxlbUVhC0bUA1jS5hz7R8SXb54VWxf7IX/07kwJiKr/mOkAzOi5067gEmCBLt9nEQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165276770335210.260752234617598; Mon, 16 May 2022 23:08:23 -0700 (PDT) Received: from localhost ([::1]:59758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqqNa-0007eH-5X for importer@patchew.org; Tue, 17 May 2022 02:08:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqq4o-0000Tl-P2 for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:02 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:38510) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nqq4l-0007ni-N9 for qemu-devel@nongnu.org; Tue, 17 May 2022 01:48:58 -0400 Received: by mail-pj1-x1032.google.com with SMTP id o13-20020a17090a9f8d00b001df3fc52ea7so1419833pjp.3 for ; Mon, 16 May 2022 22:48:55 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9CQLR9+ZabdVBvj8yT9hoESiXzPxfvDoRGYhKlSAaF0=; b=Ig4e2ZOlV6l6B/eekA8p2Y3WC7jOcp2Oi7+b0x8DuFvXpkFdWnbyciWeXw9ciEuL6W /XRl5XYEEaf36eqOY4Esw8pYTXuPcwzmi/wcv061oLLZhbHwFR+YCHA8JUJV/8koZdqv G0hqF4bKmEoGUC6hxGFiZOd3qJMxv8yXDDQTw2YWipv0Sw//+EwBoabhQm5R6QjPrLQL Yy+LLZGugDk+vDyCu0dCTSdeYLRJP0s9CwI4oL77bbp+uHhgkvrg/JW0zq9xnUFz19Tn l6lK+qwS/E3WXFWqBTtc22J1Z/0i8BWXVywCFSrdQtog3dpsFeERw0mN6j8F2Ox60wRF rT5A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9CQLR9+ZabdVBvj8yT9hoESiXzPxfvDoRGYhKlSAaF0=; b=ruUI+I3/M4ckRyLf2f765KQfm2sCM5IE6sJM4s77hKD2AHUPXmR/DDmUJW3MmzB/WW GBctxYwvg/4guOuaKxyb8ek43RODxgoFctbUlwIBh6+Jlzo0Z8ScW4+zs3iU6EOFVT9t R9gJjfKoc/wVHcl8cLveGVrH4i4yo2vxEGrumkZtI+Z6mY9qmcQfwGtUb1BU1VeywKVB ahYFnOl9pT+S+O5i2t4Qm9R8M7KE22qEvVb3tBgici1icuzIMPnnbDeeSP8/2sqfWXnY pu3mB3J5GCrT41SdwNV5GvQB1lHM/RuXlbVlr3QxzAA13AcVAIHQdmDs7wsI0uA7h0Ut yBZA== X-Gm-Message-State: AOAM532hFBGNf/wiujBBry0KLdpaMMdM6UaQpB6Wq4n57lUD7TsCt7+F AJOFoBx0eMpamwX0ch29JyLYP+IV+rHSUA== X-Google-Smtp-Source: ABdhPJwkYRZgXpazCoH5TpezoEz662E1jUw8EI8D5xNsV9+/EAlGtt9eA0rR1mYwOoCAdRvTXr4bpA== X-Received: by 2002:a17:902:700b:b0:15f:a51a:cdeb with SMTP id y11-20020a170902700b00b0015fa51acdebmr20570976plk.137.1652766534418; Mon, 16 May 2022 22:48:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 3/7] target/arm: Do not use aarch64_sve_zcr_get_valid_len in reset Date: Mon, 16 May 2022 22:48:46 -0700 Message-Id: <20220517054850.177016-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652767703667100001 Content-Type: text/plain; charset="utf-8" We don't need to constrain the value set in zcr_el[1], because it will be done by sve_zcr_len_for_el. Signed-off-by: Richard Henderson --- target/arm/cpu.c | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index d2bd74c2ed..0621944167 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -208,8 +208,7 @@ static void arm_cpu_reset(DeviceState *dev) CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { - env->vfp.zcr_el[1] =3D - aarch64_sve_zcr_get_valid_len(cpu, cpu->sve_default_vq - 1= ); + env->vfp.zcr_el[1] =3D cpu->sve_default_vq - 1; } /* * Enable 48-bit address space (TODO: take reserved_va into accoun= t). --=20 2.34.1 From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652766853; cv=none; d=zohomail.com; s=zohoarc; b=g2Gusqf1HL0jhYup/I8BPqCezrWcf8k3VKGU0SPu9mwl9EGdJDpocGyznYqXAND3mQ0rwhSsKdXnQ7OAzg6CD8nu1Ik9SU/DJQeUpll6tI77vwH6ChuCK92Ud5IPgQYk8y8Q3Y29d6PpseHoIg2g9+G7H4y99iZeuSX+HI/ckDg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652766853; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lmHQQPYKlDu3aWdQHOeaVIIUIVTyse+PwW1XBQtfA78=; b=It2Ps+DTEBNOV67ZBjlCYLJXmrulJ+pfyZDNs5EtcMnuIXIqnm+sYBvTsQb1/YwJjuLsMvxDSE/zMmYbYfOx0Q8HhjaAXQ04B7tOGA9lCIvnE7mUQe710JcnfWP1L9LK6MgOeldh35AW0uH0i6y7LIbe3LHr2atLJU/Fo8vbINA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652766853784964.8314182652999; Mon, 16 May 2022 22:54:13 -0700 (PDT) Received: from localhost ([::1]:42602 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqq9s-0003UU-9g for importer@patchew.org; Tue, 17 May 2022 01:54:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49644) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqq4r-0000U4-7c for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:03 -0400 Received: from mail-pl1-x62b.google.com ([2607:f8b0:4864:20::62b]:33625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nqq4m-0007nz-EA for qemu-devel@nongnu.org; Tue, 17 May 2022 01:48:58 -0400 Received: by mail-pl1-x62b.google.com with SMTP id d17so16461532plg.0 for ; Mon, 16 May 2022 22:48:56 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lmHQQPYKlDu3aWdQHOeaVIIUIVTyse+PwW1XBQtfA78=; b=cGV7ETBX0EQw4hCrNIxB8c5H7+FhLuLVgD/Q+KMxCmgy+VOoCo0ax9d8/lCyU0+WmS zy1pa5WOJCdjf+LvCpitdP6mNzHY3ayIuw50W7uuSeNvRz0wh7hvr5N8X89+yQklgRwl K2AL3N2dW+3mNo4HooDBnnhh19n/HEmm6jZ8eKArFcihq6euwLgRrAaDgtEOLGTgv+Hc rXZ4xK8Ba5Uo3nuVrshreXg9T9+SGtXkU+JjM2XJ/08X2Bh/tzf64RVVWbPeIJHyJjpr jxtWBnnMYf/HFgVcQKYdHCt+3Mj+Yc1P+n2J1BSvUSz1mDXrJQFPoyH4rzLuHlU1YHxz BbDg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lmHQQPYKlDu3aWdQHOeaVIIUIVTyse+PwW1XBQtfA78=; b=08+j1WGl8s9TwpCkgtU13hM2jOHVqPcxBjl7p0zmmlFAh9QIkxHceLtKvrjhIgyYHt l79JUjweLOYt6eaGC0TSuZUHDGwnrsSiLC1HI34qimU7snCqaJETf59n1x+7af+0Bkkr fxULCzORHt4yfraN+dkTWiiB1cJY6YDaBsjb+DFiQlSr80KCMeZ29DiB3yncdQOMKHsm FeIM0zmju9TAVkJdBiLhkWKgbCGDO/jGAyaHham8qvL3tUn1R6b+XxInyD2tqbWKnNd/ rk0Rq/tK86khV2fcIShlBtmVdZL3I05ffF+pWC3sbndyW+5ksxN+w9b6fkip4wHutRPF 3f1A== X-Gm-Message-State: AOAM533NbD5FvFT+f2p7tKo3GOeG3w5910dJZmcqpkLjt5myeENX2Sba r/q1hCLVZc3xAX8aPUX2K0A5+6LVA03N1g== X-Google-Smtp-Source: ABdhPJx7S8MkwcTYvDle8pRk/J6KKf59X/nvTX9t5cyjpkwYt5oNhWLeug1Ukk75ba2KI/kkXacQSw== X-Received: by 2002:a17:902:f684:b0:161:8b4d:adf5 with SMTP id l4-20020a170902f68400b001618b4dadf5mr6159456plg.112.1652766535108; Mon, 16 May 2022 22:48:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 4/7] target/arm: Merge aarch64_sve_zcr_get_valid_len into caller Date: Mon, 16 May 2022 22:48:47 -0700 Message-Id: <20220517054850.177016-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62b; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652766855063100001 Content-Type: text/plain; charset="utf-8" This function is used only once, and will need modification for Streaming SVE mode. Signed-off-by: Richard Henderson --- target/arm/internals.h | 11 ----------- target/arm/helper.c | 30 +++++++++++------------------- 2 files changed, 11 insertions(+), 30 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 6ca0e95746..36ff843cef 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -189,17 +189,6 @@ void arm_translate_init(void); void arm_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); #endif /* CONFIG_TCG */ =20 -/** - * aarch64_sve_zcr_get_valid_len: - * @cpu: cpu context - * @start_len: maximum len to consider - * - * Return the maximum supported sve vector length <=3D @start_len. - * Note that both @start_len and the return value are in units - * of ZCR_ELx.LEN, so the vector bit length is (x + 1) * 128. - */ -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len); - enum arm_fprounding { FPROUNDING_TIEEVEN, FPROUNDING_POSINF, diff --git a/target/arm/helper.c b/target/arm/helper.c index 5fd64b742a..0308920357 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6218,40 +6218,32 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } =20 -uint32_t aarch64_sve_zcr_get_valid_len(ARMCPU *cpu, uint32_t start_len) -{ - uint32_t end_len; - - start_len =3D MIN(start_len, ARM_MAX_VQ - 1); - end_len =3D start_len; - - if (!test_bit(start_len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, start_len); - assert(end_len < start_len); - } - return end_len; -} - /* * Given that SVE is enabled, return the vector length for EL. */ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); - uint32_t zcr_len =3D cpu->sve_max_vq - 1; + uint32_t len =3D cpu->sve_max_vq - 1; + uint32_t end_len; =20 if (el <=3D 1 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[1]); + len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[1]); } if (el <=3D 2 && arm_feature(env, ARM_FEATURE_EL2)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[2]); + len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[2]); } if (arm_feature(env, ARM_FEATURE_EL3)) { - zcr_len =3D MIN(zcr_len, 0xf & (uint32_t)env->vfp.zcr_el[3]); + len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - return aarch64_sve_zcr_get_valid_len(cpu, zcr_len); + end_len =3D len; + if (!test_bit(len, cpu->sve_vq_map)) { + end_len =3D find_last_bit(cpu->sve_vq_map, len); + assert(end_len < len); + } + return end_len; } =20 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.34.1 From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652766978; cv=none; d=zohomail.com; s=zohoarc; b=Wjv+vZeu5Y0V6GcA6XLtIjwAxEkWXHvH+Q+Fq4VxEKuoIdcE4zBFFK9fT2y+lT5xL2z8EtWtQ0dn1dBw614OPrYu67nunzPpOXtkUxx1wv8djVa2Cn4LrEPSKdV5S7ZpTuRVzQ18Z5Aw2TPDk05bDH1VzG+mRQhhbM/1oLfJu9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652766978; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LYTg1A3lKU1yuIoLWQgssj5UJqZjf3gnfu+aKeLn8kc=; b=ixJHubGGeESVaIZaassvtvM10hggRuURm1/v+1OCVKGA7eV6DZ3JxgJhUXlpW2on6hAbIcFKo8/avSVi9O7XWNIlsX3lEWgGkKxFsWZFusTMrgDYpJeLPKqjG9uVOmxDdGkq4IZ7RUDyAHq1Jg6G+2Y7dbPDTq5uUKwYrGjThvE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652766978635573.4049320133603; Mon, 16 May 2022 22:56:18 -0700 (PDT) Received: from localhost ([::1]:44974 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqqBp-00054R-0u for importer@patchew.org; Tue, 17 May 2022 01:56:16 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49648) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqq4r-0000U6-8A for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:04 -0400 Received: from mail-pg1-x536.google.com ([2607:f8b0:4864:20::536]:44634) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nqq4n-0007oE-Bj for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:00 -0400 Received: by mail-pg1-x536.google.com with SMTP id v10so16027221pgl.11 for ; Mon, 16 May 2022 22:48:56 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LYTg1A3lKU1yuIoLWQgssj5UJqZjf3gnfu+aKeLn8kc=; b=FDm2qPOKrXwb0geJhZVzkAuCZmVV50cIMew58BCAsiLtycoNbtLWRYIPuiHzCL8iXK Mtgb9cl4+ukILQjuqpvgfD32RFwSOaVpG501AdpFcPR056bOGAQ+IdEGoq9RtgtLM3Wj c6uwA60D/KMeq0OGHVqeb//KCentAF/XSv1YmAt5Dto2/d5Pu3nG/WX+PFOV+2Wnz7MR 1shprgSoHbqJ8eoQ5uZ5widIDhHzm/duPef9qXE+Njwf5D7dul2O4TP/SpYclH6QpWvs klYVdCY1W5U4/gPtnQe+ioStskMzAIePKvRg6nTtq8HUDHuhPOyn3imr6+07iVjbTUzu RDTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LYTg1A3lKU1yuIoLWQgssj5UJqZjf3gnfu+aKeLn8kc=; b=cb8eWrsnlPvvBszo0onCUSb9YfzxpyAqOwQ7fwQXj77uY5R0ofUljMSd6Jk5Tb+4u+ isky5eIfc/oM4Sq6zZK/QPtIh+L8dvqEXKQA/IOA3N+wlTWtCJqma+JSXroHQ1kyM90Z 5EoKjnpcaTSnzLUXWgnWDkD4nRrU0nn+5xEFlW8GSlmq+9cvXXbgv4ya1XF+xoGnnVsr cbyNIoUotRNLb89djs4txWECTuCE5mo5twWVWwFT7kp77HGEjdynXToYcyr/VhaohTLB aLh27cX37ZfQBOM4NVXPWoABaiPhpLx1II6M7qq/0dFq3bH9ROidaUbXYljB7Jyhc+m4 ZzDA== X-Gm-Message-State: AOAM533wTl+Ion/CuqKzQM5cxm5G8fEYyD57W40SU7ZeENLGlMsmZZCO 0UnYs71pyy8auSX4Uouwk58BMwYgbdvpjQ== X-Google-Smtp-Source: ABdhPJxyMQ+Z4GAyKCEVZeM844hltFuI+/nU5Rp+MpafX1fcXAkt6iGWRUgAJqFiQnaQriaH9mzJ5g== X-Received: by 2002:a63:fa4b:0:b0:3db:b85:c080 with SMTP id g11-20020a63fa4b000000b003db0b85c080mr18236708pgk.465.1652766535938; Mon, 16 May 2022 22:48:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 5/7] target/arm: Use uint32_t instead of bitmap for sve vq's Date: Mon, 16 May 2022 22:48:48 -0700 Message-Id: <20220517054850.177016-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::536; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652766979828100001 Content-Type: text/plain; charset="utf-8" The bitmap need only hold 15 bits; bitmap is over-complicated. We can simplify operations quite a bit with plain logical ops. The introduction of SVE_VQ_POW2_MAP eliminates the need for looping in order to search for powers of two. Simply perform the logical ops and use count leading or trailing zeros as required to find the result. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 6 +-- target/arm/internals.h | 5 ++ target/arm/kvm_arm.h | 7 ++- target/arm/cpu64.c | 117 ++++++++++++++++++++--------------------- target/arm/helper.c | 9 +--- target/arm/kvm64.c | 36 +++---------- 6 files changed, 75 insertions(+), 105 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d23b7b3ad4..db7e51bf67 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1039,9 +1039,9 @@ struct ArchCPU { * Bits set in sve_vq_supported represent valid vector lengths for * the CPU type. */ - DECLARE_BITMAP(sve_vq_map, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_init, ARM_MAX_VQ); - DECLARE_BITMAP(sve_vq_supported, ARM_MAX_VQ); + uint32_t sve_vq_map; + uint32_t sve_vq_init; + uint32_t sve_vq_supported; =20 /* Generic timer counter frequency, in Hz */ uint64_t gt_cntfrq_hz; diff --git a/target/arm/internals.h b/target/arm/internals.h index 36ff843cef..4165d49570 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1312,4 +1312,9 @@ void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu= ); =20 void aa32_max_features(ARMCPU *cpu); =20 +/* Powers of 2 for sve_vq_map et al. */ +#define SVE_VQ_POW2_MAP \ + ((1 << (1 - 1)) | (1 << (2 - 1)) | \ + (1 << (4 - 1)) | (1 << (8 - 1)) | (1 << (16 - 1))) + #endif diff --git a/target/arm/kvm_arm.h b/target/arm/kvm_arm.h index b7f78b5215..99017b635c 100644 --- a/target/arm/kvm_arm.h +++ b/target/arm/kvm_arm.h @@ -239,13 +239,12 @@ bool kvm_arm_get_host_cpu_features(ARMHostCPUFeatures= *ahcf); /** * kvm_arm_sve_get_vls: * @cs: CPUState - * @map: bitmap to fill in * * Get all the SVE vector lengths supported by the KVM host, setting * the bits corresponding to their length in quadwords minus one - * (vq - 1) in @map up to ARM_MAX_VQ. + * (vq - 1) up to ARM_MAX_VQ. Return the resulting map. */ -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map); +uint32_t kvm_arm_sve_get_vls(CPUState *cs); =20 /** * kvm_arm_set_cpu_features_from_host: @@ -439,7 +438,7 @@ static inline void kvm_arm_steal_time_finalize(ARMCPU *= cpu, Error **errp) g_assert_not_reached(); } =20 -static inline void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +static inline uint32_t kvm_arm_sve_get_vls(CPUState *cs) { g_assert_not_reached(); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 4ab1dcf2ef..a020933975 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -341,8 +341,11 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * any of the above. Finally, if SVE is not disabled, then at least o= ne * vector length must be enabled. */ - DECLARE_BITMAP(tmp, ARM_MAX_VQ); - uint32_t vq, max_vq =3D 0; + uint32_t vq_map =3D cpu->sve_vq_map; + uint32_t vq_init =3D cpu->sve_vq_init; + uint32_t vq_supported; + uint32_t vq_mask =3D 0; + uint32_t tmp, vq, max_vq =3D 0; =20 /* * CPU models specify a set of supported vector lengths which are @@ -350,10 +353,16 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * in the supported bitmap results in an error. When KVM is enabled we * fetch the supported bitmap from the host. */ - if (kvm_enabled() && kvm_arm_sve_supported()) { - kvm_arm_sve_get_vls(CPU(cpu), cpu->sve_vq_supported); - } else if (kvm_enabled()) { - assert(!cpu_isar_feature(aa64_sve, cpu)); + if (kvm_enabled()) { + if (kvm_arm_sve_supported()) { + cpu->sve_vq_supported =3D kvm_arm_sve_get_vls(CPU(cpu)); + vq_supported =3D cpu->sve_vq_supported; + } else { + assert(!cpu_isar_feature(aa64_sve, cpu)); + vq_supported =3D 0; + } + } else { + vq_supported =3D cpu->sve_vq_supported; } =20 /* @@ -361,8 +370,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * From the properties, sve_vq_map implies sve_vq_init. * Check first for any sve enabled. */ - if (!bitmap_empty(cpu->sve_vq_map, ARM_MAX_VQ)) { - max_vq =3D find_last_bit(cpu->sve_vq_map, ARM_MAX_VQ) + 1; + if (vq_map !=3D 0) { + max_vq =3D 32 - clz32(vq_map); + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); =20 if (cpu->sve_max_vq && max_vq > cpu->sve_max_vq) { error_setg(errp, "cannot enable sve%d", max_vq * 128); @@ -378,15 +388,10 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * For KVM we have to automatically enable all supported uniti= alized * lengths, even when the smaller lengths are not all powers-o= f-two. */ - bitmap_andnot(tmp, cpu->sve_vq_supported, cpu->sve_vq_init, ma= x_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |=3D vq_supported & ~vq_init & vq_mask; } else { /* Propagate enabled bits down through required powers-of-two.= */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_init)) { - set_bit(vq - 1, cpu->sve_vq_map); - } - } + vq_map |=3D SVE_VQ_POW2_MAP & ~vq_init & vq_mask; } } else if (cpu->sve_max_vq =3D=3D 0) { /* @@ -399,25 +404,18 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) =20 if (kvm_enabled()) { /* Disabling a supported length disables all larger lengths. */ - for (vq =3D 1; vq <=3D ARM_MAX_VQ; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_init) && - test_bit(vq - 1, cpu->sve_vq_supported)) { - break; - } - } + tmp =3D vq_init & vq_supported; } else { /* Disabling a power-of-two disables all larger lengths. */ - for (vq =3D 1; vq <=3D ARM_MAX_VQ; vq <<=3D 1) { - if (test_bit(vq - 1, cpu->sve_vq_init)) { - break; - } - } + tmp =3D vq_init & SVE_VQ_POW2_MAP; } + vq =3D ctz32(tmp) + 1; =20 max_vq =3D vq <=3D ARM_MAX_VQ ? vq - 1 : ARM_MAX_VQ; - bitmap_andnot(cpu->sve_vq_map, cpu->sve_vq_supported, - cpu->sve_vq_init, max_vq); - if (max_vq =3D=3D 0 || bitmap_empty(cpu->sve_vq_map, max_vq)) { + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); + vq_map =3D vq_supported & ~vq_init & vq_mask; + + if (max_vq =3D=3D 0 || vq_map =3D=3D 0) { error_setg(errp, "cannot disable sve%d", vq * 128); error_append_hint(errp, "Disabling sve%d results in all " "vector lengths being disabled.\n", @@ -427,7 +425,8 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } =20 - max_vq =3D find_last_bit(cpu->sve_vq_map, max_vq) + 1; + max_vq =3D 32 - clz32(vq_map); + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); } =20 /* @@ -437,9 +436,9 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) */ if (cpu->sve_max_vq !=3D 0) { max_vq =3D cpu->sve_max_vq; + vq_mask =3D MAKE_64BIT_MASK(0, max_vq); =20 - if (!test_bit(max_vq - 1, cpu->sve_vq_map) && - test_bit(max_vq - 1, cpu->sve_vq_init)) { + if (vq_init & ~vq_map & (1 << (max_vq - 1))) { error_setg(errp, "cannot disable sve%d", max_vq * 128); error_append_hint(errp, "The maximum vector length must be " "enabled, sve-max-vq=3D%d (%d bits)\n", @@ -448,8 +447,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) } =20 /* Set all bits not explicitly set within sve-max-vq. */ - bitmap_complement(tmp, cpu->sve_vq_init, max_vq); - bitmap_or(cpu->sve_vq_map, cpu->sve_vq_map, tmp, max_vq); + vq_map |=3D ~vq_init & vq_mask; } =20 /* @@ -458,13 +456,14 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) * are clear, just in case anybody looks. */ assert(max_vq !=3D 0); - bitmap_clear(cpu->sve_vq_map, max_vq, ARM_MAX_VQ - max_vq); + assert(vq_mask !=3D 0); + vq_map &=3D vq_mask; =20 /* Ensure the set of lengths matches what is supported. */ - bitmap_xor(tmp, cpu->sve_vq_map, cpu->sve_vq_supported, max_vq); - if (!bitmap_empty(tmp, max_vq)) { - vq =3D find_last_bit(tmp, max_vq) + 1; - if (test_bit(vq - 1, cpu->sve_vq_map)) { + tmp =3D vq_map ^ (vq_supported & vq_mask); + if (tmp) { + vq =3D 32 - clz32(tmp); + if (vq_map & (1 << (vq - 1))) { if (cpu->sve_max_vq) { error_setg(errp, "cannot set sve-max-vq=3D%d", cpu->sve_ma= x_vq); error_append_hint(errp, "This CPU does not support " @@ -488,15 +487,15 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) return; } else { /* Ensure all required powers-of-two are enabled. */ - for (vq =3D pow2floor(max_vq); vq >=3D 1; vq >>=3D 1) { - if (!test_bit(vq - 1, cpu->sve_vq_map)) { - error_setg(errp, "cannot disable sve%d", vq * 128); - error_append_hint(errp, "sve%d is required as it " - "is a power-of-two length smalle= r " - "than the maximum, sve%d\n", - vq * 128, max_vq * 128); - return; - } + tmp =3D SVE_VQ_POW2_MAP & vq_mask & ~vq_map; + if (tmp) { + vq =3D 32 - clz32(tmp); + error_setg(errp, "cannot disable sve%d", vq * 128); + error_append_hint(errp, "sve%d is required as it " + "is a power-of-two length smaller " + "than the maximum, sve%d\n", + vq * 128, max_vq * 128); + return; } } } @@ -516,6 +515,7 @@ void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) =20 /* From now on sve_max_vq is the actual maximum supported length. */ cpu->sve_max_vq =3D max_vq; + cpu->sve_vq_map =3D vq_map; } =20 static void cpu_max_get_sve_max_vq(Object *obj, Visitor *v, const char *na= me, @@ -576,7 +576,7 @@ static void cpu_arm_get_sve_vq(Object *obj, Visitor *v,= const char *name, if (!cpu_isar_feature(aa64_sve, cpu)) { value =3D false; } else { - value =3D test_bit(vq - 1, cpu->sve_vq_map); + value =3D (cpu->sve_vq_map >> (vq - 1)) & 1; } visit_type_bool(v, name, &value, errp); } @@ -598,12 +598,8 @@ static void cpu_arm_set_sve_vq(Object *obj, Visitor *v= , const char *name, return; } =20 - if (value) { - set_bit(vq - 1, cpu->sve_vq_map); - } else { - clear_bit(vq - 1, cpu->sve_vq_map); - } - set_bit(vq - 1, cpu->sve_vq_init); + cpu->sve_vq_map =3D deposit32(cpu->sve_vq_map, vq - 1, 1, value); + cpu->sve_vq_init |=3D 1 << (vq - 1); } =20 static bool cpu_arm_get_sve(Object *obj, Error **errp) @@ -952,7 +948,7 @@ static void aarch64_max_initfn(Object *obj) cpu->dcz_blocksize =3D 7; /* 512 bytes */ #endif =20 - bitmap_fill(cpu->sve_vq_supported, ARM_MAX_VQ); + cpu->sve_vq_supported =3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); =20 aarch64_add_pauth_properties(obj); aarch64_add_sve_properties(obj); @@ -998,12 +994,11 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; =20 - /* Suppport of A64FX's vector length are 128,256 and 512bit only */ + /* Suppport of A64FX's vector length are 128, 256 and 512bit only */ aarch64_add_sve_properties(obj); - bitmap_zero(cpu->sve_vq_supported, ARM_MAX_VQ); - set_bit(0, cpu->sve_vq_supported); /* 128bit */ - set_bit(1, cpu->sve_vq_supported); /* 256bit */ - set_bit(3, cpu->sve_vq_supported); /* 512bit */ + cpu->sve_vq_supported =3D (1 << 0) /* 128bit */ + | (1 << 1) /* 256bit */ + | (1 << 3); /* 512bit */ =20 /* TODO: Add A64FX specific HPC extension registers */ } diff --git a/target/arm/helper.c b/target/arm/helper.c index 0308920357..edeab4e473 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6225,7 +6225,6 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) { ARMCPU *cpu =3D env_archcpu(env); uint32_t len =3D cpu->sve_max_vq - 1; - uint32_t end_len; =20 if (el <=3D 1 && (arm_hcr_el2_eff(env) & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { @@ -6238,12 +6237,8 @@ uint32_t sve_zcr_len_for_el(CPUARMState *env, int el) len =3D MIN(len, 0xf & (uint32_t)env->vfp.zcr_el[3]); } =20 - end_len =3D len; - if (!test_bit(len, cpu->sve_vq_map)) { - end_len =3D find_last_bit(cpu->sve_vq_map, len); - assert(end_len < len); - } - return end_len; + len =3D 31 - clz32(cpu->sve_vq_map & MAKE_64BIT_MASK(0, len + 1)); + return len; } =20 static void zcr_write(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index b8cfaf5782..16cf01acb5 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -748,15 +748,13 @@ bool kvm_arm_steal_time_supported(void) =20 QEMU_BUILD_BUG_ON(KVM_ARM64_SVE_VQ_MIN !=3D 1); =20 -void kvm_arm_sve_get_vls(CPUState *cs, unsigned long *map) +uint32_t kvm_arm_sve_get_vls(CPUState *cs) { /* Only call this function if kvm_arm_sve_supported() returns true. */ static uint64_t vls[KVM_ARM64_SVE_VLS_WORDS]; static bool probed; uint32_t vq =3D 0; - int i, j; - - bitmap_zero(map, ARM_MAX_VQ); + int i; =20 /* * KVM ensures all host CPUs support the same set of vector lengths. @@ -797,46 +795,24 @@ void kvm_arm_sve_get_vls(CPUState *cs, unsigned long = *map) if (vq > ARM_MAX_VQ) { warn_report("KVM supports vector lengths larger than " "QEMU can enable"); + vls[0] &=3D MAKE_64BIT_MASK(0, ARM_MAX_VQ); } } =20 - for (i =3D 0; i < KVM_ARM64_SVE_VLS_WORDS; ++i) { - if (!vls[i]) { - continue; - } - for (j =3D 1; j <=3D 64; ++j) { - vq =3D j + i * 64; - if (vq > ARM_MAX_VQ) { - return; - } - if (vls[i] & (1UL << (j - 1))) { - set_bit(vq - 1, map); - } - } - } + return vls[0]; } =20 static int kvm_arm_sve_set_vls(CPUState *cs) { - uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D {0}; + ARMCPU *cpu =3D ARM_CPU(cs); + uint64_t vls[KVM_ARM64_SVE_VLS_WORDS] =3D { cpu->sve_vq_map }; struct kvm_one_reg reg =3D { .id =3D KVM_REG_ARM64_SVE_VLS, .addr =3D (uint64_t)&vls[0], }; - ARMCPU *cpu =3D ARM_CPU(cs); - uint32_t vq; - int i, j; =20 assert(cpu->sve_max_vq <=3D KVM_ARM64_SVE_VQ_MAX); =20 - for (vq =3D 1; vq <=3D cpu->sve_max_vq; ++vq) { - if (test_bit(vq - 1, cpu->sve_vq_map)) { - i =3D (vq - 1) / 64; - j =3D (vq - 1) % 64; - vls[i] |=3D 1UL << j; - } - } - return kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); } =20 --=20 2.34.1 From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652767372; cv=none; d=zohomail.com; s=zohoarc; b=h0NDgFZtqytkUyKQR9z4nBp724ayTzhSPGBumFduP9TjnnYfJmEHCchL+6469YmC6KDStjfW0Ig3HzVoXn+7j1qwzduBwgUgjzIVfNX7J6/8BE51cIMqO+nzZukvGogLqg0zgLwH3RqUKD+gcDetkgwFIc0kBMGuJG6SzzI1XFw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652767372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=i+kaX5CHz+xx+6kDKxLaFapfSu0CDuUAbTCZFIx5C8E=; b=X7Pq2VZdq7WYull8DG09/Xrij4wJr/1zpE53TnJwGkEj1RSCl68PDzpmqwl2hPF5Ga Je/B8i8LP2563lBaH7wdMuOicxaYUDpsL0WEc8Ti2CnE1+34CtMbg8C2KAUmJTqZ1+Lh f+Lc2cFWqnurInicT7TDNE/36PxCl26yW6I1yzt0A903AkT5RjrTVPUMbrX2sK0lJzuN iqWNXm8Nd3c/rIiOwhdgldzY9CpNXGwevE0wTmYfz5Owo61ItFSOs416GG9x68n4/1Wo DKkYZNb+w8zdP2/0m0Xlnby+cVRBsU3uDEH8Aac0B6HJ/ocd00xgDKTHhoYhHP0EmpJA D9vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=i+kaX5CHz+xx+6kDKxLaFapfSu0CDuUAbTCZFIx5C8E=; b=gUEhXq9NGwtDJCkWfrr5YzEAbX/u4/OIlYLh5YocHJmd3W++/ptCYQtnpKEP9+wvom So8OSXIgCmJK4ObCvHQ1mKBWfRl15BZPIb8RoGNaHuX5w129hJUETFl8TOmrPYx2HxLJ l/m/Xrt19C1D0Prd74IhJI9ysa38Wrvzxk8D/nJjoYI5Us4Ndv0CLDDh7cx8pAA16bH3 dm+kSGaBzUxqo6ag7fr+2nOsH76OB93aHdzAwSBVIjf/HwhHxHuCjw7DXwZ61JpirfVe c+veb6f9RuN6Fa3Vn3QrN5MRVRTMS/xvh48KYHJVZN1lF5qtBhVzkJrsAkI2IJFcLvQE v0WQ== X-Gm-Message-State: AOAM533kGRs2PJ3jTkZRC0H5inBSmp0zzk6Hf3id3QSGhSWW9Xypt36W 4eVK4pOSfYeA5D9KQVWri0Sv9Wj8ibt5Ng== X-Google-Smtp-Source: ABdhPJxKpUtlNy8Z2WHUtxL5PZ0gqNFlsP1+jA/f+hqCkVm2AnVXPIPhmsZhbWbMp9pe7cbjban41A== X-Received: by 2002:a17:903:2055:b0:161:7399:3b89 with SMTP id q21-20020a170903205500b0016173993b89mr9479448pla.22.1652766536846; Mon, 16 May 2022 22:48:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 6/7] target/arm: Remove fp checks from sve_exception_el Date: Mon, 16 May 2022 22:48:49 -0700 Message-Id: <20220517054850.177016-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::636; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x636.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652767373162100003 Content-Type: text/plain; charset="utf-8" Instead of checking these bits in fp_exception_el and also in sve_exception_el, document that we must compare the results. The only place where we have not already checked that FP EL is zero is in rebuild_hflags_a64. Signed-off-by: Richard Henderson --- target/arm/helper.c | 52 ++++++++++++++------------------------------- 1 file changed, 16 insertions(+), 36 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index edeab4e473..05baa73986 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6136,10 +6136,12 @@ static const ARMCPRegInfo minimal_ras_reginfo[] =3D= { .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, }; =20 -/* Return the exception level to which exceptions should be taken - * via SVEAccessTrap. If an exception should be routed through - * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should - * take care of raising that exception. +/* + * Return the exception level to which exceptions should be taken + * via SVEAccessTrap. This excludes the check for whether the exception + * should be routed through AArch64.AdvSIMDFPAccessTrap. That can easily + * be found by testing 0 < fp_exception_el <=3D sve_exception_el. + * * C.f. the ARM pseudocode function CheckSVEEnabled. */ int sve_exception_el(CPUARMState *env, int el) @@ -6159,18 +6161,6 @@ int sve_exception_el(CPUARMState *env, int el) /* route_to_el2 */ return hcr_el2 & HCR_TGE ? 2 : 1; } - - /* Check CPACR.FPEN. */ - switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { - case 1: - if (el !=3D 0) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } =20 /* @@ -6188,24 +6178,10 @@ int sve_exception_el(CPUARMState *env, int el) case 2: return 2; } - - switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { - case 1: - if (el =3D=3D 2 || !(hcr_el2 & HCR_TGE)) { - break; - } - /* fall through */ - case 0: - case 2: - return 0; - } } else if (arm_is_el2_enabled(env)) { if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { - return 0; - } } } =20 @@ -13541,15 +13517,19 @@ static CPUARMTBFlags rebuild_hflags_a64(CPUARMSta= te *env, int el, int fp_el, =20 if (cpu_isar_feature(aa64_sve, env_archcpu(env))) { int sve_el =3D sve_exception_el(env, el); - uint32_t zcr_len; + uint32_t zcr_len =3D 0; =20 /* - * If SVE is disabled, but FP is enabled, - * then the effective len is 0. + * If either FP or SVE are disabled, translator does not need len. + * If SVE EL >=3D FP EL, FP exception has precedence, and translat= or + * does not need SVE EL. Save potential re-translations by forcing + * the unneeded data to zero. */ - if (sve_el !=3D 0 && fp_el =3D=3D 0) { - zcr_len =3D 0; - } else { + if (fp_el !=3D 0) { + if (sve_el >=3D fp_el) { + sve_el =3D 0; + } + } else if (sve_el =3D=3D 0) { zcr_len =3D sve_zcr_len_for_el(env, el); } DP_TBFLAG_A64(flags, SVEEXC_EL, sve_el); --=20 2.34.1 From nobody Mon Apr 29 21:43:27 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652767523; cv=none; d=zohomail.com; s=zohoarc; b=g0FT2IWmphkYmPlj67NmAu+9E7U+B80FjJxmAIQbCrelMQT+JIPWQ0xm9Ed/1z5DrQ/kbeeJ3g73wMfK/A3VhItVCpbM6zsJ+zrQophmI18xg6xRXNsP3O7S5TEmbCTj8WUYMjDZqzAOcJ6UDTtdzYynSdDOMfzNcrlv+N8gWSA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652767523; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QZWPLUoqPQwRNEP7N/mQ6KcZy+VCmkdoHNOMQdySREE=; b=ZZMcOZVJE+XOdjmqoDPoBy4c/KMFBBIo73hnuuyymuL41MbX7e2wHZcVOsRqkvF1J52vV2gPFibQ1/K8f3jdGhhmXoo4SF44dW1kWFyWzU1aesjfUPoBqOY5ksPkzt9xYyogRdyyrenWQIm4cojua512p2JRZDvJNYmC7TwyZek= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652767523336508.9502898029933; Mon, 16 May 2022 23:05:23 -0700 (PDT) Received: from localhost ([::1]:57364 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nqqKf-0005Xj-Sp for importer@patchew.org; Tue, 17 May 2022 02:05:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nqq4r-0000UA-GS for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:04 -0400 Received: from mail-pl1-x629.google.com ([2607:f8b0:4864:20::629]:37525) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nqq4o-0007on-Rk for qemu-devel@nongnu.org; Tue, 17 May 2022 01:49:01 -0400 Received: by mail-pl1-x629.google.com with SMTP id m12so16441134plb.4 for ; Mon, 16 May 2022 22:48:58 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id b12-20020a170902d88c00b0015e8d4eb1fasm8146670plz.68.2022.05.16.22.48.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 16 May 2022 22:48:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QZWPLUoqPQwRNEP7N/mQ6KcZy+VCmkdoHNOMQdySREE=; b=BBhBZtGRqYUcaXBpG3+7zdUq4zM39qyTm8nURSTNIjHnbz5pOkzIcYC8RxCzIp47+v TAkGa/N0jhmz8Ym/9EFVaBZ5DouqalXAQLRPY825oBFCIs0kc74X7gKGW30qdlhkws2H AVM3G7vPwrjCXqkalrqsPgYJTcN/J0hyxpAQfCp46T73V0f+zDYVyD+wss21NAO1sIXS EGP2LnsobAhFODS2UmKccGdbeVCNAKDweB8u8LKJMJJHIVxeXJETn1zxdWP3qvzZJ6dg qNL4TVLKcN8ouc2IIiFLsji3tGFdKpI4JnLpKYG+Jd2nVZX5rc3haGGPpwVMcjrfim1t Q11Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QZWPLUoqPQwRNEP7N/mQ6KcZy+VCmkdoHNOMQdySREE=; b=44yP5asN09NTcI7ivOZo16gg5owFpx9+f7acaFS/opf9b4Cx9Nc3Jl7RFxUXw8Kqhg WwLd9TXHg+/cblv3oRlZLpKT6xRYxtLNQjhOQk/ar1qISf8vfibLURodRk2iIetleaaK BT9NVnXDXzZ5JOeCkWPTMiEtg/Xy5Va9sMFdIkshpX9OFFbd9S4+YHBBWoeq92bjXm35 149am45BP78eWGb64KTP1+0++7807d/xK7mkeZxpnhrC54UBc96wIC68/JPzxR7dMBmN sBym4cTTEsF8BNfar4wn+dR1roGiaNEMdYXPEXqPXvVm23GwC8SFwVK63WNKw1tiMG8o PMHg== X-Gm-Message-State: AOAM532ECQH+/mLVGq7bTOQX4X7O45M6LIE83+OeyKEs3szReOudeYt0 17Iij01RkZ0xegdcBZwQNrYrsZDZN2V86Q== X-Google-Smtp-Source: ABdhPJxNbcJ2WEtplO7A94Z0nRL9ghXu2Lcm4aR2rFSS7DQww7rL2fqdQq37LZpLPTKEwaWtlV4Hpw== X-Received: by 2002:a17:90b:35cc:b0:1df:8218:a427 with SMTP id nb12-20020a17090b35cc00b001df8218a427mr2478553pjb.15.1652766537541; Mon, 16 May 2022 22:48:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH v2 7/7] target/arm: Add el_is_in_host Date: Mon, 16 May 2022 22:48:50 -0700 Message-Id: <20220517054850.177016-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220517054850.177016-1-richard.henderson@linaro.org> References: <20220517054850.177016-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::629; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x629.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652767524277100001 Content-Type: text/plain; charset="utf-8" This (newish) ARM pseudocode function is easier to work with than open-coded tests for HCR_E2H etc. Use of the function will be staged into the code base in parts. Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 ++ target/arm/helper.c | 23 +++++++++++++++++++++++ 2 files changed, 25 insertions(+) diff --git a/target/arm/internals.h b/target/arm/internals.h index 4165d49570..58392c8246 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1310,6 +1310,8 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +bool el_is_in_host(CPUARMState *env, int el); + void aa32_max_features(ARMCPU *cpu); =20 /* Powers of 2 for sve_vq_map et al. */ diff --git a/target/arm/helper.c b/target/arm/helper.c index 05baa73986..d082a1cf18 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5282,6 +5282,29 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +/* + * Corresponds to ARM pseudocode function ELIsInHost(). + */ +bool el_is_in_host(CPUARMState *env, int el) +{ + uint64_t mask; + /* + * Since we only care about E2H and TGE, we can skip arm_hcr_el2_eff. + * Perform the simplest bit tests first, and validate EL2 afterward. + */ + if (el & 1) { + return false; /* EL1 or EL3 */ + } + + mask =3D el ? HCR_E2H : HCR_E2H | HCR_TGE; + if ((env->cp15.hcr_el2 & mask) !=3D mask) { + return false; + } + + /* TGE and/or E2H set: double check those bits are currently legal. */ + return arm_is_el2_enabled(env) && arm_el_is_aa64(env, 2); +} + static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { --=20 2.34.1