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[89.14.181.123]) by smtp.gmail.com with ESMTPSA id ci18-20020a170907267200b006f3ef214e3esm953874ejc.164.2022.05.13.10.54.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 May 2022 10:54:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=9fyFY+E6JJjVdT5p/+Wp03gGdDkS94wyw4n8PQHDYiA=; b=qsWemKgHXO+hXoAyiTh5Lcy91eu0qBEOGnMF1dlqZNZqp1rQ9ptihyJwL7MZ84qvQ3 OaCGZNyGkMC0bENwhc+AMjd3sQOzL6RatBprHqpiaWjHqHOy0T6l7iRKK7nLBQTbli0Y gGTOTBZKIT7D+0+OWJ+2B/XwnXmuljMsO36LEgspATuUZ2/Yb5XB99LK4FX2f5i996Ff 2ehQBnbvb58EfiqZI8m6Hj3FqH8ATBXH1OJJ9qcm7jg/pTfkTrSlotjXgqLo7gSrrwO7 w6w0bLj6VOnHnPdj5mE1pnODdF/N7ylXhJ7/bS+u9sm0jNyjb6tBnjLm0myW7v4LYeen Vsqg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=9fyFY+E6JJjVdT5p/+Wp03gGdDkS94wyw4n8PQHDYiA=; b=dsF60M6R8zcpgp+P4rtuRgApYaVcq0yXs/3Ui5SVrmrWC7qDsuieTA1lJJ5ytCngRb tSeS4XPp/X5KIL8VzVSW4yiDuB+3XEn6a+E7CmpHVtP/CDpiQOGduc6NDSxftlu3IYoP tchvR9TbjYklb6/BnAevDwaCOuyqe3NuoCAubdO6zVQXtyvlhKOyFVyfoZMOBcTsszkq tXok9m3yE0ke7glSOwVBwr2bZxHAHE/XCwYmKRfC0hi1kKzLYdN2Tk/jTLl10gEyqxjA V9IS0aZcTWNYRHrWzkVefrn2RGtltgEchw52kiH2mVzo08tsrau2Z6+tL+EfLbzNF4Vl GWVA== X-Gm-Message-State: AOAM533UOEQPo+89Wa72PBSQPfZZDoyT9PpYNXOcYkKscpLhmG+zH3AZ Pgfmnyor/a6osYNNG6jpyuVXKO25GPU= X-Google-Smtp-Source: ABdhPJwkZ9ghJLzaakaY3NvWYMmn7TMqV1AKuxwiTNTXCx+8BsavE5NlC4dGZVb50yqOXL1zP2hytA== X-Received: by 2002:a17:907:6088:b0:6f4:bc5b:ab3c with SMTP id ht8-20020a170907608800b006f4bc5bab3cmr5332056ejc.236.1652464499471; Fri, 13 May 2022 10:54:59 -0700 (PDT) From: Bernhard Beschow To: qemu-devel@nongnu.org Cc: qemu-trivial@nongnu.org, Bernhard Beschow , "Michael S. Tsirkin" , Marcel Apfelbaum , =?UTF-8?q?Philippe=20Mathieu-Daud=C3=A9?= , Aurelien Jarno , =?UTF-8?q?Herv=C3=A9=20Poussineau?= Subject: [PATCH 3/6] hw/isa/piix{3,4}: QOM'ify PCI device creation and wiring Date: Fri, 13 May 2022 19:54:42 +0200 Message-Id: <20220513175445.89616-4-shentey@gmail.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220513175445.89616-1-shentey@gmail.com> References: <20220513175445.89616-1-shentey@gmail.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::632; envelope-from=shentey@gmail.com; helo=mail-ej1-x632.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1652464713395100001 Content-Type: text/plain; charset="utf-8" PCI interrupt wiring and device creation (piix4 only) were performed in create() functions which are obsolete. Move these tasks into QOM functions to modernize the code. In order to avoid duplicate checking for xen_enabled() the piix3 realize methods are now split. Signed-off-by: Bernhard Beschow Reviewed-by: Mark Cave-Ayland --- hw/isa/piix3.c | 67 +++++++++++++++++++++++++++++++++----------------- hw/isa/piix4.c | 20 +++++++++------ 2 files changed, 57 insertions(+), 30 deletions(-) diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index 7d69420967..d15117a7c7 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -24,6 +24,7 @@ =20 #include "qemu/osdep.h" #include "qemu/range.h" +#include "qapi/error.h" #include "hw/southbridge/piix.h" #include "hw/irq.h" #include "hw/isa/isa.h" @@ -280,7 +281,7 @@ static const MemoryRegionOps rcr_ops =3D { .endianness =3D DEVICE_LITTLE_ENDIAN }; =20 -static void piix3_realize(PCIDevice *dev, Error **errp) +static void pci_piix3_realize(PCIDevice *dev, Error **errp) { PIIX3State *d =3D PIIX3_PCI_DEVICE(dev); =20 @@ -305,7 +306,6 @@ static void pci_piix3_class_init(ObjectClass *klass, vo= id *data) dc->desc =3D "ISA bridge"; dc->vmsd =3D &vmstate_piix3; dc->hotpluggable =3D false; - k->realize =3D piix3_realize; k->vendor_id =3D PCI_VENDOR_ID_INTEL; /* 82371SB PIIX3 PCI-to-ISA bridge (Step A1) */ k->device_id =3D PCI_DEVICE_ID_INTEL_82371SB_0; @@ -329,11 +329,28 @@ static const TypeInfo piix3_pci_type_info =3D { }, }; =20 +static void piix3_realize(PCIDevice *dev, Error **errp) +{ + ERRP_GUARD(); + PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus =3D pci_get_bus(dev); + + pci_piix3_realize(dev, errp); + if (*errp) { + return; + } + + pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, + piix3, PIIX_NUM_PIRQS); + pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); +}; + static void piix3_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->config_write =3D piix3_write_config; + k->realize =3D piix3_realize; } =20 static const TypeInfo piix3_info =3D { @@ -342,11 +359,33 @@ static const TypeInfo piix3_info =3D { .class_init =3D piix3_class_init, }; =20 +static void piix3_xen_realize(PCIDevice *dev, Error **errp) +{ + ERRP_GUARD(); + PIIX3State *piix3 =3D PIIX3_PCI_DEVICE(dev); + PCIBus *pci_bus =3D pci_get_bus(dev); + + pci_piix3_realize(dev, errp); + if (*errp) { + return; + } + + /* + * Xen supports additional interrupt routes from the PCI devices to + * the IOAPIC: the four pins of each PCI device on the bus are also + * connected to the IOAPIC directly. + * These additional routes can be discovered through ACPI. + */ + pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, + piix3, XEN_PIIX_NUM_PIRQS); +}; + static void piix3_xen_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k =3D PCI_DEVICE_CLASS(klass); =20 k->config_write =3D piix3_write_config_xen; + k->realize =3D piix3_xen_realize; }; =20 static const TypeInfo piix3_xen_info =3D { @@ -368,27 +407,11 @@ PIIX3State *piix3_create(PCIBus *pci_bus, ISABus **is= a_bus) { PIIX3State *piix3; PCIDevice *pci_dev; + const char *type =3D xen_enabled() ? TYPE_PIIX3_XEN_DEVICE + : TYPE_PIIX3_DEVICE; =20 - /* - * Xen supports additional interrupt routes from the PCI devices to - * the IOAPIC: the four pins of each PCI device on the bus are also - * connected to the IOAPIC directly. - * These additional routes can be discovered through ACPI. - */ - if (xen_enabled()) { - pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, - TYPE_PIIX3_XEN_DEVICE); - piix3 =3D PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(pci_bus, xen_piix3_set_irq, xen_pci_slot_get_pirq, - piix3, XEN_PIIX_NUM_PIRQS); - } else { - pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, - TYPE_PIIX3_DEVICE); - piix3 =3D PIIX3_PCI_DEVICE(pci_dev); - pci_bus_irqs(pci_bus, piix3_set_irq, pci_slot_get_pirq, - piix3, PIIX_NUM_PIRQS); - pci_bus_set_route_irq_fn(pci_bus, piix3_route_intx_pin_to_irq); - } + pci_dev =3D pci_create_simple_multifunction(pci_bus, -1, true, type); + piix3 =3D PIIX3_PCI_DEVICE(pci_dev); *isa_bus =3D ISA_BUS(qdev_get_child_bus(DEVICE(piix3), "isa.0")); =20 return piix3; diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index a223b69e24..134d23aea7 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -204,6 +204,8 @@ static const MemoryRegionOps piix4_rcr_ops =3D { static void piix4_realize(PCIDevice *dev, Error **errp) { PIIX4State *s =3D PIIX4_PCI_DEVICE(dev); + PCIDevice *pci; + PCIBus *pci_bus =3D pci_get_bus(dev); ISABus *isa_bus; qemu_irq *i8259_out_irq; =20 @@ -242,6 +244,15 @@ static void piix4_realize(PCIDevice *dev, Error **errp) return; } s->rtc.irq =3D isa_get_irq(ISA_DEVICE(&s->rtc), s->rtc.isairq); + + /* IDE */ + pci =3D pci_create_simple(pci_bus, dev->devfn + 1, "piix4-ide"); + pci_ide_create_devs(pci); + + /* USB */ + pci_create_simple(pci_bus, dev->devfn + 2, "piix4-usb-uhci"); + + pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PI= RQS); } =20 static void piix4_init(Object *obj) @@ -292,7 +303,6 @@ type_init(piix4_register_types) =20 DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbu= s) { - PIIX4State *s; PCIDevice *pci; DeviceState *dev; int devfn =3D PCI_DEVFN(10, 0); @@ -300,22 +310,16 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **i= sa_bus, I2CBus **smbus) pci =3D pci_create_simple_multifunction(pci_bus, devfn, true, TYPE_PIIX4_PCI_DEVICE); dev =3D DEVICE(pci); - s =3D PIIX4_PCI_DEVICE(pci); + if (isa_bus) { *isa_bus =3D ISA_BUS(qdev_get_child_bus(dev, "isa.0")); } =20 - pci =3D pci_create_simple(pci_bus, devfn + 1, "piix4-ide"); - pci_ide_create_devs(pci); - - pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { *smbus =3D piix4_pm_init(pci_bus, devfn + 3, 0x1100, qdev_get_gpio_in_named(dev, "isa", 9), NULL, 0, NULL); } =20 - pci_bus_irqs(pci_bus, piix4_set_irq, pci_slot_get_pirq, s, PIIX_NUM_PI= RQS); - return dev; } --=20 2.36.1