From nobody Tue Feb 10 09:10:49 2026 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id DE074C433EF for ; Wed, 11 May 2022 22:00:34 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1348487AbiEKWAd (ORCPT ); Wed, 11 May 2022 18:00:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1348468AbiEKWAU (ORCPT ); Wed, 11 May 2022 18:00:20 -0400 Received: from mail-pj1-x1035.google.com (mail-pj1-x1035.google.com [IPv6:2607:f8b0:4864:20::1035]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0E89A16D13D for ; Wed, 11 May 2022 15:00:16 -0700 (PDT) Received: by mail-pj1-x1035.google.com with SMTP id iq10so3487001pjb.0 for ; Wed, 11 May 2022 15:00:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=rivosinc-com.20210112.gappssmtp.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=v0blOO6OMMRpfB03V+aWer2Uy71SbSrW98ReFlCeP2c=; b=m55T1fgtiCBZjB2RHZNG6pIhzzEg0Iimz9pQLOXxGYdg1e2/FqiMA6WrR1UHRsqBSI S1+IaZivFtFvnaV8hYvlNS0tZDZNCJRr+MUTLkisxMngs7m9mNY3YL1TnOqIPvca0QOv 7xsQTcnpNdi7LvxWBuWmDPl0uG8LxqySeH5ofqysjYA72Wki3ykg3m3G7vM2Pbresc51 0ZPB0tkfMZLFDhLdrRTiITmcV6jf/GEdRfLQPexbwoPED84qDBFd8XaraNaSKmeybtpS 67cKUY0hdGjTkw+1HYz38BSQnXsoNY6U6UGPUmWZJyy6bWtLm1maPTPylphAaFn6O+8l P4vQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=v0blOO6OMMRpfB03V+aWer2Uy71SbSrW98ReFlCeP2c=; b=msMNLlC69vSH0HMnDbtcExlgsM+tA8s1Ist2+UDAxQGp+OQ2Jc/LH2dih4dXUQhHPw ArdWrox9yaBe/yrRmMKJYD55d6pKx8sZCnJEpynrZ/g4E1KnSnKeNEY7wb5wsXR4w+fK eiWYcIGlqUpxpEwDOqDhahZTGixrDrYLUohO7KuyALol9T2Ot2Y95vVrgahz+TqBvQbI NhEhYct9QntvPvsgTxWF0etKeIV1EgrpqeSwPQvT8dX0TmTOkc/1W99mZsdEjXD3CLV0 xPINhd/HNbZxqLHuxB4xSfxG8CFaPmRTyR3rNjxc5p2rZ9ZqK6A2s4V9weV21IYTn+7u 6cJQ== X-Gm-Message-State: AOAM532M+dg3D1EZatk9pCJz+UcSpuvuMYVQiLYweWXiuCnX2Y0yucAy L4jhtgE8aJ9u3NCdcM0pKqXpeBTZQ2XK0A== X-Google-Smtp-Source: ABdhPJxlK9brAtSBaEkVJiOsCmELqbknRSm9bs7pddRMmB3v9K01c/9z8+YRTcY1RDClGarj5APLsA== X-Received: by 2002:a17:90a:ab90:b0:1da:375f:2f44 with SMTP id n16-20020a17090aab9000b001da375f2f44mr7444064pjq.33.1652306414824; Wed, 11 May 2022 15:00:14 -0700 (PDT) Received: from atishp.ba.rivosinc.com ([66.220.2.162]) by smtp.gmail.com with ESMTPSA id r23-20020a62e417000000b0050dc762816asm2261303pfh.68.2022.05.11.15.00.13 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 May 2022 15:00:14 -0700 (PDT) From: Atish Patra To: linux-kernel@vger.kernel.org Cc: Bin Meng , Alistair Francis , Atish Patra , Bin Meng , Palmer Dabbelt , qemu-devel@nongnu.org, qemu-riscv@nongnu.org Subject: [PATCH v8 04/12] target/riscv: pmu: Make number of counters configurable Date: Wed, 11 May 2022 14:59:48 -0700 Message-Id: <20220511215956.2351243-5-atishp@rivosinc.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220511215956.2351243-1-atishp@rivosinc.com> References: <20220511215956.2351243-1-atishp@rivosinc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" The RISC-V privilege specification provides flexibility to implement any number of counters from 29 programmable counters. However, the QEMU implements all the counters. Make it configurable through pmu config parameter which now will indicate how many programmable counters should be implemented by the cpu. Reviewed-by: Bin Meng Reviewed-by: Alistair Francis Signed-off-by: Atish Patra Signed-off-by: Atish Patra --- target/riscv/cpu.c | 2 +- target/riscv/cpu.h | 2 +- target/riscv/csr.c | 94 ++++++++++++++++++++++++++++++---------------- 3 files changed, 63 insertions(+), 35 deletions(-) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 5ad17b40189f..2dc4b500797d 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -822,7 +822,7 @@ static Property riscv_cpu_properties[] =3D { DEFINE_PROP_BOOL("u", RISCVCPU, cfg.ext_u, true), DEFINE_PROP_BOOL("v", RISCVCPU, cfg.ext_v, false), DEFINE_PROP_BOOL("h", RISCVCPU, cfg.ext_h, true), - DEFINE_PROP_BOOL("pmu", RISCVCPU, cfg.ext_pmu, true), + DEFINE_PROP_UINT8("pmu-num", RISCVCPU, cfg.pmu_num, 16), DEFINE_PROP_BOOL("Zifencei", RISCVCPU, cfg.ext_ifencei, true), DEFINE_PROP_BOOL("Zicsr", RISCVCPU, cfg.ext_icsr, true), DEFINE_PROP_BOOL("Zfh", RISCVCPU, cfg.ext_zfh, false), diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 09a0c71093c5..7cbcd8d62fc1 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -391,7 +391,6 @@ struct RISCVCPUConfig { bool ext_zksed; bool ext_zksh; bool ext_zkt; - bool ext_pmu; bool ext_ifencei; bool ext_icsr; bool ext_svinval; @@ -413,6 +412,7 @@ struct RISCVCPUConfig { /* Vendor-specific custom extensions */ bool ext_XVentanaCondOps; =20 + uint8_t pmu_num; char *priv_spec; char *user_spec; char *bext_spec; diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c625b17dd58e..7e14f7685fb9 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -73,9 +73,17 @@ static RISCVException ctr(CPURISCVState *env, int csrno) CPUState *cs =3D env_cpu(env); RISCVCPU *cpu =3D RISCV_CPU(cs); int ctr_index; + int base_csrno =3D CSR_HPMCOUNTER3; + bool rv32 =3D riscv_cpu_mxl(env) =3D=3D MXL_RV32 ? true : false; =20 - if (!cpu->cfg.ext_pmu) { - /* The PMU extension is not enabled */ + if (rv32 && csrno >=3D CSR_CYCLEH) { + /* Offset for RV32 hpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; + + if (!cpu->cfg.pmu_num || ctr_index >=3D (cpu->cfg.pmu_num)) { + /* No counter is enabled in PMU or the counter is out of range */ return RISCV_EXCP_ILLEGAL_INST; } =20 @@ -103,7 +111,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + if (rv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->mcounteren, COUNTEREN_CY)) { @@ -158,7 +166,7 @@ static RISCVException ctr(CPURISCVState *env, int csrno) } break; } - if (riscv_cpu_mxl(env) =3D=3D MXL_RV32) { + if (rv32) { switch (csrno) { case CSR_CYCLEH: if (!get_field(env->hcounteren, COUNTEREN_CY) && @@ -202,6 +210,26 @@ static RISCVException ctr32(CPURISCVState *env, int cs= rno) } =20 #if !defined(CONFIG_USER_ONLY) +static RISCVException mctr(CPURISCVState *env, int csrno) +{ + CPUState *cs =3D env_cpu(env); + RISCVCPU *cpu =3D RISCV_CPU(cs); + int ctr_index; + int base_csrno =3D CSR_MHPMCOUNTER3; + + if ((riscv_cpu_mxl(env) =3D=3D MXL_RV32) && csrno >=3D CSR_MCYCLEH) { + /* Offset for RV32 mhpmcounternh counters */ + base_csrno +=3D 0x80; + } + ctr_index =3D csrno - base_csrno; + if (!cpu->cfg.pmu_num || ctr_index >=3D cpu->cfg.pmu_num) { + /* The PMU is not enabled or counter is out of range*/ + return RISCV_EXCP_ILLEGAL_INST; + } + + return RISCV_EXCP_NONE; +} + static RISCVException any(CPURISCVState *env, int csrno) { return RISCV_EXCP_NONE; @@ -3683,35 +3711,35 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D { [CSR_HPMCOUNTER30] =3D { "hpmcounter30", ctr, read_zero }, [CSR_HPMCOUNTER31] =3D { "hpmcounter31", ctr, read_zero }, =20 - [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", any, read_zero }, - [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", any, read_zero }, - [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", any, read_zero }, - [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", any, read_zero }, - [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", any, read_zero }, - [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", any, read_zero }, - [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", any, read_zero }, - [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", any, read_zero }, - [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", any, read_zero }, - [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", any, read_zero }, - [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", any, read_zero }, - [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", any, read_zero }, - [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", any, read_zero }, - [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", any, read_zero }, - [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", any, read_zero }, - [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", any, read_zero }, - [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", any, read_zero }, - [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", any, read_zero }, - [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", any, read_zero }, - [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", any, read_zero }, - [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", any, read_zero }, - [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", any, read_zero }, - [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", any, read_zero }, - [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", any, read_zero }, - [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", any, read_zero }, - [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", any, read_zero }, - [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", any, read_zero }, - [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", any, read_zero }, - [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", any, read_zero }, + [CSR_MHPMCOUNTER3] =3D { "mhpmcounter3", mctr, read_zero }, + [CSR_MHPMCOUNTER4] =3D { "mhpmcounter4", mctr, read_zero }, + [CSR_MHPMCOUNTER5] =3D { "mhpmcounter5", mctr, read_zero }, + [CSR_MHPMCOUNTER6] =3D { "mhpmcounter6", mctr, read_zero }, + [CSR_MHPMCOUNTER7] =3D { "mhpmcounter7", mctr, read_zero }, + [CSR_MHPMCOUNTER8] =3D { "mhpmcounter8", mctr, read_zero }, + [CSR_MHPMCOUNTER9] =3D { "mhpmcounter9", mctr, read_zero }, + [CSR_MHPMCOUNTER10] =3D { "mhpmcounter10", mctr, read_zero }, + [CSR_MHPMCOUNTER11] =3D { "mhpmcounter11", mctr, read_zero }, + [CSR_MHPMCOUNTER12] =3D { "mhpmcounter12", mctr, read_zero }, + [CSR_MHPMCOUNTER13] =3D { "mhpmcounter13", mctr, read_zero }, + [CSR_MHPMCOUNTER14] =3D { "mhpmcounter14", mctr, read_zero }, + [CSR_MHPMCOUNTER15] =3D { "mhpmcounter15", mctr, read_zero }, + [CSR_MHPMCOUNTER16] =3D { "mhpmcounter16", mctr, read_zero }, + [CSR_MHPMCOUNTER17] =3D { "mhpmcounter17", mctr, read_zero }, + [CSR_MHPMCOUNTER18] =3D { "mhpmcounter18", mctr, read_zero }, + [CSR_MHPMCOUNTER19] =3D { "mhpmcounter19", mctr, read_zero }, + [CSR_MHPMCOUNTER20] =3D { "mhpmcounter20", mctr, read_zero }, + [CSR_MHPMCOUNTER21] =3D { "mhpmcounter21", mctr, read_zero }, + [CSR_MHPMCOUNTER22] =3D { "mhpmcounter22", mctr, read_zero }, + [CSR_MHPMCOUNTER23] =3D { "mhpmcounter23", mctr, read_zero }, + [CSR_MHPMCOUNTER24] =3D { "mhpmcounter24", mctr, read_zero }, + [CSR_MHPMCOUNTER25] =3D { "mhpmcounter25", mctr, read_zero }, + [CSR_MHPMCOUNTER26] =3D { "mhpmcounter26", mctr, read_zero }, + [CSR_MHPMCOUNTER27] =3D { "mhpmcounter27", mctr, read_zero }, + [CSR_MHPMCOUNTER28] =3D { "mhpmcounter28", mctr, read_zero }, + [CSR_MHPMCOUNTER29] =3D { "mhpmcounter29", mctr, read_zero }, + [CSR_MHPMCOUNTER30] =3D { "mhpmcounter30", mctr, read_zero }, + [CSR_MHPMCOUNTER31] =3D { "mhpmcounter31", mctr, read_zero }, =20 [CSR_MHPMEVENT3] =3D { "mhpmevent3", any, read_zero }, [CSR_MHPMEVENT4] =3D { "mhpmevent4", any, read_zero }, --=20 2.25.1