From nobody Tue May 14 18:41:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652141384; cv=none; d=zohomail.com; s=zohoarc; b=VB/0I7sa68s4AlLYCmybL0UX9BR4k5bwaf4aKQeLVcxjdkmFPEhRsPSzB+4x2vfA38ZoyFZjAZyON5+xQi/66MHCzVqekzJpWIiLQvThsmBSgM7oxMBZ8bScg0ZxHYL9qYs6dI/PidE/me/gUhdAtH7IJtObQlaynTTCarITXt8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652141384; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aqE31/G84do5x2ANoQ3B3dzVwa3TzsZPNoyk2qXIy4U=; b=borkZZ5Iw0KbxPlCf3l7I9FQA/j78JfWjiXbuNzAX5+zBcoL8cAKWZFYLEb6yd+FJXUjZVcLWKAgrKWKXmswr71D9dITv+Q6s56jYLgy5AgXIiR71Te/UMviQTaVO44LYL+98cTgG4xFmv1xy+MbSHhvOhVv6AaQtqT9x4tApoU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652141384794894.8008066062766; Mon, 9 May 2022 17:09:44 -0700 (PDT) Received: from localhost ([::1]:57442 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noDRf-0001yl-I2 for importer@patchew.org; Mon, 09 May 2022 20:09:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noDMh-000633-55 for qemu-devel@nongnu.org; Mon, 09 May 2022 20:04:35 -0400 Received: from mail-pg1-x52b.google.com ([2607:f8b0:4864:20::52b]:33301) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1noDMd-0005B1-5z for qemu-devel@nongnu.org; Mon, 09 May 2022 20:04:33 -0400 Received: by mail-pg1-x52b.google.com with SMTP id k14so13340739pga.0 for ; Mon, 09 May 2022 17:04:30 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id x71-20020a63864a000000b003c15f7f2914sm8983691pgd.24.2022.05.09.17.04.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 17:04:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=aqE31/G84do5x2ANoQ3B3dzVwa3TzsZPNoyk2qXIy4U=; b=KLwemzzHeX4PZOxSfbuIpLv9DLs33SwwMpOPmus6sBaeMQj1+Xez+NefjypPn+8OKm /j3aVuJ79ObxFS1tuE7LbLWwmnvwIocv9qAWKfiGuQolgTkKgQ2oHswo4o1Mv0wFkfQ6 b/cadO7cXPRlUfpse0Ei+z9xn1gankGTRaIEVmX79ar6OxvKWOXPOvVmx0oJWjWSSlD1 U9TOTFxEZSBZ97iMquzHfqOV/A7vg8PmqdKB7SseoS6H3Mvyw1wF24RfsXvQyoM5DTEW SQdiQn4BXf/k4EbHgNuTIAsluTIK4zohT1tUXHxjOWxWmYeXdYiFG+o7c60UlwmPWzu8 x+hg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aqE31/G84do5x2ANoQ3B3dzVwa3TzsZPNoyk2qXIy4U=; b=TuQojpp9ceD4Vji2HglmCg8M9UYO1puWh7mn/X02k91MvlzKVHpuItkRdIBqIdhOII viIoAG+Izp7VvmyyUSHAd3AfnapL2/6oNMKgg8nkRYBwZMTK1BUQCh+iEexF2mi02cPP Cd9mS78ky5EpJP+R6JWzdH877goxA/3DDauMpj5TLQE4MDqp8aq8JUoWL7lTImOOY2FX heBFSShOcgN3dCN/O7fQTNzfP38Nc/YUzlvEc3sNK1Ex3xcB1s6Rv4YV8yFbTm5zi6S5 C29Eh5jVhQzxjaKkmm+lqxTqN7yxkHJQaf8F0iUxLUznqKKImUNUTgFlwF6oAVwKfL1a JEqw== X-Gm-Message-State: AOAM530ScwnTlScbqSGrR56u8b5KVNzjLJtC77kO/yCfFiXOHS+9d7F1 ZzmFU0Xf8g4fyR5nJFHlDGLKDv7QYvbzxg== X-Google-Smtp-Source: ABdhPJwzIwXpYENzfPNtoZLi6iizJ2XMH6dtNli83apgfj85yqbNlkm34tmHtyinQIWVRWo+BEDvEw== X-Received: by 2002:a05:6a00:1385:b0:50a:9768:9eca with SMTP id t5-20020a056a00138500b0050a97689ecamr17726661pfg.43.1652141069550; Mon, 09 May 2022 17:04:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 1/2] target/arm: Enable FEAT_HCX for -cpu max Date: Mon, 9 May 2022 17:04:25 -0700 Message-Id: <20220510000426.45797-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220510000426.45797-1-richard.henderson@linaro.org> References: <20220510000426.45797-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52b; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652141387184100001 Content-Type: text/plain; charset="utf-8" This feature adds a new register, HCRX_EL2, which controls many of the newer AArch64 features. So far the register is effectively RES0, because none of the new features are done. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 20 ++++++++++++++++++ target/arm/cpu64.c | 1 + target/arm/helper.c | 50 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 71 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 18ca61e8e2..b35b117fe7 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -362,6 +362,7 @@ typedef struct CPUArchState { uint32_t pmsav5_data_ap; /* PMSAv5 MPU data access permissions */ uint32_t pmsav5_insn_ap; /* PMSAv5 MPU insn access permissions */ uint64_t hcr_el2; /* Hypervisor configuration register */ + uint64_t hcrx_el2; /* Extended Hypervisor configuration register */ uint64_t scr_el3; /* Secure configuration register. */ union { /* Fault status registers. */ struct { @@ -1543,6 +1544,19 @@ static inline void xpsr_write(CPUARMState *env, uint= 32_t val, uint32_t mask) #define HCR_TWEDEN (1ULL << 59) #define HCR_TWEDEL MAKE_64BIT_MASK(60, 4) =20 +#define HCRX_ENAS0 (1ULL << 0) +#define HCRX_ENALS (1ULL << 1) +#define HCRX_ENASR (1ULL << 2) +#define HCRX_FNXS (1ULL << 3) +#define HCRX_FGTNXS (1ULL << 4) +#define HCRX_SMPME (1ULL << 5) +#define HCRX_TALLINT (1ULL << 6) +#define HCRX_VINMI (1ULL << 7) +#define HCRX_VFNMI (1ULL << 8) +#define HCRX_CMOW (1ULL << 9) +#define HCRX_MCE2 (1ULL << 10) +#define HCRX_MSCEN (1ULL << 11) + #define HPFAR_NS (1ULL << 63) =20 #define SCR_NS (1U << 0) @@ -2310,6 +2324,7 @@ static inline bool arm_is_el2_enabled(CPUARMState *en= v) * Not included here is HCR_RW. */ uint64_t arm_hcr_el2_eff(CPUARMState *env); +uint64_t arm_hcrx_el2_eff(CPUARMState *env); =20 /* Return true if the specified exception level is running in AArch64 stat= e. */ static inline bool arm_el_is_aa64(CPUARMState *env, int el) @@ -3931,6 +3946,11 @@ static inline bool isar_feature_aa64_ats1e1(const AR= MISARegisters *id) return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, PAN) >=3D 2; } =20 +static inline bool isar_feature_aa64_hcx(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr1, ID_AA64MMFR1, HCX) !=3D 0; +} + static inline bool isar_feature_aa64_uao(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, UAO) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 04427e073f..4ab1dcf2ef 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -910,6 +910,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HCX, 1); /* FEAT_HCX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; diff --git a/target/arm/helper.c b/target/arm/helper.c index 432bd81919..93ab552346 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5278,6 +5278,52 @@ uint64_t arm_hcr_el2_eff(CPUARMState *env) return ret; } =20 +static void hcrx_write(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value) +{ + uint64_t valid_mask =3D 0; + + /* No features adding bits to HCRX are implemented. */ + + /* Clear RES0 bits. */ + env->cp15.hcrx_el2 =3D value & valid_mask; +} + +static CPAccessResult access_hxen(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + if (arm_current_el(env) < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_HXEN)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo hcrx_el2_reginfo =3D { + .name =3D "HCRX_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 2, + .access =3D PL2_RW, .writefn =3D hcrx_write, .accessfn =3D access_hxen, + .fieldoffset =3D offsetof(CPUARMState, cp15.hcrx_el2), +}; + +/* Return the effective value of HCRX_EL2. */ +uint64_t arm_hcrx_el2_eff(CPUARMState *env) +{ + /* + * The bits in this register behave as 0 for all purposes other than + * direct reads of the register if: + * - EL2 is not enabled in the current security state, + * - SCR_EL3.HXEn is 0. + */ + if (!arm_is_el2_enabled(env) + || (arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_HXEN))) { + return 0; + } + return env->cp15.hcrx_el2; +} + static void cptr_el2_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { @@ -8384,6 +8430,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, zcr_reginfo); } =20 + if (cpu_isar_feature(aa64_hcx, cpu)) { + define_one_arm_cp_reg(cpu, &hcrx_el2_reginfo); + } + #ifdef TARGET_AARCH64 if (cpu_isar_feature(aa64_pauth, cpu)) { define_arm_cp_regs(cpu, pauth_reginfo); --=20 2.34.1 From nobody Tue May 14 18:41:44 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652141281; cv=none; d=zohomail.com; s=zohoarc; b=iz2WyB1RpcKFj7yVxBdCNfNlxKN3i12Ns5PH6zBaKcKT9REe2HdFrevEybXgNHXGW4tOmNXrnmBpfHsNX0Jx3fKWb/JI6uRGMm75b6mt6CvcsizbvOLGEh8hIrhqGemnGHxDTfPwDyEIpHWx3qdaBDIBNa090yUSTORxbaLcajA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652141281; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=nZfmKi5wEe9aGuUVbmC8o559hWcefbU875G5kJZujtA=; b=UHCYTlDz0N2MCSvOmAQrEfwXZw9emUyYtmziNIIp483OSpeQ7+bQkaDw52KbXldDyyEcjvBnhI8k5F6SzvyHERuuWa1ynFDl/BbQL0E15bH7HJbjCeo3K6IZDrNdeNZrSZgSZxI6N6rXM1yXo4E1rpW0wHOSO/XLiOR0iv7XkDs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16521412815215.828713043316384; Mon, 9 May 2022 17:08:01 -0700 (PDT) Received: from localhost ([::1]:54464 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1noDQ0-0008Nj-Bl for importer@patchew.org; Mon, 09 May 2022 20:08:00 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50990) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1noDMh-00063m-U2 for qemu-devel@nongnu.org; Mon, 09 May 2022 20:04:35 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:44957) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1noDMd-0005BA-W3 for qemu-devel@nongnu.org; Mon, 09 May 2022 20:04:35 -0400 Received: by mail-pf1-x434.google.com with SMTP id x52so13558051pfu.11 for ; Mon, 09 May 2022 17:04:31 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id x71-20020a63864a000000b003c15f7f2914sm8983691pgd.24.2022.05.09.17.04.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 17:04:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=nZfmKi5wEe9aGuUVbmC8o559hWcefbU875G5kJZujtA=; b=KTP54plnrVl9Yc34Bz9V2NPiV9QTCHfaAy4sovgNiE/qSnWI71m799byjVibSrFu4t Dn5cykA4j1JGpDMlJKtBwWJG/ThsU6OFXiy07Hf/Y5uDfObqcRYNU/oe5KIZGPQqjMA1 xo1FoiSjOhEVWiOFKAfKfjFLzjm6xqjMNwILlAaPFqy+KREbtlJxG8Fzkrhy51d2pmOW zaZG6UsG0K0/Xjg/A4Dq0mNO1zjPqM44wpm1RcFkFXZjLtgvMLdGkxJ6eCP9yvC4+DRj mfjpiXukozWBMQDpEPJkj7SghdE13X/BfKIdzg21xGdvIfb6nmhv7xu1ZNqC5ZyxzfD9 PI2w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=nZfmKi5wEe9aGuUVbmC8o559hWcefbU875G5kJZujtA=; b=rteDegZejYT674FE8sylRdpCllEBdCNNXELT1J2rgji0m0i9R6BPPMJmfvAvc+yST/ xnXqj321hMKKNuoqefa2cvC+DP/NRJGIkhlc/n0QdO9vSAHMpJrtnDmGgFI/2ClgjcB6 tBya8VtabDab72Rf3oSyTnhzJd/nSkrlp5/m1uqd5+w7nkJSntDRXM9PFmNNM8lc8fMp Kzi5rDsSzyAwSlI7k/aGywkrtqCy/+qeEXL7pG6v5h8JxTqzsVPQyIbzlXse8IXWtRI/ q2ViACdEgG5+KWTlScXiJPoJiAd86NHr4gEstK+WrlVWHpCZS3m05g4jMzzDnsKpRkg+ fsLw== X-Gm-Message-State: AOAM531PPyHN5KWVg5t9Uz1FmTSaeWDtfwg9u7sYR23IMF77GNQfl1Rb UAPu61HHoV+zcQzFf9k473RhVibOcw5dsQ== X-Google-Smtp-Source: ABdhPJweSTHwwc9dWtLwW/Y9wbnHXFADkBEnxGHikrLP+AA1bjoBqXvhDF6bI2ffPOUO8R3WFAu7Kw== X-Received: by 2002:a05:6a00:238f:b0:4f6:b09a:4c63 with SMTP id f15-20020a056a00238f00b004f6b09a4c63mr17816946pfc.35.1652141070519; Mon, 09 May 2022 17:04:30 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org Subject: [PATCH 2/2] target/arm: Use FIELD definitions for CPACR, CPTR_ELx Date: Mon, 9 May 2022 17:04:26 -0700 Message-Id: <20220510000426.45797-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220510000426.45797-1-richard.henderson@linaro.org> References: <20220510000426.45797-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652141282404100001 Content-Type: text/plain; charset="utf-8" We had a few CPTR_* bits defined, but missed quite a few. Complete all of the fields up to ARMv9.2. Use FIELD_EX64 instead of manual extract32. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.h | 44 +++++++++++++++++++++++++++++++----- hw/arm/boot.c | 2 +- target/arm/cpu.c | 11 ++++++--- target/arm/helper.c | 54 ++++++++++++++++++++++----------------------- 4 files changed, 75 insertions(+), 36 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index b35b117fe7..c44acd8b84 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -1259,11 +1259,45 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_SPINTMASK (1ULL << 62) /* FEAT_NMI */ #define SCTLR_TIDCP (1ULL << 63) /* FEAT_TIDCP1 */ =20 -#define CPTR_TCPAC (1U << 31) -#define CPTR_TTA (1U << 20) -#define CPTR_TFP (1U << 10) -#define CPTR_TZ (1U << 8) /* CPTR_EL2 */ -#define CPTR_EZ (1U << 8) /* CPTR_EL3 */ +/* Bit definitions for CPACR (AArch32 only) */ +FIELD(CPACR, CP10, 20, 2) +FIELD(CPACR, CP11, 22, 2) +FIELD(CPACR, TRCDIS, 28, 1) /* matches CPACR_EL1.TTA */ +FIELD(CPACR, D32DIS, 31, 1) /* up to v7; RAZ in v8 */ +FIELD(CPACR, ASEDIS, 31, 1) + +/* Bit definitions for CPACR_EL1 (AArch64 only) */ +FIELD(CPACR_EL1, ZEN, 16, 2) +FIELD(CPACR_EL1, FPEN, 20, 2) +FIELD(CPACR_EL1, SMEN, 24, 2) +FIELD(CPACR_EL1, TTA, 28, 1) /* matches CPACR.TRCDIS */ + +/* Bit definitions for HCPTR (AArch32 only) */ +FIELD(HCPTR, TCP10, 10, 1) +FIELD(HCPTR, TCP11, 11, 1) +FIELD(HCPTR, TSAE, 15, 1) +FIELD(HCPTR, TTA, 20, 1) +FIELD(HCPTR, TAM, 30, 1) /* matches CPTR_EL2.TAM */ +FIELD(HCPTR, TCPAC, 31, 1) /* matches CPTR_EL2.TCPAC */ + +/* Bit definitions for CPTR_EL2 (AArch64 only) */ +FIELD(CPTR_EL2, TZ, 8, 1) /* !E2H */ +FIELD(CPTR_EL2, TFP, 10, 1) /* !E2H, matches HCPTR.TCP10 */ +FIELD(CPTR_EL2, TSM, 12, 1) /* !E2H */ +FIELD(CPTR_EL2, ZEN, 16, 2) /* E2H */ +FIELD(CPTR_EL2, FPEN, 20, 2) /* E2H */ +FIELD(CPTR_EL2, SMEN, 24, 2) /* E2H */ +FIELD(CPTR_EL2, TTA, 28, 1) +FIELD(CPTR_EL2, TAM, 30, 1) /* matches HCPTR.TAM */ +FIELD(CPTR_EL2, TCPAC, 31, 1) /* matches HCPTR.TCPAC */ + +/* Bit definitions for CPTR_EL3 (AArch64 only) */ +FIELD(CPTR_EL3, EZ, 8, 1) +FIELD(CPTR_EL3, TFP, 10, 1) +FIELD(CPTR_EL3, ESM, 12, 1) +FIELD(CPTR_EL3, TTA, 20, 1) +FIELD(CPTR_EL3, TAM, 30, 1) +FIELD(CPTR_EL3, TCPAC, 31, 1) =20 #define MDCR_EPMAD (1U << 21) #define MDCR_EDAD (1U << 20) diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a47f38dfc9..a8de33fd64 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -761,7 +761,7 @@ static void do_cpu_reset(void *opaque) env->cp15.scr_el3 |=3D SCR_ATA; } if (cpu_isar_feature(aa64_sve, cpu)) { - env->cp15.cptr_el[3] |=3D CPTR_EZ; + env->cp15.cptr_el[3] |=3D R_CPTR_EL3_EZ_MASK; } /* AArch64 kernels never boot in secure mode */ assert(!info->secure_boot); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 029f644768..d2bd74c2ed 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -201,9 +201,11 @@ static void arm_cpu_reset(DeviceState *dev) /* Trap on btype=3D3 for PACIxSP. */ env->cp15.sctlr_el[1] |=3D SCTLR_BT0; /* and to the FP/Neon instructions */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, FPEN, 3); /* and to the SVE instructions */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 16, 2, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR_EL1, ZEN, 3); /* with reasonable vector length */ if (cpu_isar_feature(aa64_sve, cpu)) { env->vfp.zcr_el[1] =3D @@ -252,7 +254,10 @@ static void arm_cpu_reset(DeviceState *dev) } else { #if defined(CONFIG_USER_ONLY) /* Userspace expects access to cp10 and cp11 for FP/Neon */ - env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 4, 0xf); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR, CP10, 3); + env->cp15.cpacr_el1 =3D FIELD_DP64(env->cp15.cpacr_el1, + CPACR, CP11, 3); #endif } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index 93ab552346..5fd64b742a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -767,11 +767,14 @@ static void cpacr_write(CPUARMState *env, const ARMCP= RegInfo *ri, */ if (cpu_isar_feature(aa32_vfp_simd, env_archcpu(env))) { /* VFP coprocessor: cp10 & cp11 [23:20] */ - mask |=3D (1 << 31) | (1 << 30) | (0xf << 20); + mask |=3D R_CPACR_ASEDIS_MASK | + R_CPACR_D32DIS_MASK | + R_CPACR_CP11_MASK | + R_CPACR_CP10_MASK; =20 if (!arm_feature(env, ARM_FEATURE_NEON)) { /* ASEDIS [31] bit is RAO/WI */ - value |=3D (1 << 31); + value |=3D R_CPACR_ASEDIS_MASK; } =20 /* VFPv3 and upwards with NEON implement 32 double precision @@ -779,7 +782,7 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (!cpu_isar_feature(aa32_simd_r32, env_archcpu(env))) { /* D32DIS [30] is RAO/WI if D16-31 are not implemented. */ - value |=3D (1 << 30); + value |=3D R_CPACR_D32DIS_MASK; } } value &=3D mask; @@ -791,8 +794,8 @@ static void cpacr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); - value |=3D env->cp15.cpacr_el1 & (0xf << 20); + mask =3D R_CPACR_CP11_MASK | R_CPACR_CP10_MASK; + value =3D (value & ~mask) | (env->cp15.cpacr_el1 & mask); } =20 env->cp15.cpacr_el1 =3D value; @@ -808,7 +811,7 @@ static uint64_t cpacr_read(CPUARMState *env, const ARMC= PRegInfo *ri) =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0xf << 20); + value =3D ~(R_CPACR_CP11_MASK | R_CPACR_CP10_MASK); } return value; } @@ -828,11 +831,11 @@ static CPAccessResult cpacr_access(CPUARMState *env, = const ARMCPRegInfo *ri, if (arm_feature(env, ARM_FEATURE_V8)) { /* Check if CPACR accesses are to be trapped to EL2 */ if (arm_current_el(env) =3D=3D 1 && arm_is_el2_enabled(env) && - (env->cp15.cptr_el[2] & CPTR_TCPAC)) { + FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TCPAC)) { return CP_ACCESS_TRAP_EL2; /* Check if CPACR accesses are to be trapped to EL3 */ } else if (arm_current_el(env) < 3 && - (env->cp15.cptr_el[3] & CPTR_TCPAC)) { + FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { return CP_ACCESS_TRAP_EL3; } } @@ -844,7 +847,8 @@ static CPAccessResult cptr_access(CPUARMState *env, con= st ARMCPRegInfo *ri, bool isread) { /* Check if CPTR accesses are set to trap to EL3 */ - if (arm_current_el(env) =3D=3D 2 && (env->cp15.cptr_el[3] & CPTR_TCPAC= )) { + if (arm_current_el(env) =3D=3D 2 && + FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TCPAC)) { return CP_ACCESS_TRAP_EL3; } =20 @@ -5333,8 +5337,8 @@ static void cptr_el2_write(CPUARMState *env, const AR= MCPRegInfo *ri, */ if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value &=3D ~(0x3 << 10); - value |=3D env->cp15.cptr_el[2] & (0x3 << 10); + uint64_t mask =3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; + value =3D (value & ~mask) | (env->cp15.cptr_el[2] & mask); } env->cp15.cptr_el[2] =3D value; } @@ -5349,7 +5353,7 @@ static uint64_t cptr_el2_read(CPUARMState *env, const= ARMCPRegInfo *ri) =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_el_is_aa64(env, 3) && !arm_is_secure(env) && !extract32(env->cp15.nsacr, 10, 1)) { - value |=3D 0x3 << 10; + value |=3D R_HCPTR_TCP11_MASK | R_HCPTR_TCP10_MASK; } return value; } @@ -6144,8 +6148,7 @@ int sve_exception_el(CPUARMState *env, int el) uint64_t hcr_el2 =3D arm_hcr_el2_eff(env); =20 if (el <=3D 1 && (hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_T= GE)) { - /* Check CPACR.ZEN. */ - switch (extract32(env->cp15.cpacr_el1, 16, 2)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, ZEN)) { case 1: if (el !=3D 0) { break; @@ -6158,7 +6161,7 @@ int sve_exception_el(CPUARMState *env, int el) } =20 /* Check CPACR.FPEN. */ - switch (extract32(env->cp15.cpacr_el1, 20, 2)) { + switch (FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN)) { case 1: if (el !=3D 0) { break; @@ -6175,8 +6178,7 @@ int sve_exception_el(CPUARMState *env, int el) */ if (el <=3D 2) { if (hcr_el2 & HCR_E2H) { - /* Check CPTR_EL2.ZEN. */ - switch (extract32(env->cp15.cptr_el[2], 16, 2)) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, ZEN)) { case 1: if (el !=3D 0 || !(hcr_el2 & HCR_TGE)) { break; @@ -6187,8 +6189,7 @@ int sve_exception_el(CPUARMState *env, int el) return 2; } =20 - /* Check CPTR_EL2.FPEN. */ - switch (extract32(env->cp15.cptr_el[2], 20, 2)) { + switch (FIELD_EX32(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { case 1: if (el =3D=3D 2 || !(hcr_el2 & HCR_TGE)) { break; @@ -6199,10 +6200,10 @@ int sve_exception_el(CPUARMState *env, int el) return 0; } } else if (arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TZ) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TZ)) { return 2; } - if (env->cp15.cptr_el[2] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { return 0; } } @@ -6210,7 +6211,7 @@ int sve_exception_el(CPUARMState *env, int el) =20 /* CPTR_EL3. Since EZ is negative we must check for EL3. */ if (arm_feature(env, ARM_FEATURE_EL3) - && !(env->cp15.cptr_el[3] & CPTR_EZ)) { + && !FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, EZ)) { return 3; } #endif @@ -13266,7 +13267,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) * This register is ignored if E2H+TGE are both set. */ if ((hcr_el2 & (HCR_E2H | HCR_TGE)) !=3D (HCR_E2H | HCR_TGE)) { - int fpen =3D extract32(env->cp15.cpacr_el1, 20, 2); + int fpen =3D FIELD_EX64(env->cp15.cpacr_el1, CPACR_EL1, FPEN); =20 switch (fpen) { case 0: @@ -13312,8 +13313,7 @@ int fp_exception_el(CPUARMState *env, int cur_el) */ if (cur_el <=3D 2) { if (hcr_el2 & HCR_E2H) { - /* Check CPTR_EL2.FPEN. */ - switch (extract32(env->cp15.cptr_el[2], 20, 2)) { + switch (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, FPEN)) { case 1: if (cur_el !=3D 0 || !(hcr_el2 & HCR_TGE)) { break; @@ -13324,14 +13324,14 @@ int fp_exception_el(CPUARMState *env, int cur_el) return 2; } } else if (arm_is_el2_enabled(env)) { - if (env->cp15.cptr_el[2] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[2], CPTR_EL2, TFP)) { return 2; } } } =20 /* CPTR_EL3 : present in v8 */ - if (env->cp15.cptr_el[3] & CPTR_TFP) { + if (FIELD_EX64(env->cp15.cptr_el[3], CPTR_EL3, TFP)) { /* Trap all FP ops to EL3 */ return 3; } --=20 2.34.1