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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c
Date: Mon, 9 May 2022 12:58:22 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Previously we were defining some of these in user-only mode,
but none of them are accessible from user-only, therefore
define them only in system mode.
This will shortly be used from cpu_tcg.c also.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-6-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/internals.h | 6 ++++
target/arm/cpu64.c | 64 +++---------------------------------------
target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++
3 files changed, 69 insertions(+), 60 deletions(-)
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 255833479d4..343b465d516 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1307,4 +1307,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteA=
rray *buf, int reg);
int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg);
#endif
=20
+#ifdef CONFIG_USER_ONLY
+static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { }
+#else
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu);
+#endif
+
#endif
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index c841d55d0e9..33a0a719003 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -34,65 +34,9 @@
#include "hvf_arm.h"
#include "qapi/visitor.h"
#include "hw/qdev-properties.h"
-#include "cpregs.h"
+#include "internals.h"
=20
=20
-#ifndef CONFIG_USER_ONLY
-static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *=
ri)
-{
- ARMCPU *cpu =3D env_archcpu(env);
-
- /* Number of cores is in [25:24]; otherwise we RAZ */
- return (cpu->core_count - 1) << 24;
-}
-#endif
-
-static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D {
-#ifndef CONFIG_USER_ONLY
- { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read,
- .writefn =3D arm_cp_write_ignore },
- { .name =3D "L2CTLR",
- .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read,
- .writefn =3D arm_cp_write_ignore },
-#endif
- { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "L2ECTLR",
- .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CPUACTLR",
- .cp =3D 15, .opc1 =3D 0, .crm =3D 15,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
- { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CPUECTLR",
- .cp =3D 15, .opc1 =3D 1, .crm =3D 15,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
- { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CPUMERRSR",
- .cp =3D 15, .opc1 =3D 2, .crm =3D 15,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
- { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "L2MERRSR",
- .cp =3D 15, .opc1 =3D 3, .crm =3D 15,
- .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
-};
-
static void aarch64_a57_initfn(Object *obj)
{
ARMCPU *cpu =3D ARM_CPU(obj);
@@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj)
cpu->gic_num_lrs =3D 4;
cpu->gic_vpribits =3D 5;
cpu->gic_vprebits =3D 5;
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
=20
static void aarch64_a53_initfn(Object *obj)
@@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj)
cpu->gic_num_lrs =3D 4;
cpu->gic_vpribits =3D 5;
cpu->gic_vprebits =3D 5;
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
=20
static void aarch64_a72_initfn(Object *obj)
@@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj)
cpu->gic_num_lrs =3D 4;
cpu->gic_vpribits =3D 5;
cpu->gic_vprebits =3D 5;
- define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+ define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
=20
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index 9338088b226..d078f06931c 100644
--- a/target/arm/cpu_tcg.c
+++ b/target/arm/cpu_tcg.c
@@ -20,6 +20,65 @@
#endif
#include "cpregs.h"
=20
+#ifndef CONFIG_USER_ONLY
+static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
+{
+ ARMCPU *cpu =3D env_archcpu(env);
+
+ /* Number of cores is in [25:24]; otherwise we RAZ */
+ return (cpu->core_count - 1) << 24;
+}
+
+static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D {
+ { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2,
+ .access =3D PL1_RW, .readfn =3D l2ctlr_read,
+ .writefn =3D arm_cp_write_ignore },
+ { .name =3D "L2CTLR",
+ .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2,
+ .access =3D PL1_RW, .readfn =3D l2ctlr_read,
+ .writefn =3D arm_cp_write_ignore },
+ { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "L2ECTLR",
+ .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "CPUACTLR",
+ .cp =3D 15, .opc1 =3D 0, .crm =3D 15,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
+ { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "CPUECTLR",
+ .cp =3D 15, .opc1 =3D 1, .crm =3D 15,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
+ { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "CPUMERRSR",
+ .cp =3D 15, .opc1 =3D 2, .crm =3D 15,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
+ { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
+ { .name =3D "L2MERRSR",
+ .cp =3D 15, .opc1 =3D 3, .crm =3D 15,
+ .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval=
ue =3D 0 },
+};
+
+void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu)
+{
+ define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo);
+}
+#endif /* !CONFIG_USER_ONLY */
+
/* CPU models. These are not needed for the AArch64 linux-user build. */
#if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
=20
--=20
2.25.1