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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2
Date: Mon, 9 May 2022 12:58:21 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
This register is present for either VHE or Debugv8p2.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-5-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 15 +++++++++++----
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 72d05070f02..7b31c719806 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D {
.access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
};
=20
+static const ARMCPRegInfo contextidr_el2 =3D {
+ .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1,
+ .access =3D PL2_RW,
+ .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2])
+};
+
static const ARMCPRegInfo vhe_reginfo[] =3D {
- { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1,
- .access =3D PL2_RW,
- .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) },
{ .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1,
.access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write,
@@ -8215,6 +8218,10 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_one_arm_cp_reg(cpu, &ssbs_reginfo);
}
=20
+ if (cpu_isar_feature(aa64_vh, cpu) ||
+ cpu_isar_feature(aa64_debugv8p2, cpu)) {
+ define_one_arm_cp_reg(cpu, &contextidr_el2);
+ }
if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu=
)) {
define_arm_cp_regs(cpu, vhe_reginfo);
}
--=20
2.25.1