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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 04/32] target/arm: Merge zcr reginfo
Date: Mon, 9 May 2022 12:58:20 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Drop zcr_no_el2_reginfo and merge the 3 registers into one array,
now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped
while registering.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-4-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 55 ++++++++++++++-------------------------------
1 file changed, 17 insertions(+), 38 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index ea2788b3d53..72d05070f02 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6122,35 +6122,22 @@ static void zcr_write(CPUARMState *env, const ARMCP=
RegInfo *ri,
}
}
=20
-static const ARMCPRegInfo zcr_el1_reginfo =3D {
- .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL1_RW, .type =3D ARM_CP_SVE,
- .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]),
- .writefn =3D zcr_write, .raw_writefn =3D raw_write
-};
-
-static const ARMCPRegInfo zcr_el2_reginfo =3D {
- .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_SVE,
- .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]),
- .writefn =3D zcr_write, .raw_writefn =3D raw_write
-};
-
-static const ARMCPRegInfo zcr_no_el2_reginfo =3D {
- .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_SVE,
- .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore
-};
-
-static const ARMCPRegInfo zcr_el3_reginfo =3D {
- .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL3_RW, .type =3D ARM_CP_SVE,
- .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]),
- .writefn =3D zcr_write, .raw_writefn =3D raw_write
+static const ARMCPRegInfo zcr_reginfo[] =3D {
+ { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
+ .access =3D PL1_RW, .type =3D ARM_CP_SVE,
+ .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]),
+ .writefn =3D zcr_write, .raw_writefn =3D raw_write },
+ { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
+ .access =3D PL2_RW, .type =3D ARM_CP_SVE,
+ .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]),
+ .writefn =3D zcr_write, .raw_writefn =3D raw_write },
+ { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64,
+ .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0,
+ .access =3D PL3_RW, .type =3D ARM_CP_SVE,
+ .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]),
+ .writefn =3D zcr_write, .raw_writefn =3D raw_write },
};
=20
void hw_watchpoint_update(ARMCPU *cpu, int n)
@@ -8233,15 +8220,7 @@ void register_cp_regs_for_features(ARMCPU *cpu)
}
=20
if (cpu_isar_feature(aa64_sve, cpu)) {
- define_one_arm_cp_reg(cpu, &zcr_el1_reginfo);
- if (arm_feature(env, ARM_FEATURE_EL2)) {
- define_one_arm_cp_reg(cpu, &zcr_el2_reginfo);
- } else {
- define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo);
- }
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- define_one_arm_cp_reg(cpu, &zcr_el3_reginfo);
- }
+ define_arm_cp_regs(cpu, zcr_reginfo);
}
=20
#ifdef TARGET_AARCH64
--=20
2.25.1