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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks
Date: Mon, 9 May 2022 12:58:19 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local
vpidr_regs definition, and rely on the squashing to ARM_CP_CONST
while registering for v8.
This is a behavior change for v7 cpus with Security Extensions and
without Virtualization Extensions, in that the virtualization cpregs
are now correctly not present. This would be a migration compatibility
break, except that we have an existing bug in which migration of 32-bit
cpus with Security Extensions enabled does not work.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-3-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 158 ++++----------------------------------------
1 file changed, 13 insertions(+), 145 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 9ab8b65e7bc..ea2788b3d53 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D {
.fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) },
};
=20
-/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */
-static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D {
- { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL2_RW,
- .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore },
- { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL2_RW,
- .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL2_RW,
- .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32,
- .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32,
- .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2,
- .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns,
- .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32,
- .cp =3D 15, .opc1 =3D 6, .crm =3D 2,
- .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns,
- .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 },
- { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2,
- .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14,
- .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14,
- .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST,
- .resetvalue =3D 0 },
- { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1,
- .access =3D PL2_RW, .accessfn =3D access_tda,
- .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4,
- .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns,
- .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0,
- .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
- { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32,
- .type =3D ARM_CP_CONST,
- .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2,
- .access =3D PL2_RW, .resetvalue =3D 0 },
-};
-
-/* Ditto, but for registers which exist in ARMv8 but not v7 */
-static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D {
- { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32,
- .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4,
- .access =3D PL2_RW,
- .type =3D ARM_CP_CONST, .resetvalue =3D 0 },
-};
-
static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_=
mask)
{
ARMCPU *cpu =3D env_archcpu(env);
@@ -7902,7 +7784,17 @@ void register_cp_regs_for_features(ARMCPU *cpu)
define_arm_cp_regs(cpu, v8_idregs);
define_arm_cp_regs(cpu, v8_cp_reginfo);
}
- if (arm_feature(env, ARM_FEATURE_EL2)) {
+
+ /*
+ * Register the base EL2 cpregs.
+ * Pre v8, these registers are implemented only as part of the
+ * Virtualization Extensions (EL2 present). Beginning with v8,
+ * if EL2 is missing but EL3 is enabled, mostly these become
+ * RES0 from EL3, with some specific exceptions.
+ */
+ if (arm_feature(env, ARM_FEATURE_EL2)
+ || (arm_feature(env, ARM_FEATURE_EL3)
+ && arm_feature(env, ARM_FEATURE_V8))) {
uint64_t vmpidr_def =3D mpidr_read_val(env);
ARMCPRegInfo vpidr_regs[] =3D {
{ .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32,
@@ -7946,33 +7838,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
};
define_one_arm_cp_reg(cpu, &rvbar);
}
- } else {
- /* If EL2 is missing but higher ELs are enabled, we need to
- * register the no_el2 reginfos.
- */
- if (arm_feature(env, ARM_FEATURE_EL3)) {
- /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value
- * of MIDR_EL1 and MPIDR_EL1.
- */
- ARMCPRegInfo vpidr_regs[] =3D {
- { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =
=3D 0,
- .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns,
- .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr,
- .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) },
- { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH,
- .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =
=3D 5,
- .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns,
- .type =3D ARM_CP_NO_RAW,
- .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read=
},
- };
- define_arm_cp_regs(cpu, vpidr_regs);
- define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo);
- if (arm_feature(env, ARM_FEATURE_V8)) {
- define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo);
- }
- }
}
+
+ /* Register the base EL3 cpregs. */
if (arm_feature(env, ARM_FEATURE_EL3)) {
define_arm_cp_regs(cpu, el3_cp_reginfo);
ARMCPRegInfo el3_regs[] =3D {
--=20
2.25.1