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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 24/32] target/arm: Define cortex-a76
Date: Mon, 9 May 2022 12:58:40 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Enable the a76 for virt and sbsa board use.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220506180242.216785-24-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/virt.rst | 1 +
hw/arm/sbsa-ref.c | 1 +
hw/arm/virt.c | 1 +
target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++
4 files changed, 69 insertions(+)
diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst
index 5fe045cbf06..3e264d85af8 100644
--- a/docs/system/arm/virt.rst
+++ b/docs/system/arm/virt.rst
@@ -55,6 +55,7 @@ Supported guest CPU types:
- ``cortex-a53`` (64-bit)
- ``cortex-a57`` (64-bit)
- ``cortex-a72`` (64-bit)
+- ``cortex-a76`` (64-bit)
- ``a64fx`` (64-bit)
- ``host`` (with KVM only)
- ``max`` (same as ``host`` for KVM; best possible emulation with TCG)
diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c
index 23874019639..2ddde88f5eb 100644
--- a/hw/arm/sbsa-ref.c
+++ b/hw/arm/sbsa-ref.c
@@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] =3D {
static const char * const valid_cpus[] =3D {
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
+ ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("max"),
};
=20
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index f94278935f5..12bc2318ecb 100644
--- a/hw/arm/virt.c
+++ b/hw/arm/virt.c
@@ -202,6 +202,7 @@ static const char *valid_cpus[] =3D {
ARM_CPU_TYPE_NAME("cortex-a53"),
ARM_CPU_TYPE_NAME("cortex-a57"),
ARM_CPU_TYPE_NAME("cortex-a72"),
+ ARM_CPU_TYPE_NAME("cortex-a76"),
ARM_CPU_TYPE_NAME("a64fx"),
ARM_CPU_TYPE_NAME("host"),
ARM_CPU_TYPE_NAME("max"),
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index f55121060dc..adfe6b26be7 100644
--- a/target/arm/cpu64.c
+++ b/target/arm/cpu64.c
@@ -194,6 +194,71 @@ static void aarch64_a72_initfn(Object *obj)
define_cortex_a72_a57_a53_cp_reginfo(cpu);
}
=20
+static void aarch64_a76_initfn(Object *obj)
+{
+ ARMCPU *cpu =3D ARM_CPU(obj);
+
+ cpu->dtb_compatible =3D "arm,cortex-a76";
+ set_feature(&cpu->env, ARM_FEATURE_V8);
+ set_feature(&cpu->env, ARM_FEATURE_NEON);
+ set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
+ set_feature(&cpu->env, ARM_FEATURE_AARCH64);
+ set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
+ set_feature(&cpu->env, ARM_FEATURE_EL2);
+ set_feature(&cpu->env, ARM_FEATURE_EL3);
+ set_feature(&cpu->env, ARM_FEATURE_PMU);
+
+ /* Ordered by B2.4 AArch64 registers by functional group */
+ cpu->clidr =3D 0x82000023;
+ cpu->ctr =3D 0x8444C004;
+ cpu->dcz_blocksize =3D 4;
+ cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull;
+ cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull;
+ cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull;
+ cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull;
+ cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull;
+ cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull;
+ cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat=
er */
+ cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull;
+ cpu->id_afr0 =3D 0x00000000;
+ cpu->isar.id_dfr0 =3D 0x04010088;
+ cpu->isar.id_isar0 =3D 0x02101110;
+ cpu->isar.id_isar1 =3D 0x13112111;
+ cpu->isar.id_isar2 =3D 0x21232042;
+ cpu->isar.id_isar3 =3D 0x01112131;
+ cpu->isar.id_isar4 =3D 0x00010142;
+ cpu->isar.id_isar5 =3D 0x01011121;
+ cpu->isar.id_isar6 =3D 0x00000010;
+ cpu->isar.id_mmfr0 =3D 0x10201105;
+ cpu->isar.id_mmfr1 =3D 0x40000000;
+ cpu->isar.id_mmfr2 =3D 0x01260000;
+ cpu->isar.id_mmfr3 =3D 0x02122211;
+ cpu->isar.id_mmfr4 =3D 0x00021110;
+ cpu->isar.id_pfr0 =3D 0x10010131;
+ cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */
+ cpu->isar.id_pfr2 =3D 0x00000011;
+ cpu->midr =3D 0x414fd0b1; /* r4p1 */
+ cpu->revidr =3D 0;
+
+ /* From B2.18 CCSIDR_EL1 */
+ cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */
+ cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */
+ cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */
+
+ /* From B2.93 SCTLR_EL3 */
+ cpu->reset_sctlr =3D 0x30c50838;
+
+ /* From B4.23 ICH_VTR_EL2 */
+ cpu->gic_num_lrs =3D 4;
+ cpu->gic_vpribits =3D 5;
+ cpu->gic_vprebits =3D 5;
+
+ /* From B5.1 AdvSIMD AArch64 register summary */
+ cpu->isar.mvfr0 =3D 0x10110222;
+ cpu->isar.mvfr1 =3D 0x13211111;
+ cpu->isar.mvfr2 =3D 0x00000043;
+}
+
void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp)
{
/*
@@ -881,6 +946,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D {
{ .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn },
{ .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn },
{ .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn },
+ { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn },
{ .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn },
{ .name =3D "max", .initfn =3D aarch64_max_initfn },
#if defined(CONFIG_KVM) || defined(CONFIG_HVF)
--=20
2.25.1