From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652097775; cv=none; d=zohomail.com; s=zohoarc; b=J+Jbq2GlUZR7UvHJys2eCe0brcGRnL+rPfC7TAMP8n/lKg2GWHrg+E8JA7qTdmKfZF/qUGQQvMpq3Lv302LT1XfVZRj512BWG5SJw6/o+IAu8FtxCoqLOD/KZZxgCx9VlPYBpDNgUApA/ByW2p7pUE/24JlojLOAqXCDFn90zjQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652097775; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=HECDO2g5fuR9qiRk+IIoBmUOKs2yPZa4jqvWajfBo7U=; b=gc4IBB0TNOIuhz9HdMGNs/Le4s0QnwVIYlbzL0vHzaH/gLMkSzPOJ++CX/TRzdMnj9jdp3+kehI1xroZRv95GJZXWGQWA1XzxfppMd4i3ZtfYkqYTVxCIg6Hgegm07YRYQ21DCjHIkOErrnqLWDPHZcXmy4MALzMm24CZ/SzWrs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652097775929425.69207619500173; Mon, 9 May 2022 05:02:55 -0700 (PDT) Received: from localhost ([::1]:50398 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no26I-0001ch-1e for importer@patchew.org; Mon, 09 May 2022 08:02:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49600) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22Q-00070k-Jt for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:54 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:37625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22O-0001Ga-Vc for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:54 -0400 Received: by mail-wr1-x42d.google.com with SMTP id t6so19116578wra.4 for ; Mon, 09 May 2022 04:58:52 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=HECDO2g5fuR9qiRk+IIoBmUOKs2yPZa4jqvWajfBo7U=; b=n3/OLf9tX4IaEs7CFqVxQk2s5TKdjTzg34rTZOGapIeW+c7e+/mJWNHgp1beHWA/Yk CcQE/PAfXr6rJeMWjBtbHjfJuV8tAc/Vj9C14btrWUBy8OrDpuWbevXSxOxDGASrlI0c DtqE6HjVs2um+exqe6PFGNTTwwJQgCX8Qfj2h2YipiLd7VoE3rwAtk4+/fmoGbuOtUIA dpnLhhOtmuuyYc5oNZN/cW6lamUPtsSxQeKSGPh4Twr2oOsRBeodpjPxIsuNsMiYMdLp hhyuzbFC1zhLU6dIfVI2eqX6XPLfb436V7ZLyz9bGJgg/7iY8ooMXsUkZ6ORkuEDbgOD cYCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=HECDO2g5fuR9qiRk+IIoBmUOKs2yPZa4jqvWajfBo7U=; b=X4l4WladBHlp+qoeuZTY+Rk/AQ1ntp/Y8sBDAPfDfObgylTZtkEiA4M2qbkqmP/eDu YoZX0bjbS+Agn8fHjaH/yvCQhAQeiVd55B3KCQzCeKe4fNbk1mO4adHBZnSQOPyo7A8M CdOes5KOS9N0RuKxpsw+LTBNPYjxU3EQEdfSxkIOzZA8vNtnZrKzukQPSezW6qtM0qr5 SeiYBJdvHZ+nLw+35/X97WvmsRef52nezFbDuJ4kfutj7CP8WKsnxHN0NWkM630NJmbs vEH4fkQE13AqrBNflRRY19F9zBKwKKI9Qi/UK651AhHECEBhhETCq4+xE3SBK3Zakwqf 3V1A== X-Gm-Message-State: AOAM531FOZwGXDWERX8f/3+QOuRr7uQfI2+GosVFIDl8xWd9JNTfHR7D YZR6kEwmAeWvDNZArRdmheKS8xirKpCjdg== X-Google-Smtp-Source: ABdhPJxcbCkmsCd5H31gTdGSTcSYCCbxWLbOTWQHPbI12IC743RVVmtQc9fqUOWEsTzbu/7dlYJsxQ== X-Received: by 2002:a05:6000:178d:b0:20c:b1fb:abe9 with SMTP id e13-20020a056000178d00b0020cb1fbabe9mr9440987wrg.452.1652097530837; Mon, 09 May 2022 04:58:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/32] MAINTAINERS/.mailmap: update email for Leif Lindholm Date: Mon, 9 May 2022 12:58:17 +0100 Message-Id: <20220509115848.3521805-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652097776572100001 From: Leif Lindholm NUVIA was acquired by Qualcomm in March 2021, but kept functioning on separate infrastructure for a transitional period. We've now switched over to contributing as Qualcomm Innovation Center (quicinc), so update my email address to reflect this. Signed-off-by: Leif Lindholm Message-id: 20220505113740.75565-1-quic_llindhol@quicinc.com Cc: Leif Lindholm Cc: Peter Maydell Reviewed-by: Philippe Mathieu-Daud=C3=A9 [Fixed commit message typo] Signed-off-by: Peter Maydell --- .mailmap | 3 ++- MAINTAINERS | 2 +- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.mailmap b/.mailmap index 2976a675ea5..8c326709cfa 100644 --- a/.mailmap +++ b/.mailmap @@ -62,7 +62,8 @@ Greg Kurz Huacai Chen Huacai Chen James Hogan -Leif Lindholm +Leif Lindholm +Leif Lindholm Radoslaw Biernacki Paul Burton Paul Burton diff --git a/MAINTAINERS b/MAINTAINERS index 662ec472467..42f67e2b930 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -889,7 +889,7 @@ F: include/hw/ssi/imx_spi.h SBSA-REF M: Radoslaw Biernacki M: Peter Maydell -R: Leif Lindholm +R: Leif Lindholm L: qemu-arm@nongnu.org S: Maintained F: hw/arm/sbsa-ref.c --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652097786; cv=none; d=zohomail.com; s=zohoarc; b=Q7/n60OjIdUaOZsd4YG5s7xxRjUSUrZKsIf1C9NTSm0BQr9YxSP1KWSi7ro+eJRBUCG+vImtokcHGl/AB/W4cf4Ls1sOzAdETS6Mzmk7P6uCldtO08/DBBeIhe8yrZb4d+bedZh5/vWrChfF7KveWtnkFr9BdE+6/GaTT8UUzkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652097786; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vS3vnqyqeVbTmMwpOiEpeAFu4aTlt8ymePUVlIPTNuA=; b=YL7PskdCJhfTy4b1OF5xYTjArNPLPik49Alr3bJ+s9t5MVRsj6MfUL0iWOUukWLdGYrLMgs+zv5mqEHlEr+0Q35CA6lGEQkvW7BGBbuvxzTXkcJdq3rjv/tNVo4Su+WnM8kaDsDr0+4XjRL/Jfe7ErIEkOvU7KURvv67ZguEsUE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652097786914937.2434407731156; Mon, 9 May 2022 05:03:06 -0700 (PDT) Received: from localhost ([::1]:50886 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no26T-0001xS-II for importer@patchew.org; Mon, 09 May 2022 08:03:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49670) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22T-00073w-1A for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:57 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22Q-0001Gn-D3 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:56 -0400 Received: by mail-wr1-x436.google.com with SMTP id e24so19108668wrc.9 for ; Mon, 09 May 2022 04:58:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vS3vnqyqeVbTmMwpOiEpeAFu4aTlt8ymePUVlIPTNuA=; b=PBzoCT6kke2+/PWr10clQtscft37He8oP/r/by+OI3W4YpHg7073bFUTvrnLFCxYuy 2X/Wr69Cg09HtgZB/nhDzhXAvBod6gxq9/WMeDNvigIMFv+Ko2mk2kAmYa0aWKUMQEiq E/IBZ4XnrrFcBEP29xVUrPogPN1Zm9AngYgb+SMviK7o9vnWqw3uziyaF3Do6n/f7gwk 0ZqCbhJYzeWHYBNuu5lKfGpfqfpWsMzgphCv2xZKBQ0kFqEHOscdAuZvz4As299MRPDw 1qAJp4rS6PsqTlKqcPg0unJpWq9ZCqqmkR6tla1jtMrfHxpjdi+FjpUKe0+dmVWpZqGP zVvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vS3vnqyqeVbTmMwpOiEpeAFu4aTlt8ymePUVlIPTNuA=; b=1BQU2C9w/84KNy/FHLo3aRcNh0RUwN7Qp+fphKU9UQathpehLyCm6bnLiTrxM3reuV cKJ5eUpiyCQjKpLB6+AvoUsj7jJGZwzhLwsUoOWHD6hF5AUsU/PRWbS1kA5yTHu6HgNI o66irAOABzSS8AJ1zPsxLYtsobtWEAYfDdfTd1XQz3jKsukOm3Q/1a9Mj1bE3LhuUf5Q QqOVd1Ahf8DH0PTuOuRyjL9gksd7H78VRcwPRH9ufFfrTOFV+4s3pgO/tui1N1/N3XAm Es7PQbcoEwZvgRtG9heN24SmwFsujHWNhHXMruNZ1T244JHA8MtFGG5CvqC3+4QfEtLY zwmw== X-Gm-Message-State: AOAM532/CkyuhJn+9D4Ey1JS8AFnQwTnIZ4FQdKhwyv+47Lmy03DxMeF QL+npPHBE6nDiLBq98OWyIEQJ7ZFPVxwKA== X-Google-Smtp-Source: ABdhPJwlA2ZpO6Uw0TcqJN1qUaaGbX8QXJJUXikM6hwbFx1ZRigvPU6OVfbuTs7iJ2utQYNPm+SVBA== X-Received: by 2002:a05:6000:2a5:b0:20c:520a:a12e with SMTP id l5-20020a05600002a500b0020c520aa12emr13088129wry.629.1652097531815; Mon, 09 May 2022 04:58:51 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/32] target/arm: Handle cpreg registration for missing EL Date: Mon, 9 May 2022 12:58:18 +0100 Message-Id: <20220509115848.3521805-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652097788434100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson More gracefully handle cpregs when EL2 and/or EL3 are missing. If the reg is entirely inaccessible, do not register it at all. If the reg is for EL2, and EL3 is present but EL2 is not, either discard, squash to res0, const, or keep unchanged. Per rule RJFFP, mark the 4 aarch32 hypervisor access registers with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. This will simplify cpreg registration for conditional arm features. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 11 +++ target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- 2 files changed, 133 insertions(+), 56 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 73984549d25..db03d6a7e13 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -102,6 +102,17 @@ enum { ARM_CP_SVE =3D 1 << 14, /* Flag: Do not expose in gdb sysreg xml. */ ARM_CP_NO_GDB =3D 1 << 15, + /* + * Flags: If EL3 but not EL2... + * - UNDEF: discard the cpreg, + * - KEEP: retain the cpreg as is, + * - C_NZ: set const on the cpreg, but retain resetvalue, + * - else: set const on the cpreg, zero resetvalue, aka RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + ARM_CP_EL3_NO_EL2_UNDEF =3D 1 << 16, + ARM_CP_EL3_NO_EL2_KEEP =3D 1 << 17, + ARM_CP_EL3_NO_EL2_C_NZ =3D 1 << 18, }; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index b4daf4f0761..9ab8b65e7bc 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5056,16 +5056,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_FPU, + .access =3D PL2_RW, + .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, @@ -5542,27 +5543,27 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D tlbimva_hyp_is_write }, { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2_write }, { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2_write }, { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2_write }, { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2is_write }, { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY /* Unlike the other EL2-related AT operations, these must @@ -5572,11 +5573,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se @@ -6076,7 +6079,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, + .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit * alias is DBGDCCINT. @@ -6892,11 +6895,11 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NOP }, { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, @@ -6906,19 +6909,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NOP }, { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2_write }, { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2_write }, { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, @@ -6973,11 +6976,11 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2is_write }, { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, @@ -6985,7 +6988,7 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .writefn =3D tlbi_aa64_alle1is_write }, { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, @@ -7905,21 +7908,24 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D cpu->midr, .type =3D ARM_CP_ALIAS, + .resetvalue =3D cpu->midr, + .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, .access =3D PL2_RW, .resetvalue =3D cpu->midr, + .type =3D ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D vmpidr_def, .type =3D ARM_CP_ALIAS, + .resetvalue =3D vmpidr_def, + .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vmpidr_el2)= }, { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, - .access =3D PL2_RW, - .resetvalue =3D vmpidr_def, + .access =3D PL2_RW, .resetvalue =3D vmpidr_def, + .type =3D ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, }; define_arm_cp_regs(cpu, vpidr_regs); @@ -8506,13 +8512,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, int crm, int opc1, int opc2, const char *name) { + CPUARMState *env =3D &cpu->env; uint32_t key; ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; - bool isbanked; size_t name_len; + bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -8547,6 +8554,32 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + make_const =3D false; + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? PL2_RW : PL1_RW); + if ((r->access & max_el) =3D=3D 0) { + return; + } + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8567,44 +8600,77 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, r2->opaque =3D opaque; } =20 - isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; - if (isbanked) { + if (make_const) { + /* This should not have been a very special register to begin. */ + int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); /* - * Register is banked (using both entries in array). - * Overwriting fieldoffset as the array is only used to define - * banked registers but later only fieldoffset is used. + * Set the special function to CONST, retaining the other flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; - } + r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; + /* + * Usually, these registers become RES0, but there are a few + * special cases like VPIDR_EL2 which have a constant non-zero + * value with writes ignored. + */ + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { + r2->resetvalue =3D 0; + } + /* + * ARM_CP_CONST has precedence, so removing the callbacks and + * offsets are not strictly necessary, but it is potentially + * less confusing to debug later. + */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->resetfn =3D NULL; + r2->fieldoffset =3D 0; + r2->bank_fieldoffsets[0] =3D 0; + r2->bank_fieldoffsets[1] =3D 0; + } else { + bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 - if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { /* - * If the register is banked then we don't need to migrate or - * reset the 32-bit instance in certain cases: - * - * 1) If the register has both 32-bit and 64-bit instances the= n we - * can count on the 64-bit instance taking care of the - * non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit version - * taking care of the secure bank. This requires that sepa= rate - * 32 and 64-bit definitions are provided. + * Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + } + if (state =3D=3D ARM_CP_STATE_AA32) { + if (isbanked) { + /* + * If the register is banked then we don't need to migrate= or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances + * then we can count on the 64-bit instance taking care + * of the non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit + * version taking care of the secure bank. This requir= es + * that separate 32 and 64-bit definitions are provided. + */ + if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { + r2->type |=3D ARM_CP_ALIAS; + } + } else if ((secstate !=3D r->secure) && !ns) { + /* + * The register is not banked so we only want to allow + * migration of the non-secure instance. + */ r2->type |=3D ARM_CP_ALIAS; } - } else if ((secstate !=3D r->secure) && !ns) { - /* - * The register is not banked so we only want to allow migrati= on - * of the non-secure instance. - */ - r2->type |=3D ARM_CP_ALIAS; - } =20 - if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); + if (HOST_BIG_ENDIAN && + r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); + } } } =20 @@ -8615,7 +8681,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r->type & ARM_CP_SPECIAL_MASK) { + if (r2->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098001; cv=none; d=zohomail.com; s=zohoarc; b=c2kQB1950PenhNHNkuPXEe+pnQQOjpIKAFUEpkz7WgnJl90nZ4eGlWDTVCqr3DzvfTHj8KsyPFdTigzCMFigVozZ3cb3YI6Lz5ObV421WT5V2nMo5E37B2ojHD16mcyMi9hOS59ZiX/k1ocAZhDRcBflIAFeCxp/7G5EVtO9Uao= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098001; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=AMHYpqYyVexl/KQxM32vgi111AbDDgBeiFSwyB6v1qY=; b=F9R4A/ErK5QdNcXKVrzZsHnfOQ1J1OGhnhHf6Lv/m8VWTpNsocO9SRFZbWbvCQeASZoIxejPSmUaItV/CBIh1PWdkaPkr7yLthALqki8QQqiV7hLzbwHKrjSbhFkMttkgPDgk5qh1K+iIZFKqGF9JnHV2fKtSkPp5hnvLnWOk0c= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098001369896.9830381705377; Mon, 9 May 2022 05:06:41 -0700 (PDT) Received: from localhost ([::1]:58946 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no29w-0007Uv-9S for importer@patchew.org; Mon, 09 May 2022 08:06:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49654) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22S-00071t-Cj for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:56 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22Q-0001Gm-Ak for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:56 -0400 Received: by mail-wr1-x42d.google.com with SMTP id j15so19134476wrb.2 for ; Mon, 09 May 2022 04:58:53 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.51 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=AMHYpqYyVexl/KQxM32vgi111AbDDgBeiFSwyB6v1qY=; b=z2c3usWgNkj0IeuV9S3gCwit8cc13I3mZ6oaR8q4zBGP1Fiy0AEpL97X9a6gPlLACc qTdLg3FoLaPVLcTPDbRCKebFbFUN98CaxMEBSgniqYjOK+fUk888HkPMU09eFlDpjCpc c8Kyeo6X0noZYTDC+EwBoVqOhITg8MugspwiNZS25jGj9YJl2u4pdGTVEGKtMpsKu6Mb wqw/l3JI1xMz+GugZZ2GUAk5DAOWD7MYymSdBAJ/sDOm6Q34suCkECr5iNsXoohatq8w L3JBGfFdF4E1n3/jgVMGcBD482b9Yijjm63TXrkxWrEfV/AtbFHnfFzJFTGtP7ImZcZ4 S3bg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=AMHYpqYyVexl/KQxM32vgi111AbDDgBeiFSwyB6v1qY=; b=IDWZWqcvzi3/I9mRE6pxBRqRo9XA6T1B4Zwp4ET2Qm87EIOync764Bja7MfQKAxdqh K2+7Ztg6G8Kla6aOYYv1fUb4tdTPQUaf/tXKeXtnS74YYCWiwH0y1HxNK8RmUMHrKyBG 6BsMpfYYT7gGygDO2XxfBNJAGbAZig+1JOAj9h1CwO1qCh9X7aQGl4nzKmG7zB2LTP2L 0z1WxwS0pyEdIQBo7T3qFuK8xdE4XRCMyyp+QU4WTOdGN0bsnL5TfK/YMh2aCOatk/fK FfK/wCGDw5riOliJyw6o7TsZ3iIa7Dhq69AvweOec+fdIwB2BhcowXnrCS+9fKbBYmT1 amTg== X-Gm-Message-State: AOAM53304TYNXh1wO8PXZua7qAnovY0GnHTGaeePSw5OF/VCjHfJWKKO tP2ia3UBvA67r06lgY5LZxyvEi/XAHhv4A== X-Google-Smtp-Source: ABdhPJxMDADuwXZYygM1QeSlWj+sV9LdFUgKLipfUx1vwbYa3j6pGMRfOvfm6QTvjGu5h3vN+M/jjg== X-Received: by 2002:adf:f748:0:b0:20c:86d5:c343 with SMTP id z8-20020adff748000000b0020c86d5c343mr13628104wrp.477.1652097532797; Mon, 09 May 2022 04:58:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/32] target/arm: Drop EL3 no EL2 fallbacks Date: Mon, 9 May 2022 12:58:19 +0100 Message-Id: <20220509115848.3521805-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098001779100002 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local vpidr_regs definition, and rely on the squashing to ARM_CP_CONST while registering for v8. This is a behavior change for v7 cpus with Security Extensions and without Virtualization Extensions, in that the virtualization cpregs are now correctly not present. This would be a migration compatibility break, except that we have an existing bug in which migration of 32-bit cpus with Security Extensions enabled does not work. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 158 ++++---------------------------------------- 1 file changed, 13 insertions(+), 145 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9ab8b65e7bc..ea2788b3d53 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; =20 -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0 }, -}; - -/* Ditto, but for registers which exist in ARMv8 but not v7 */ -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D { - { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, -}; - static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); @@ -7902,7 +7784,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_EL2)) { + + /* + * Register the base EL2 cpregs. + * Pre v8, these registers are implemented only as part of the + * Virtualization Extensions (EL2 present). Beginning with v8, + * if EL2 is missing but EL3 is enabled, mostly these become + * RES0 from EL3, with some specific exceptions. + */ + if (arm_feature(env, ARM_FEATURE_EL2) + || (arm_feature(env, ARM_FEATURE_EL3) + && arm_feature(env, ARM_FEATURE_V8))) { uint64_t vmpidr_def =3D mpidr_read_val(env); ARMCPRegInfo vpidr_regs[] =3D { { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, @@ -7946,33 +7838,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &rvbar); } - } else { - /* If EL2 is missing but higher ELs are enabled, we need to - * register the no_el2 reginfos. - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value - * of MIDR_EL1 and MPIDR_EL1. - */ - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_NO_RAW, - .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); - } - } } + + /* Register the base EL3 cpregs. */ if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, el3_cp_reginfo); ARMCPRegInfo el3_regs[] =3D { --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098238; cv=none; d=zohomail.com; s=zohoarc; b=Klfhk4qBi40yDeM8tS6YyADCdwz/bQptk9X5YsG8aQfGRRHA4wyR0RTRnw9DeV9N9AeFCrD95hfONQn5/v5yRx0kLqgP1r1hPSlWOH+JHAfjBzotFTw+owyemHP+wiJ6wef8BJgooLF/HX3KeuSFc/Yvjxuw3X41tem1W6/x+pk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098238; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=td1xtIAYO/HO2sfcsrTqOil4G/8JSLwPxSu0vY6fM+Q=; b=TO6zJizc5yJQuwivVMh2ufCfHLe2OIhIxf+Qy6ObaXV40Ku/j2SoFqs3Uz24MUKEg1yypfhvBqPVw8ciCoN+ndh0zmKgrlz24ptqjEuT95jgJkHCe/39fkiZPX83ib5qPPhiGR45XX8CympCpTpM3iCenqxkMEgTuui00pZiQLA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165209823841384.45358888521378; Mon, 9 May 2022 05:10:38 -0700 (PDT) Received: from localhost ([::1]:39180 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Dk-0004r5-G8 for importer@patchew.org; Mon, 09 May 2022 08:10:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22S-00072V-JN for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:56 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:40783) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22Q-0001Gs-T9 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:56 -0400 Received: by mail-wr1-x432.google.com with SMTP id e2so19095769wrh.7 for ; Mon, 09 May 2022 04:58:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=td1xtIAYO/HO2sfcsrTqOil4G/8JSLwPxSu0vY6fM+Q=; b=KQ5YJNr/ENfUtj1+7cHtGFS3se8DsQ0iM25ElXXWhkX7SF3ulWtYbya4NJKb+RHytc mgEqlT7d+FYQPH8zXVont2mCRaDAT1mj4xt6fqPJuGQYC0mmno7QXZQVN2UWhwQC9mg6 Og/KSo1XdmWmDfCwB/JVVhin7g6DYZi1Sdcxgwo/7eQ0klnOzjb2DEi4BZWPSShBMS6B LqO31X+ASd5qTBVOWWhFKF1y6I2Qv+e+vGH46Wko//nXHAWTnsPio/9+ds4ynDs5bfqW 7WKxhSKkheZf6Id26kpgtp63kKij42/UJ/AYuC8KQbnDbYOttf2QCWHvcV3hjKZF/FR7 C3cA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=td1xtIAYO/HO2sfcsrTqOil4G/8JSLwPxSu0vY6fM+Q=; b=NwaA8nF2QRklpjXTf4eFivD8mUKWkufhaWpJv1Q0kcBZBxsAYWW9ebUTDVVhol3ESN 0U2NnLQkiNMluXA1j0/80InjskzhfHA4U8g3qxlsjtnesVfM3kdPDpRU5u8n7P3AhccK avYw6ssWpnZYgdOxPVWd1Hlhm2PO/oijYHYVxf03SgWfyFgtRLICrC4I1o7etlNzmKgX ImbolRBBN+tzzyuCSCLaU8nqSYZx4bX22cO85mKpYJ4+Y58wyoQ/46Zc/A6pAvg4WYdq /mPzSuR3q4CFreIYEOh7MlKgBmcnyOi+ivOvluRDQA2wDuS8GYtM1XlduY2uQGijuvSC XQjg== X-Gm-Message-State: AOAM533u+3GyXuPcgGLXqIyJ7unPlVuWm5TUVz/IQ796ADT3CwctR7Tl dC57PXch671HybEgqbs63R3tlx6PeTlr7g== X-Google-Smtp-Source: ABdhPJxrOvC9TF4VLkUtPWvx/7nSk9gTo/uMB9dN/HdkLSoBd65fJCRP+x/wH/PltU/G1y7vXJl9PQ== X-Received: by 2002:a5d:5085:0:b0:20a:e090:85ad with SMTP id a5-20020a5d5085000000b0020ae09085admr13387896wrt.235.1652097533587; Mon, 09 May 2022 04:58:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/32] target/arm: Merge zcr reginfo Date: Mon, 9 May 2022 12:58:20 +0100 Message-Id: <20220509115848.3521805-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098240522100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Drop zcr_no_el2_reginfo and merge the 3 registers into one array, now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped while registering. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 55 ++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ea2788b3d53..72d05070f02 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6122,35 +6122,22 @@ static void zcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static const ARMCPRegInfo zcr_el1_reginfo =3D { - .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_no_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore -}; - -static const ARMCPRegInfo zcr_el3_reginfo =3D { - .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write +static const ARMCPRegInfo zcr_reginfo[] =3D { + { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 void hw_watchpoint_update(ARMCPU *cpu, int n) @@ -8233,15 +8220,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_sve, cpu)) { - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); - if (arm_feature(env, ARM_FEATURE_EL2)) { - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); - } else { - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); - } + define_arm_cp_regs(cpu, zcr_reginfo); } =20 #ifdef TARGET_AARCH64 --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098000; cv=none; d=zohomail.com; s=zohoarc; b=TrZO8ssaS+Ev9Q90ja0Adg6Avx7L3DOjS74IYOVzqsm5sYeJRgCPsu143F34uv/zuP1cw0AvxivDmWWckis8R1F7oXiS6pk+Hi4+UkH/q5Zet2IbrxV8i2mypDhNGLPOsMhLkTvt0p78jmwN/jm05mtODxhn2bTNRcyBVGlq7Ug= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098000; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ppR8M7ixk9OKU1weHfQnjLWTVAHBFdys9ITuaO8WXIs=; b=UAWph6ehYppj1fjOJAMYKMXRbSxDb6KusdaYWynO/de0a8aK1gtMZK5OFfR2GTEU+g0bDFHgIEzhnGlhpyT4mRo+Zh28dLv47t0oCQ0lD1eAz9Tt3r9DwrFeUMYuKuMUhgZbCi+hUn+umfzUX4rDS0iZOSMgrW3ARNxZzOsxLq4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098000254673.4521793549244; Mon, 9 May 2022 05:06:40 -0700 (PDT) Received: from localhost ([::1]:58864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no29u-0007Rp-OW for importer@patchew.org; Mon, 09 May 2022 08:06:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49672) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22T-00074F-Ak for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:57 -0400 Received: from mail-wm1-x330.google.com ([2a00:1450:4864:20::330]:51108) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22R-0001HE-Nn for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:57 -0400 Received: by mail-wm1-x330.google.com with SMTP id 129so8240189wmz.0 for ; Mon, 09 May 2022 04:58:55 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ppR8M7ixk9OKU1weHfQnjLWTVAHBFdys9ITuaO8WXIs=; b=pdwa+SCC74XdaKZKT+1bADvrYieb+dWKs/IQ19Er+CcgcDC6Q+J47SPw2nuzys0khf ubZCLZvVLmiJyPa7W2EiULvtWAHv+pK0VFvuuZgPnDE4vVwUflF2tH3qXk1VzN+A6qSt UBbMuVQ9UvTbre53aPUmGQVuu3qB8cQZn3ND1yPTbq2nDkes7n0efYdItRkDIZKH9zi1 dY5dC1vnTyH+MA9dQWeyQqgtZDVY9YqHmgMJ5+HCeCtExHx1Iqrdz082mGaNtdLg0xuu AceFKCUomY159mZMDkyTWuzbfIX/T98UD4XsvcH1f95WU/H1Zhe9zKa5WGMzOwhsVBJW +4FA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ppR8M7ixk9OKU1weHfQnjLWTVAHBFdys9ITuaO8WXIs=; b=ZTksA59LpiH/zsNgajRXEDc2zwjhqFIoxrZ81QChfScRqkY2acstte08287UFe+PE7 Dr2+4EHbqY59tyRFE5K3gwgwBB9AdZGdCm0ZSsrXv/iXjt1ToGpTDAQO7S5gc+xiVXTJ Nq/wl05whnXLkvceE9mQ2Y2qCwvp7S+jNssgztzoVoE9Y+6YOD4jdv+xpeJLTBAxVSyx NQ7Ew9py6QeXdoABLdJ6EdaCJaqnYk2Nz7weTSO0f12UiFIoEj3NY7kzz2NIqtrBIosB lzBGr4G/uKBwoe2CASzvFRXhrUgTBa+Guam9jPAm8Xm3Owl1UOF8IDe5UQqekBP1oK7D y8Vw== X-Gm-Message-State: AOAM53240ZURZNObQo8NiHqOYH1G7X+AAzyRW+6Y2AbW8TZc5IULxHZr rbMrvpCAj0bKdz4WNyxdFT/jjrwkynfwFg== X-Google-Smtp-Source: ABdhPJx/kEnQ1o1H8hAIFoMDsW1HWgoUwoTunuCS89CbDsAZMrWPxngsJ7g1xp7IZoowWZqx/eZjrA== X-Received: by 2002:a7b:c4d9:0:b0:394:41a:d36f with SMTP id g25-20020a7bc4d9000000b00394041ad36fmr15651014wmk.152.1652097534305; Mon, 09 May 2022 04:58:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/32] target/arm: Adjust definition of CONTEXTIDR_EL2 Date: Mon, 9 May 2022 12:58:21 +0100 Message-Id: <20220509115848.3521805-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::330; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098001738100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This register is present for either VHE or Debugv8p2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72d05070f02..7b31c719806 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 +static const ARMCPRegInfo contextidr_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, @@ -8215,6 +8218,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652097786; cv=none; d=zohomail.com; s=zohoarc; b=Drq9zV/00dr5afqTqxey42Vrs6eJNP+2keZK7zGICmjTtYvhBqrVxbQcImVUKGG6UigwuM483/ImvmgiFNLS9mfqX1YVXx2HFv7iccDuZWLExDD7yBMAUZyOibuJgLrGLHeFpl0npDjRz6E7socGWufArqF54EvlEURGce2EB9I= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652097786; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LY5sAZbP9l4aivrMm1pJ8nSFUjBRbRAVppWVZ7qEALg=; b=MbpvhytYmWP+Ojn1ZRMLpiRbyyBb4d0v+HJpKbMSeCU2gQV2nwnkaj7zNRGaCe7sLiPCDhaw01O8kdtJJmVFtsxKhAUORuDUXEHI6xGVWAxFdRFNU6fIJu6rZ+BcXrx3DP1VQ2AEUnxThJUvlQCx0WJj0zajhGXHCypGdL4Pq8w= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652097786005212.95812203092203; Mon, 9 May 2022 05:03:06 -0700 (PDT) Received: from localhost ([::1]:50830 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no26S-0001vI-CQ for importer@patchew.org; Mon, 09 May 2022 08:03:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49694) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22U-00077x-Ho for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:58 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:53958) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22S-0001HQ-Ii for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:58 -0400 Received: by mail-wm1-x333.google.com with SMTP id p189so8230788wmp.3 for ; Mon, 09 May 2022 04:58:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.54 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LY5sAZbP9l4aivrMm1pJ8nSFUjBRbRAVppWVZ7qEALg=; b=zobKmjVie7A/HsvDzpHJ5zvXYJ2RvxBxwxnOmeDfXoulseASR8suIav66VHRsoYM6J f70r/kAxepge4buikzR0TX6cKUdG75Tw/ETpMSvQMgmWdDJW+Q0ftEN3O/mvwNkR9dif KDqGpEGWMHiDtNnYj08UFizGDTT6gZF5B8O0Ara1v5dmKxHzcF8W9q8ozygr2rY5lys5 Xo6EeEDduNmNNVdy8T2Yty1EfrnpqfonXOJEgndSOk/ighyZFS9JCNKXUlgtFvVYsxjn V9UiwOrz269fSxoaSYM+WtCCAJyEQJpLWBXCEzg3LDwFKyKFRhanOx5aVY9D1DyN78Gt JnQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LY5sAZbP9l4aivrMm1pJ8nSFUjBRbRAVppWVZ7qEALg=; b=rtePg/xFR0o2iJ1DGgQs2A+Fg9cOTdqCyYzd/jpuXPsSLO2W4VExToEIrFJx8f8Q8Z kL2etU55g62cqiHFGB22mHX0+iDrA7zmj3tBXu/T9LU4N7Ky8btV1d1YfF1qKc+b4YXL N+LKXOZk6xUe8LZIxw9A6vFROIRqkChn+wf4h/ghzXilHYcc41OGp0cERqmM1KkQCW2e exdN4Z4raCLcMYkoTRcepllbxjQxCplWIvubhWDuIqkeoH2sHqBPN0T2pNb0BAv86mwf 71sMKyo5hvpi3ClTGeM2oxsCkTMlA8Fu7cPVzTarbv/T751oQjvewtGa4KWoATuFXCJS 51FQ== X-Gm-Message-State: AOAM530VIFsHuSyP7euGXchH85bg031c+7prbiYEvzwWa59GIjYeiwys bibOA7zEYnJgXoO01RgTnObdQwBQM2kqwQ== X-Google-Smtp-Source: ABdhPJycdfyx+o9y+X6YZ26kI4Dwb6kTIe1hRetWS7+3p1kN34wak22Fu3So3RXHm14MqUkCFETeng== X-Received: by 2002:a05:600c:3503:b0:394:8382:9fda with SMTP id h3-20020a05600c350300b0039483829fdamr10189511wmq.0.1652097535186; Mon, 09 May 2022 04:58:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/32] target/arm: Move cortex impdef sysregs to cpu_tcg.c Date: Mon, 9 May 2022 12:58:22 +0100 Message-Id: <20220509115848.3521805-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652097786498100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Previously we were defining some of these in user-only mode, but none of them are accessible from user-only, therefore define them only in system mode. This will shortly be used from cpu_tcg.c also. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 6 ++++ target/arm/cpu64.c | 64 +++--------------------------------------- target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+), 60 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 255833479d4..343b465d516 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1307,4 +1307,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteA= rray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); #endif =20 +#ifdef CONFIG_USER_ONLY +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +#else +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +#endif + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c841d55d0e9..33a0a719003 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,65 +34,9 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" -#include "cpregs.h" +#include "internals.h" =20 =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; -} -#endif - -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2CTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, -#endif - { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ECTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR", - .cp =3D 15, .opc1 =3D 0, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUECTLR", - .cp =3D 15, .opc1 =3D 1, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUMERRSR", - .cp =3D 15, .opc1 =3D 2, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2MERRSR", - .cp =3D 15, .opc1 =3D 3, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, -}; - static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a53_initfn(Object *obj) @@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a72_initfn(Object *obj) @@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9338088b226..d078f06931c 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,65 @@ #endif #include "cpregs.h" =20 +#ifndef CONFIG_USER_ONLY +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; +} + +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { + { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2CTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ECTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR", + .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR", + .cp =3D 15, .opc1 =3D 1, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUMERRSR", + .cp =3D 15, .opc1 =3D 2, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2MERRSR", + .cp =3D 15, .opc1 =3D 3, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, +}; + +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} +#endif /* !CONFIG_USER_ONLY */ + /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098008; cv=none; d=zohomail.com; s=zohoarc; b=X6PQwET99FLUcm4ZazkhcIZtD1H7MAIjHn3G0cIlsACvCKWeWqakMjX5pXWcn4zjQPTKL13teqsZu/ZNFx9xKC/1/8TwPrbRXWSkshuksz5yqjP+anNDNa+HYWLWOZzt3N7Q4WYsVAJSarhYP2npzf6dC9aZc5vYD8MHue1rn4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098008; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NTlGCwPOD+kUxmNLauVtxFXKm1Wxpl+T/qfsIS4Q+pg=; b=L2rn733Piv/riZm3stEjvMTgPJiip3MJOREVgMGcjC/RRatXZDGBoafW+HRjoJFfKwW8iNWKYeYU94RiHiMg9qTN6AC0B4bDZJLaQUo5X0bS8OwF2qGo1c3gMmkK4Bf/cD4nUxXetdEQHCKz6b+7AaS2X6FwidX/c39Dq//2IBI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098008773280.4117518525611; Mon, 9 May 2022 05:06:48 -0700 (PDT) Received: from localhost ([::1]:59592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2A3-0007x6-PC for importer@patchew.org; Mon, 09 May 2022 08:06:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49714) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22V-00079U-9N for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:59 -0400 Received: from mail-wm1-x32c.google.com ([2a00:1450:4864:20::32c]:53079) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22T-0001Hl-Cb for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:59 -0400 Received: by mail-wm1-x32c.google.com with SMTP id k126so8239444wme.2 for ; Mon, 09 May 2022 04:58:57 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=NTlGCwPOD+kUxmNLauVtxFXKm1Wxpl+T/qfsIS4Q+pg=; b=ONB7tcZwaI4hgq6dY1sBEOEReFZEBy8BK8o4WP6tv2IU1IWhpcfoxLDKCCLi/hmeyw bPu9Q5ZDLKCzX9FD3Cyee+mOvoAznoe3cJSJ1HygItRc5EMjm8Ly5NQESOJ5Rf+xZLHs ZZhcYHQnC8W8Y9mSOgqbwO3X7j3YA42d8fXX2kFgw9YtmmUxqULcP51b10D7MrBgoF9Z jZyznHNuawB8En5LsVHS3gi2w165XOMpG++XVAv3lDS3MPpXfGwRMEitOBxDf6OpuOOC mcM9Va4EncujNImyRUH8r63Ap74w7XwJjfnpT26Uc4MAXV1kE7DhOJYdXMdCXk+H87c+ 5LCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NTlGCwPOD+kUxmNLauVtxFXKm1Wxpl+T/qfsIS4Q+pg=; b=RClksMzbexCE3JBQURSadlQXaIcG+KcONTScDijDi2909cM7kFY6VhuS+Kaxfsgzh7 6aBukBOboDA88kU+7B07evR8ypNAPsk0clF34yQQ8FMaRubP5yvzyqQcPfVzXGLcjuLs 5b6uQHALu4O+n1qRjiSEaNCjNernNYWz7BfFCX9DKoDxAM96H5VbfqEodx59dhzgOcQp hmNY0lIkRjAgEbrR+QWpEaQ1eh+lEk6U8LdrQfd4q9LYeTpAqwWYsVQeJJqAeYOJc+mT b+MxFLWJN3OOiuowagLoJA2P8oXhYjjmpYJJJzi6F46p9CB93ndefuOm1WqI/5i42Ovt o56A== X-Gm-Message-State: AOAM5330kOkHp9t+K0xuAjs4X4uWDkuSQ77bM5wkDlBfb4fNpNwOCqgJ bjGjL9MZFTfGj4fUfAzqzNLP/kNMsiPnxA== X-Google-Smtp-Source: ABdhPJyAwTKdijUYepEeXC21x1hOY0XNN+O2on8+LTcn7iSdsUb3JUiAlhnwiTJOqhSWVHBdcpeG2A== X-Received: by 2002:a1c:7414:0:b0:394:1d5d:27f2 with SMTP id p20-20020a1c7414000000b003941d5d27f2mr15811751wmc.37.1652097536026; Mon, 09 May 2022 04:58:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/32] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Date: Mon, 9 May 2022 12:58:23 +0100 Message-Id: <20220509115848.3521805-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098009718100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- 1 file changed, 92 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d078f06931c..f9094c17525 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -994,71 +994,104 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t t; =20 - cortex_a15_initfn(obj); + /* aarch64_a57_initfn, advertising none of the aarch64 features */ + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; =20 #ifdef CONFIG_USER_ONLY /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. + * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. + * Only do this for user-mode, where -cpu max is the default, so that + * older v6 and v7 programs are more likely to work without adjustment. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif } #endif /* !TARGET_AARCH64 */ =20 --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098248; cv=none; d=zohomail.com; s=zohoarc; b=V+vpceieP8Cf4sl65pWted9MlWCH9qpGbDRjMi5k5qoDTligdHaqF4g8jf9LNqVI//oBBJKtAKxgzaWwDVJX1goGnYZ2VHLVxWb+pOGPhIrOEI1juJpm7lXLjddRYGYyEy9bc/2D2k1w9NdFd67j8UAbABHc9lPjfziJrWiq4yE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098248; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=utw3LcG1dMmm1L7xgVlIZJE0fwXZzx5RP9DT2it4qMY=; b=PfPGmFEwWl4HKqbgRlvCufIDXrNc3KrzIa7NjpCkXpZpYohM5I9UppVACNg/k6S0DiTZ7MLR1NDwHPqCwmWkiubaLdHspwc8805ATv+CIwDBu6Oz1kNKUYCcWhLVbFyx+sxW3O/zuSlgebHiBPxuiPvmOcERhgjLeyCvGPPVltA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098248361566.3853265073266; Mon, 9 May 2022 05:10:48 -0700 (PDT) Received: from localhost ([::1]:39978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Dv-0005P5-7F for importer@patchew.org; Mon, 09 May 2022 08:10:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49736) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22W-0007Bg-9M for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:00 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:47027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22U-0001I7-NI for qemu-devel@nongnu.org; Mon, 09 May 2022 07:58:59 -0400 Received: by mail-wr1-x429.google.com with SMTP id i5so19083154wrc.13 for ; Mon, 09 May 2022 04:58:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=utw3LcG1dMmm1L7xgVlIZJE0fwXZzx5RP9DT2it4qMY=; b=I8LFVy4UBf/5CFt85x/PlfGgFsQDAgSkpjJYzu5aCnA5ngi7bRI+QXAOM8LKDTwiRG fDcdhZnbyGPZz6rBxGPy0+uONdeTkTVJkBsRB5rIjR7GXoEbCrSK4iuXAyKvk/DR7h9m ggbCA4RbeUsf1f9t+kWCK+rak1mBn5bTH7UJGRa0Hrg3INKkQ+AXlFKtCxzaVoykdXyr Poutc8I1YMEjL9C0XPkkrq56dGvL3shY0EIdj4pGPA6e3vMhg9cwln5mp5lkgm8kfiwu pxIq2SgVvblo6mSJ5yQFnUapHtfDKWMVhYo7XPdFV0sw0mHWDHRxnFSCp77kAQ4ivW8C BOJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=utw3LcG1dMmm1L7xgVlIZJE0fwXZzx5RP9DT2it4qMY=; b=bqCbKZF1dX/2H78HOYLTw8wbV0FREG1X6a0FamwN0VvQflccT/tI36AwQzgo2nXNSt 92XSc0jxfMf5XjkgVgRGPcpw6Den9qSTEATMPUYffgciJ7QpUFstg/64QcU6ILHWjf8Q zvsygXHFKyGtFQW09pAMy3+lwkkxl1tAnUzu4afvHgdO9Jr7QriAAkk6+3P+Yw48ytSN GX79i8vVS0XFweyxnh06raCdSU2uvXGBVPol0dpaEUecGJRu2xeMDAElpPbd6FueKm0u VljpUhtVZ44pJXFxlyEe0/2AWluUka6M08M6BQjLPvTbhhXup8aw2zhwwc3lTm3A2W+J loGA== X-Gm-Message-State: AOAM5300FfdDDl/6EUsEWHfbbDHLC4r2KKb5HzDEbvm6A6y13iCztTZr udjjJ36ZIa+4OsxYbVIwiRCiXHR1bR8VNQ== X-Google-Smtp-Source: ABdhPJxwRKncAo0BqRj7yDmkw5wpBs+H3y1ewro5MYAhriKtebgOmNEOxE3BXnejZ2BuFqLAQAzZUA== X-Received: by 2002:a5d:598e:0:b0:20c:57ef:6083 with SMTP id n14-20020a5d598e000000b0020c57ef6083mr13535445wri.457.1652097536728; Mon, 09 May 2022 04:58:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/32] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Mon, 9 May 2022 12:58:24 +0100 Message-Id: <20220509115848.3521805-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098248604100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f9094c17525..9aa2f737c1e 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1084,6 +1084,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 =3D t; =20 + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; + #ifdef CONFIG_USER_ONLY /* * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098514; cv=none; d=zohomail.com; s=zohoarc; b=RTH/Z+uNk6SUlSXVYvTR0jh3XN4UfcHAU37IhZyn2pnRCVKVfzc6iXhSAPLBOp4QIeZCxrljmo8//olLcnoHqhgxfbje84WU1msc5n0g/IqjsfPqbAMmQqJidPjsVOX/S6mXK0ZAKhFqLkKYUaaKZ2NADdkukjI6EuxYQQke4FM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098513; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+LCYa4SACHz39b/N8QB7n8zUhxKTI4/N9Nw1WrChTbA=; b=OUtlo8/9BF+3rC/0O05y//COrTBGajQNuVPRUpxUbL4Yk3XxCEQxgEYtoXrC7a5AX5cZJeqVF2Et8oGM8ytXpbIZ+YJZp2eNK1cWPb1e6o6pvPKlR/VjzEbzEhGHFMbiNMhARuehJCNZmDyEVOlVRkMJz/qgrXJ+QJXgExUKg2s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098513991638.8448011691145; Mon, 9 May 2022 05:15:13 -0700 (PDT) Received: from localhost ([::1]:48580 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2IC-0002oX-Nl for importer@patchew.org; Mon, 09 May 2022 08:15:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49766) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22X-0007Dv-6D for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:01 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:53084) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22V-0001IB-3f for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:00 -0400 Received: by mail-wm1-x331.google.com with SMTP id k126so8239512wme.2 for ; Mon, 09 May 2022 04:58:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+LCYa4SACHz39b/N8QB7n8zUhxKTI4/N9Nw1WrChTbA=; b=EmXl+onMX5B4JnHTlHew38l4WLwLQFQ7VgB+ttMudctyRIWblTzODdj1ykvyq6S8sD 7nGR0ZZptOSqbzlIVF4QKLQXc9e3M9eAcNl44G1NyynIFGa0ftzery3wAZxwIpq3QCOE 8ucqiLc3O7inJE1Me9PO4zqsXICN0wKyd3Hv90Pa39P/ItQummhBPF9omrv72JC/whY3 FV18iB/rPIj9a1Z2d7hX6DkWiwyKnXYa7eG+lFfCW+9G7Stc4T+I6BeKe/kJ76P4s3C8 OH6FuRWoOavorhpSAE9MUWX4KnS53k8o8gHLH+ZA64Wl9x0Ui61clBgrr+s7KgWUXStN Mjqw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+LCYa4SACHz39b/N8QB7n8zUhxKTI4/N9Nw1WrChTbA=; b=23HVPgtfDdrOBp3Q1nZvDuUbJoBtrPnhJIZKo32StNNnk9QpLagxsM6EXxDNWKfVjD IltJYwpwLJWSswYMTN/GiWDmN2H2cPR/FzLN8/5+vfEmbZWsg3b32pJiY93hNPhPzYLJ GdmIvUvyEBsbxr+MWH6OWetyP6elP/EHGERoqcLVRD5gl4NhYuM2JILiCeO6K1Eb9h2J k5JYucGYxurUuAFVw+2eK/ayq38DQ1Abin4N3Cbx0qAZo5y/OIcZRFFzpSAP47kU5m6l UpUWbWKqVU5/8iLm/EvdslSRmmTPNke3JL8AftgUC5xdY5dktDjRP8eADnj75rfOEVxQ XXCQ== X-Gm-Message-State: AOAM533DnnjnCmh+Mo7FglghbqTx97DlFOCpiJ9PJoognHo9PyWl/r6C DNvAQ0WgkVsR+VimxPR5QhhewcrwLgOLxg== X-Google-Smtp-Source: ABdhPJwuiMzuaUbGJ6l1axaOgqUUJGpeW+WXdGXxWEJ9QbLshNXjjQT26QVzipe4rfIZIH0KmL5Hig== X-Received: by 2002:a05:600c:3caa:b0:394:8fb8:716 with SMTP id bg42-20020a05600c3caa00b003948fb80716mr4970063wmb.105.1652097537613; Mon, 09 May 2022 04:58:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/32] target/arm: Split out aa32_max_features Date: Mon, 9 May 2022 12:58:25 +0100 Message-Id: <20220509115848.3521805-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098514553100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 2 + target/arm/cpu64.c | 50 +----------------- target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- 3 files changed, 65 insertions(+), 101 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 343b465d516..c563b3735f2 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1313,4 +1313,6 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +void aa32_max_features(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 33a0a719003..6da42af56eb 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,7 +682,6 @@ static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; - uint32_t u; =20 if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ @@ -799,57 +798,12 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); cpu->isar.id_aa64zfr0 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D t; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9aa2f737c1e..b0dbf2c991b 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,66 @@ #endif #include "cpregs.h" =20 + +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; +} + #ifndef CONFIG_USER_ONLY static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -994,7 +1054,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t t; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -1035,58 +1094,7 @@ static void arm_max_initfn(Object *obj) cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - - t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D t; + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098707; cv=none; d=zohomail.com; s=zohoarc; b=BMwxYkz1QR21GDEFnV4r+YzCdnP2ouPMt5l9FhqBrdHE8WR3gz8qtiAKmLWcwIMv19V+46Atek3M2Mm+LQzK2zu2kC5pZs+CB4aEpq1bRCjDk9+ebNkqxXRq2NVOntslRyJTabhAj0Uc1BSjOOR/jXM/l2lQgpCZY3W0OmPcYOE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098707; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vceOIhx7TgPek853xQx9nRZrn5XzWmRekZy6kMIQLHM=; b=HtuUwhjKK1uqf4AifQEu8jIwQGORhfvadd/zKOg03KTU5EZl0Vc084asNSyVBI/nzH9TQYIhHdVvzhULC3NNLRDoz6dUGEBkAwuZmTu3frjh6U/+IV+cxrOE9t84MNhh6/c1N5Xc7iELmsnyhlxhrr+vRiWcUK1/jZDnudLFJNY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098707237352.58836453338995; Mon, 9 May 2022 05:18:27 -0700 (PDT) Received: from localhost ([::1]:57170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2LJ-000082-Mk for importer@patchew.org; Mon, 09 May 2022 08:18:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49768) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22X-0007EE-9I for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:01 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22V-0001Gn-9j for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:00 -0400 Received: by mail-wr1-x436.google.com with SMTP id e24so19108668wrc.9 for ; Mon, 09 May 2022 04:58:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=vceOIhx7TgPek853xQx9nRZrn5XzWmRekZy6kMIQLHM=; b=jDD6IlsQ9JjrxAmW8owpTZQ6OTI54wUiYtmu9oNICosINeB+VD1KlTxzrjxGY2rGIl Pa9fE+/Lwr/+jO3+4yu9YHZLPXA1+kmJCuda4Sy+yOb5wZcVixQx0c/tDzT3gojeyPu1 zjoalsaeBqnb38Mi0R2Uhw4oK8F49qg6dRnn5pcbYkx9ysD08nW9Jf6s9WC2PL0lRWXT xTw+vEgxgzujSGzelYqMx2AYz+b+oK48WNXhhk5Vv3H2nusZmNQ+FOXKt80VBrfDptyN IVEas9gTMx3SMcMQ7gn3/q9iaYrl9AK1SGG55k2EdZH7dOwMgVZIqq/Mq9OO7JL3GZ4F OgQQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vceOIhx7TgPek853xQx9nRZrn5XzWmRekZy6kMIQLHM=; b=6A8lUY7QvFH6ZtmaKfygCdqKX6k5LRnTPTw2ExBp8sVSaxTXK7JEuNcEAoU5xrPscl h1KuD2LXtajrN4tjt/HjYGHrMrv3pULwjNCPTS8SekBp3+IaFKHOm8N+muPRzQHU4FNT przHvGQfam+pxAMsfrwf+AOKfe0uuVHiguvGfTD6cpDpRgVMjWYLU7nOONUmjAqD3JLP d0XPtTsGEh9d4VHy2t5au0ROijdtsH6X9ibuk++/I4cIihjU2NgovKmjbas4Wj/QRGjJ J6JCgQF//brRvfrX9Rq7GGXD6hWekJTZvylV/0b76p6PSD5uBqwIMO7kqOXxn1qVHGun gc4g== X-Gm-Message-State: AOAM532OvIveI4TcZOQgo/4q9el2U9hneQINX9NTo2lZ67dNQTl2DeIZ 5tZJvP+uNblk4YqR3wfZiLQrCl96JzhSpQ== X-Google-Smtp-Source: ABdhPJwcxuVk9wSgKo7G2eXmSk2QcOjAOgpyGe9eEky+KCCRNbkw20rpk4V2uPvCzq4axinY/lEx2Q== X-Received: by 2002:adf:fa42:0:b0:20a:e8d6:58b8 with SMTP id y2-20020adffa42000000b0020ae8d658b8mr13912991wrr.64.1652097538460; Mon, 09 May 2022 04:58:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/32] target/arm: Annotate arm_max_initfn with FEAT identifiers Date: Mon, 9 May 2022 12:58:26 +0100 Message-Id: <20220509115848.3521805-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098708497100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- target/arm/cpu_tcg.c | 48 ++++++++++----------- 2 files changed, 74 insertions(+), 74 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6da42af56eb..5fce40a6bc0 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -713,51 +713,51 @@ static void aarch64_max_initfn(Object *obj) cpu->midr =3D t; =20 t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; @@ -769,37 +769,37 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b0dbf2c991b..bc8f9d0edf5 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -28,55 +28,55 @@ void aa32_max_features(ARMCPU *cpu) =20 /* Add additional features supported by QEMU */ t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } =20 --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098040; cv=none; d=zohomail.com; s=zohoarc; b=niiLXC3219vQ05bkKHm/DIW1vKP/dOqCl2uTswpnZ8KUEG/wMKxr209B+2hbFTS56lkdLvezFXuAaSAldXvlgYWWh8h5lPJjgDK8BbWAX3WHLAbkalBD8NeQWw2KEAHagraYa2O/nzxhklf5Vq1vW8epVylDuiQeHojh+Z5kKgs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098040; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qa9bXLZrtUjkR08O1nmZU1gZrJzLSKj+bcC5vCf6akQ=; b=XfvTMxdTUaynbIqmw/YVcnhZRH6oErUJCk1Hup7VhuUfnsi+sv3Oi7p0AiexRsow+YHoYbheNiHfajK03GAG5eDGsx/QnsFjaCgndw1GZwMIUxq795xNt2g2FBlnZHgDLI5RjbB8ebMMH8BsxoFyFPsoSL3XHz7SqVxaUUz/R6k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098040104619.3851311775186; Mon, 9 May 2022 05:07:20 -0700 (PDT) Received: from localhost ([::1]:34058 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2AY-0001Mg-KM for importer@patchew.org; Mon, 09 May 2022 08:07:18 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22Y-0007GU-Dx for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:02 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:45640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22W-0001IW-L9 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:02 -0400 Received: by mail-wr1-x42a.google.com with SMTP id w4so19070775wrg.12 for ; Mon, 09 May 2022 04:59:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qa9bXLZrtUjkR08O1nmZU1gZrJzLSKj+bcC5vCf6akQ=; b=lBg71FUejsMOGgDjkg2a3q3HoFPcoiTPkAk35Re3AJwRs0yh+f/bK5BJdJjBXlC8hs OosnlXDx+F65FS74EZDPU15JKWM6kBHI5LMcvUoRnUlJay8BC68KNDSkpZu0iKhMg46G QPA8NDchVgqlkltUAz76bGCJ9ABiFZXg7A4XrWsO2ljNNBncz901Rr12lYntwSI+qVx8 V/mdTqt0SFA7xCnBUsk1AV0z9AvDa+EqFchN1s3utb5XqjKwLg80DAHrul19XvhAE7Gb p1eD9/KwQ+neTnAGQQKindJ/XkXgBEAgXAVD22liBy9X3gSSSX0r5fSB0OiD8R+Cc4RG 5uUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qa9bXLZrtUjkR08O1nmZU1gZrJzLSKj+bcC5vCf6akQ=; b=imhEB6L4dBCIaUqU7/GUp8xo4tVKWP2EZNzngb4JfM5/ds8m41wuA94GEZO5fK6qQO 3lxZoA42aTt5Qxr/dK6Db5EuVp49RgTJzZFy9eU+9yURTAe2TUlVY6WnVx0IcsdNWRI6 +Xwemqi7G7kyJNzszVtVgxWvsBrwQ/I3qouFmILbuzOnFB/Qeiz4jJehlp6YP46Ut89m d43iyAQF+9qgisZ0JSGe0UWtpW76x/4mmQ1PQGom4kfq4OLn/ohB6ryTDOjcUPMN4JGU nNUth/aHPv/Mfo0j1fmasKcoArgavPWD6bw4El5SA4LlciY2b/iJXNJWfJguhiqqBELU oWmg== X-Gm-Message-State: AOAM530cl0lU5ZZ6ZVRS59NleRDQPjwJisK7AJucDQ0TcEO2VHd7T05q ZrzVj+OFTKwYOVUvTtBgU9aVfS11KkLtuQ== X-Google-Smtp-Source: ABdhPJz/X2PfI9jjaAnlGW3NXa6CHlPn39KAWrCT08Y6elcOb7XxnQR2YzY3UIHecdZ+Ih4UhGV/sg== X-Received: by 2002:a05:6000:2a5:b0:20c:520a:a12e with SMTP id l5-20020a05600002a500b0020c520aa12emr13088558wry.629.1652097539234; Mon, 09 May 2022 04:58:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/32] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Mon, 9 May 2022 12:58:27 +0100 Message-Id: <20220509115848.3521805-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098041122100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-11-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01176b2569f..7995ff27126 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098238; cv=none; d=zohomail.com; s=zohoarc; b=Ph8rIH1nd7/aT439O386GwvEvsZ97sG8Q7ys1CyIWo96m2f7itdlcTjSygw84CLQsfsnn82alNXOgPzfgo9i+o3AFFD6e2YOnRCFAsnRI/RFG3NTrunIL8c0O9jwZa1v5exqBD+CpVpEn8ZXkoNi6Qvp6Ry6w0a0qhSLGu116O8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098238; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SNNEXS1ZgRVkdqjO580Cr2E6Kdi1t7aqdV46MS2BNEw=; b=KjrsxSx1FoWq4b6Zul3Dx7de87UXmZhnVTpzJGFxAtn1XhUALoSrYQxvRY9mTDoaV+Elqn/Xc+uPgCU2oMahZ+4gwiZ978oq+rpBJOgxhRueSAX8cl+b19y7tOWttJ5BiXtmDytWoLt4PQXl4Mj7xI3gob5BzHkKYEKoWgy8Zes= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098238191675.4073667357322; Mon, 9 May 2022 05:10:38 -0700 (PDT) Received: from localhost ([::1]:39118 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Dk-0004om-Ir for importer@patchew.org; Mon, 09 May 2022 08:10:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49798) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22Y-0007H4-Jv for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:02 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:47027) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22W-0001I7-TN for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:02 -0400 Received: by mail-wr1-x429.google.com with SMTP id i5so19083154wrc.13 for ; Mon, 09 May 2022 04:59:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.58.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:58:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SNNEXS1ZgRVkdqjO580Cr2E6Kdi1t7aqdV46MS2BNEw=; b=yqzZWaK3b3AL9Hh6QRmWSVZRLVT/aMXPv8KvS7PfUbtEzDhZJtWqizDOrFhO5o0GmR +UgCHdwTYnEUALB+6eJJtVYnFziM2LORdrGg6XXA198QpjIGjLjUKCdc3EA5t/KojgSD KycfwuLTJE/0kUAnCOESaCSBt4ICku85LPg3Kfcw8cu9Xi11r1GXc+YunKudR0cYPUwu 2Ceof9XGMyFjVTQlHfqZ6QF+5vErB30yHYi51V8GOMIA4kj7D374tRKqYGG3VdBsf4sR 4L6w+cdd1cmCgTrrzUFambGzJch2vPMpYIq8UOIfMjbDoWpwKdpfqh/r/LBqQ2xNpUnX Jwng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SNNEXS1ZgRVkdqjO580Cr2E6Kdi1t7aqdV46MS2BNEw=; b=I4kT6vd2WkjNoU0O6DUVmaZ3Vib4RjFVgSJCOj7AtilPhiQHVe6KDFBvduj2Xf0KvB yeeTrrcSmOweGB7y5nOL2CUCsB9N8LhE9557rbRaLG2XC6jkD3eXTRBg6216u0D+UdJV tB94NaBpfdj2pudhbL++HIhwfpDCvVK/Jds3mSoHdhScslWyVnEp6iDzz0uVEK2iq0fo wyx14W2vuE3KehyT9d2zOJygp9Rqr9jDnI/yYPs5+hFdZfPMu+5htGPsZOL5hxDJ23kn cz9Xinckt/uLHtB/7wFPUB+ZPZQUPQFp/rtVEt9d4F2wOM7lhjsZBOYCNp0R2/4xGSH+ eH8w== X-Gm-Message-State: AOAM533FLUDSuunSNRiHnBXYg8BJD7jz3/xrP9sd3wwX3vjoa2NVgu35 fJBlE3GGk+oPsJxiClGEesc9PfkqT70J7g== X-Google-Smtp-Source: ABdhPJx9mqlyODTbAJLRBhuRs5USzbrO1f5whAGa143sN6cu4xvUaPmagKJC71wbWGfkKCarhnqgYg== X-Received: by 2002:adf:f748:0:b0:20c:86d5:c343 with SMTP id z8-20020adff748000000b0020c86d5c343mr13628538wrp.477.1652097539979; Mon, 09 May 2022 04:58:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/32] target/arm: Enable FEAT_Debugv8p2 for -cpu max Date: Mon, 9 May 2022 12:58:28 +0100 Message-Id: <20220509115848.3521805-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098238723100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index c3bd0676a87..965f35d8c9a 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -14,6 +14,7 @@ the following architecture extensions: - FEAT_BTI (Branch Target Identification) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7995ff27126..2667aaf28bf 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1806,6 +1806,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5fce40a6bc0..202fd5c46e4 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -799,6 +799,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index bc8f9d0edf5..b6fc3752f2c 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,6 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098491; cv=none; d=zohomail.com; s=zohoarc; b=dLGtMdywCz3E2yhIKoXH2tqawL/ML9mpKfsvErLnYbZilRM69OJkzxp2C2Eo1T7jd5onDlu29FQEkrh3S91T3pVrnPka4oMhmSeyJ9Uyiyg/wSxCZ2jiPUKtcBzPzDYMeXW80W3eqLWKGetu+5l7jFhyTaeOfORBj3FUTEYK8i0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098491; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Xq4iM0BZvoq8/HgoELbIYA7Nz6YX3WBJKHh4C9qCekk=; b=TCnqLjHquTzh4sCGNM5DEqNrhdctWVXkqfyA6lTvtPjXvhWQjj6WiB9mtzfTuxDb1YAUACuIJNdApIGbSlz4T8GfXKLI1gyN+XTw1EgD5HEWpknaVKrIpr0+SyQOtHW8GtRLuFk7QUNHcKKPzWPlBY+QZjwGXs5rPtMPrxbtpBw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098491622244.74869156222292; Mon, 9 May 2022 05:14:51 -0700 (PDT) Received: from localhost ([::1]:47706 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Hq-0002F5-G0 for importer@patchew.org; Mon, 09 May 2022 08:14:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22Z-0007Kw-QC for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:03 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:38580) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22Y-0001Iy-4l for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:03 -0400 Received: by mail-wr1-x435.google.com with SMTP id k2so19091116wrd.5 for ; Mon, 09 May 2022 04:59:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Xq4iM0BZvoq8/HgoELbIYA7Nz6YX3WBJKHh4C9qCekk=; b=YnZ+dLdFO1w6+l3YjhRNd5NQJqdvO2432QMMUh1CDRc9RTx56xWW+6RtxvaAJAP5OY tbze/z+u2CM5ZvwkFGSvbMx6WTyfGIISc7+xF7kEUr82fEs1b72JUj9XwBad1YhH/66b shmgD73107weCRObpB0sowHZ0eALafMRDwXelIQJX8OO12jN83bdG1LyZtQU3CnKnmGD OlASbUmg5YP2ng3pyVwqKJ78XhZ446fQszYhBYEwLX/YnempiknJNEuZdGNlGmXVYTqZ eBBrqWPlgp547ZGwwyIOJolb/nhwu6xIXJifxwQF8eHcruC8fDdeIEl2Zyr6vKXrr45t AG/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Xq4iM0BZvoq8/HgoELbIYA7Nz6YX3WBJKHh4C9qCekk=; b=ZJ9Gz4dtoOxhpvIAPMVm87kXN/Z3zMrQ98OhCzdbnTsUOlm4Bsr2k4EYTy7VyTwwGi uEDgHIG7kI3bGjA5+R/C2MXWtIX0cEArmjtVBvLexh7ZRF9Or8gPW7YKKkCc8wN9xKsu 0M4jE4XMl4FcDBy4VRGrLFvznd/VgW85Alc8Leeg3eZj91s5fKfZud2nVXzPFavksz2j emxDrEUnbFC8QQbITaRT3O25l6pymHFWc/d12AAbQ9QaADXhl0A9+mEuYlEE/cVcTmrS L5PCkryTNgwkglhDfGkfZ/KfAIJ9Gd412D+6+5tj9F5dv5G/SC8PmEaS75f4QA+glj+w LRCQ== X-Gm-Message-State: AOAM530q511aYPHaAHuj4tiZnRxvPN2iUwLpSrSU4uog6xndtioLVRNx zlPs+syDAN+WUMy0NdjE6OwB+rSmalCijw== X-Google-Smtp-Source: ABdhPJyfEnO9NTdWA3cikiGmted523EQrW8IsYgEaOQYWHuZav4hDyt+Xh/TJxrjbZrrNrxtAzJ9Gw== X-Received: by 2002:a5d:5085:0:b0:20a:e090:85ad with SMTP id a5-20020a5d5085000000b0020ae09085admr13388304wrt.235.1652097540757; Mon, 09 May 2022 04:59:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/32] target/arm: Enable FEAT_Debugv8p4 for -cpu max Date: Mon, 9 May 2022 12:58:29 +0100 Message-Id: <20220509115848.3521805-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098492553100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 965f35d8c9a..0acac6347c5 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -15,6 +15,7 @@ the following architecture extensions: - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) +- FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 202fd5c46e4..88d3cef93e8 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -799,7 +799,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b6fc3752f2c..337598e9490 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,8 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098496; cv=none; d=zohomail.com; s=zohoarc; b=ae8qnxwmNvjj8RaevD5OjXt6XKv0gKqvSHIH9VR5KBOYQwQI096MInEYKK5kx9kLYC/vxWzvTz6uwT47iQGciVCZ2XmeAh1bQLNnmOO+UBWQWAxZ5bVz6A0R0JPnr7wjGL7SyAFClQ55IBnqXyW91F9x72ZP3oeWQ0jp7uSG2Tc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098496; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QFEFHrp8GnfgbZp41x52WMf8dTsWr28zOIoNVlzdXik=; b=LO+2Zrqwuk3bx0Yf04wZ1mZZ2pHtFBXZfOtNAG1nggpE+TMO3Y5/KLubBOFSUKVrSEQyjgiaQM8QSAowgEKfvp+kcY7+8NpfZHL/bhFbuQQ0VOaSZgR9c6vBSWmgdofNrwlUmfDARyv5T5C6Q4V7A/eeeodOuiHcbkBhP9mFqOg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098496954416.09370008714166; Mon, 9 May 2022 05:14:56 -0700 (PDT) Received: from localhost ([::1]:47978 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Hv-0002Qu-G3 for importer@patchew.org; Mon, 09 May 2022 08:14:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49852) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22a-0007Ng-FH for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:04 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:43791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22Y-0001GV-Hg for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:04 -0400 Received: by mail-wr1-x431.google.com with SMTP id v12so19069501wrv.10 for ; Mon, 09 May 2022 04:59:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=QFEFHrp8GnfgbZp41x52WMf8dTsWr28zOIoNVlzdXik=; b=nrADNp01sOuN1uEPaP6mfcXcHIQhZF4ZHH7O6iVuwNea0zRThtjthiH5f7jRbQDiuW Q6m3q6rrOl2IrU2LtKLJx9hBfVAdiYEaTPbY6lFp2aT+JQVDBACdt31VizL6NsjpFITk xLQ56oEyfg1Z2ty4X0OPiSdpPlR66kx/N7U+jJOl0Efr+m+P19baHddpIiDMT6i61usV iqSJyWNauqpFxQ0/C/6lqUUTpOOW8OudkW2t0MdjJLv3I4uZyWsR4DTAlYtKxzWkCOkL HqhEMFPes2lF60zEz+FaBYCxp/JNPpRZ3pgzFF+RpO7wBzqLQSn95nQRPyY4uOXjDXKk UcEg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QFEFHrp8GnfgbZp41x52WMf8dTsWr28zOIoNVlzdXik=; b=LUQUWbR1DxWD7/+Z0nql2R9Y9YnCKGVgM3cGZx+o5Qw97CoCYTHhSFWUJpDUABnUNZ e1sQQt4jxR7LC5w32OdLu7AyrQYDmlAs19ChMa8WXAaR99mQsZwpfrsgzav+N/7gA2Vc JbtjUaKh88qbrq9HIi7zxqiqkmwATejDMczK2pk9fLieBXhYukq1jDEolV9/PKAKY2rC bmXWqDajvnQAXfHEz8Zdte53IZxBXevf+PP+2NQ5xnJYcYvacU3hMVLyGbkWvoDkEdvl sq8FQ05q8hXNcCcuV3If6LdrSfUMr+WqD8ofrqXeAYtXZNRTiCF3AMam+iEZlb2ZOmLm 5EbA== X-Gm-Message-State: AOAM531nZ9MFry/EJdqI9Lku5Lp2Rgg18Vh/8BlK2tz4uRQ8IIIWX1YX udrQ9zWYxiA0eD6okMCf0jDKz5IUDTa6vg== X-Google-Smtp-Source: ABdhPJwaAERPBDHdonrWuKvRs0iBwNcpiGQjrrwpDP2jZfVLWeUqTlxx1LfCipyWM+UsNrZ6oEdpqQ== X-Received: by 2002:a05:6000:1f91:b0:20c:d301:2a57 with SMTP id bw17-20020a0560001f9100b0020cd3012a57mr228677wrb.400.1652097541638; Mon, 09 May 2022 04:59:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/32] target/arm: Add minimal RAS registers Date: Mon, 9 May 2022 12:58:30 +0100 Message-Id: <20220509115848.3521805-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098498504100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add only the system registers required to implement zero error records. This means that all values for ERRSELR are out of range, which means that it and all of the indexed error record registers need not be implemented. Add the EL2 registers required for injecting virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca01f909a86..a55980d66da 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -525,6 +525,11 @@ typedef struct CPUArchState { uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ uint64_t gcr_el1; uint64_t rgsr_el1; + + /* Minimal RAS registers */ + uint64_t disr_el1; + uint64_t vdisr_el2; + uint64_t vsesr_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b31c719806..37c5e42bc08 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5980,6 +5980,87 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, }; =20 +/* + * Check for traps to RAS registers, which are controlled + * by HCR_EL2.TERR and SCR_EL3.TERR. + */ +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + return env->cp15.vdisr_el2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return 0; /* RAZ/WI */ + } + return env->cp15.disr_el1; +} + +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = val) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + env->cp15.vdisr_el2 =3D val; + return; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return; /* RAZ/WI */ + } + env->cp15.disr_el1 =3D val; +} + +/* + * Minimal RAS implementation with no Error Records. + * Which means that all of the Error Record registers: + * ERXADDR_EL1 + * ERXCTLR_EL1 + * ERXFR_EL1 + * ERXMISC0_EL1 + * ERXMISC1_EL1 + * ERXMISC2_EL1 + * ERXMISC3_EL1 + * ERXPFGCDN_EL1 (RASv1p1) + * ERXPFGCTL_EL1 (RASv1p1) + * ERXPFGF_EL1 (RASv1p1) + * ERXSTATUS_EL1 + * and + * ERRSELR_EL1 + * may generate UNDEFINED, which is the effect we get by not + * listing them at all. + */ +static const ARMCPRegInfo minimal_ras_reginfo[] =3D { + { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.disr= _el1), + .readfn =3D disr_read, .writefn =3D disr_write, .raw_writefn =3D raw= _write }, + { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_terr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, +}; + /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should @@ -8217,6 +8298,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_ssbs, cpu)) { define_one_arm_cp_reg(cpu, &ssbs_reginfo); } + if (cpu_isar_feature(any_ras, cpu)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo); + } =20 if (cpu_isar_feature(aa64_vh, cpu) || cpu_isar_feature(aa64_debugv8p2, cpu)) { --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098686; cv=none; d=zohomail.com; s=zohoarc; b=MFFQXT5sC4f2RH1/k0v7W+V05VXlr5DXEe/6yM62w947YoWEBwC7Lkm9X5Oj04VGxiGT0rM7owUxx1q2L7i9wTv1LOizTJD74tax11Sukk0X1D5hyxMLz4MXmGvhL0JecRsG3AamC/cIjvFXuSY8l4j7vJTV0lstl/TxRGEn7U4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098686; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7pySLzbCv+tkaUGvN3VNAC3sQSHs+Dm5J6SjR0nFzKc=; b=n1uYTu1ARn8AqeXnZ2Br8j6BnOqfd6WPWPfICKXnSzcbsqGzI+X69Tn8tSwZFbMCUxfAeHbB3XmrAc/fFuEvTCS8EfXQyLWgJ0qWOiDOYP57HUs64gf4HrZqya8eoD+9o33YdahpoXDhe2048yc0gBm57Kv6b2BkBs7LFeuWF3Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098686591403.2036778340532; Mon, 9 May 2022 05:18:06 -0700 (PDT) Received: from localhost ([::1]:56230 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Kz-0007wL-J7 for importer@patchew.org; Mon, 09 May 2022 08:18:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49872) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22b-0007Rv-FA for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:05 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:45750) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22Z-0001JH-Mu for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:05 -0400 Received: by mail-wm1-x335.google.com with SMTP id m2-20020a1ca302000000b003943bc63f98so8121477wme.4 for ; Mon, 09 May 2022 04:59:03 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=7pySLzbCv+tkaUGvN3VNAC3sQSHs+Dm5J6SjR0nFzKc=; b=s80sxpH91V2tjpTaxW7zK5aY/KJHza9mQ1FiaVeT9qCwfLi6mZ5oglve8Ep3aynca3 p1+MnmAhDtcmKJtkE3IeUeB8PoQD9ttItzlUWiCYrZ5fsQSK/c7SvDfgX7ZUiOB7DBeR dzklElN8uZ1xD/M5yo33KxfWX/hQ2lWjmIlQgoG1OrBUkZkwQKhbUxK/7YIXIjCDGYw/ 0k2ndYxnnLXAbEXUuF7l/qRui5w2D9Dv82faX5S0PMyhAH9lgdcvnJzeHO5RC+cJ/t+K NIvsHm2qcoKvmLcnE2jOrE2H0MHwcwaeIqYAdQFPTk1bqdBT3qXsefBpCiNIMV2iSS7n a2Cw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7pySLzbCv+tkaUGvN3VNAC3sQSHs+Dm5J6SjR0nFzKc=; b=nHi+2Gtq/dirKtEUcCWKXsgt4UkaOI9PBjgfpDhJIQK+eYer6LGj/vncSvKfZbHYIw c53EbC4os/woKb1hl59feO4b8vj0T0ayhlXwlXLwITGbP8wNV+sQhe6LSciwvftRX4hM rcv/YHJbt3eInf4HWoVgxbvZ/DsxirauSwWqVW//yuZfHQLIfnL9nH+Kw/ZHOnZ4NYMs MA/TZfJ8wQEUac6dke831yZZ2um6AOGr+HbUG4EeMCZeR0ETBQ2IhUnLyCIudXTGO0vs be/PkEgH8OCC3bjeW4urOW0pe3OH+CPRkRDbZtjdOqyi2Z9tOz+34iu+ipNtD2xS89mZ dJhQ== X-Gm-Message-State: AOAM531LrijgMagIYwiL4fnjRn/i3iIc+w4ThNB9N0EPEW+OyIlSgRXZ 4YB3ojC3kKpLx6UsyCX6AVgOYoi7zyt4Ow== X-Google-Smtp-Source: ABdhPJz8mTuHCcmBh9+WOOEvZ8b8nZyoP5uFWMrrxqp55JZtM74zHQcxaIfK1syqrJC1GVKiBybGng== X-Received: by 2002:a1c:f30b:0:b0:37b:b5de:c804 with SMTP id q11-20020a1cf30b000000b0037bb5dec804mr21958884wmq.166.1652097542369; Mon, 09 May 2022 04:59:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/32] target/arm: Enable SCR and HCR bits for RAS Date: Mon, 9 May 2022 12:58:31 +0100 Message-Id: <20220509115848.3521805-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098688616100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37c5e42bc08..b6faebf4a75 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1755,6 +1755,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } valid_mask &=3D ~SCR_NET; =20 + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D SCR_TLOR; } @@ -1769,6 +1772,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |=3D HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098696; cv=none; d=zohomail.com; s=zohoarc; b=TueT+i7bQFQxVIRFetj9yTbC4TwPcYhGarkOuiy+N8YiWCTXHfD6ECg19sAm43kuad2vaSv/Gp6have3BjxPtuO727oWnXtzEq4dK2R/SQ7eLcNDloda5gqh+a5HY1eXiXhBBDEa6MujCiF+LjarM3exHLN8bfrNm7BnF+PhaFg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098696; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=h2fvx2tQiDpuY8jz1XT17Zp34OPniFEINsNj/DI0Pqc=; b=ZsJ+LaXqEa5y5GcHacEHwAYFKuSMvqmeJPrnI6YmQM87k6Ce1J/CtQWuTjh9cy/V4QN4PJly0p/DN1dijaTfUDTp26a23rytaQmbTeqxflLfxYdRS/FXw3CFMQUANc7lrdsFZE/C5QoouL4tYGrpMnICvDxEFACnBPvfCumCfMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098696161527.5432515173216; Mon, 9 May 2022 05:18:16 -0700 (PDT) Received: from localhost ([::1]:56540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2L8-00089s-Ta for importer@patchew.org; Mon, 09 May 2022 08:18:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49904) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22c-0007VR-Ka for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:06 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:45739) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22a-0001JR-Le for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:06 -0400 Received: by mail-wm1-x329.google.com with SMTP id m2-20020a1ca302000000b003943bc63f98so8121506wme.4 for ; Mon, 09 May 2022 04:59:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=h2fvx2tQiDpuY8jz1XT17Zp34OPniFEINsNj/DI0Pqc=; b=S5WsTObh8gIUMIGjrBSg5/qN3xTcHAoUYuWnNiFBEcvGyDxPSn2EY5dJKoP8vZCGVp fp0TtNa07/kiYEiyZxdtlGTsM3oSus5GCOed6axJmlVu688lsh0JIz0+63BToBbCNYjc B9DT1uxNZSveASiNuf1B6T9hjjwRpeS0c0XirK2cQzklztm8pYBa0U/gtKpeol7f+g2m DbiBrlaLg0K0Q0JJtB+f2hoeZybmS/rT5d3VQtJcqQMkK8DD4eq5uU9mCWGP3/xt3apF 7vPxVYnFfZ/+MNz8baau/iiDRQiNP1rpmSqcuizt7x586NHHNEmMaLpNtQvvNsuMlG33 zeKw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=h2fvx2tQiDpuY8jz1XT17Zp34OPniFEINsNj/DI0Pqc=; b=4JNSrIi3hXk+UX4c+8eFM58rQ9OcqxYv/HwAISJQOkB8wRjuu8uYErLIxT7jeyYJsC gsVAiaYYCy6CMFj5LniTk9FVX0NTeAu5cnKe5MJTwFhE8QluzmIBV8ZncQYsDMegMD+k 0Ap8sC5moGMJtE28FLemyYawdSu+lxGpFX6cwqi9WchhXI80LkMOu7ge0WlYCmNobpoX qf7w6B2cUD87UQld5N57j+OcWvxmW8UfMGlbDIX4APl+SBFagy4B61UiXgOukJ4EOgZQ LePAIFRBe/KS9euIeAykIzKOef76AxYZwSps0QoQbnXlawSIa5+DjdepAsTjYck0RYK0 dE8g== X-Gm-Message-State: AOAM5328W4jeDKsh9/yigOmPXz+ZLKBX7VmeghpyQfXdptpSICEojGcz MF8S48lh2rRRVoYfcWWb1hxkO/MXlEf5Tw== X-Google-Smtp-Source: ABdhPJwCORZzch+UtI+TFWEX6NrLfCkcoT6jwsEoggDVmNTUK0fP5wPkJJBL/ZayOXnSiq+a72ImSg== X-Received: by 2002:a05:600c:35cc:b0:394:7b56:ef38 with SMTP id r12-20020a05600c35cc00b003947b56ef38mr15199685wmq.34.1652097543234; Mon, 09 May 2022 04:59:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/32] target/arm: Implement virtual SError exceptions Date: Mon, 9 May 2022 12:58:32 +0100 Message-Id: <20220509115848.3521805-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098696486100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/syndrome.h | 5 +++++ target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 91 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a55980d66da..aade9237bde 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -56,6 +56,7 @@ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ +#define EXCP_VSERR 24 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -89,6 +90,7 @@ enum { #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index c563b3735f2..6ca0e957468 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -947,6 +947,14 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit + * + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, + * following a change to the HCR_EL2.VSE bit. + */ +void arm_cpu_update_vserr(ARMCPU *cpu); + /** * arm_mmu_idx_el: * @env: The cpu environment diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8cde8e7243a..0cb26dde7d8 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -287,4 +287,9 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_serror(uint32_t extra) +{ + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2667aaf28bf..652a84cf849 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -85,7 +85,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } =20 @@ -511,6 +511,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, uns= igned int excp_idx, return false; } return !(env->daif & PSTATE_I); + case EXCP_VSERR: + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_A); default: g_assert_not_reached(); } @@ -632,6 +638,17 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) goto found; } } + if (interrupt_request & CPU_INTERRUPT_VSERR) { + excp_idx =3D EXCP_VSERR; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + /* Taking a virtual abort clears HCR_EL2.VSE */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + goto found; + } + } return false; =20 found: @@ -684,6 +701,25 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vserr(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index b6faebf4a75..4857d2dbb80 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1863,7 +1863,12 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) } } =20 - /* External aborts are not possible in QEMU so A bit is always clear */ + if (hcr_el2 & HCR_AMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + ret |=3D CPSR_A; + } + } + return ret; } =20 @@ -5175,6 +5180,7 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) g_assert(qemu_mutex_iothread_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); + arm_cpu_update_vserr(cpu); } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9331,6 +9337,7 @@ void arm_log_exception(CPUState *cs) [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] =3D "Virtual SERR", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -9843,6 +9850,31 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) mask =3D CPSR_A | CPSR_I | CPSR_F; offset =3D 4; break; + case EXCP_VSERR: + { + /* + * Note that this is reported as a data abort, but the DFAR + * has an UNKNOWN value. Construct the SError syndrome from + * AET and ExT fields. + */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal, }; + + if (extended_addresses_enabled(env)) { + env->exception.fsr =3D arm_fi_to_lfsc(&fi); + } else { + env->exception.fsr =3D arm_fi_to_sfsc(&fi); + } + env->exception.fsr |=3D env->cp15.vsesr_el2 & 0xd000; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", + env->exception.fsr); + + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + } + break; case EXCP_SMC: new_mode =3D ARM_CPU_MODE_MON; addr =3D 0x08; @@ -10063,6 +10095,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) case EXCP_VFIQ: addr +=3D 0x100; break; + case EXCP_VSERR: + addr +=3D 0x180; + /* Construct the SError syndrome from IDS and ISS fields. */ + env->exception.syndrome =3D syn_serror(env->cp15.vsesr_el2 & 0x1ff= ffff); + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098864; cv=none; d=zohomail.com; s=zohoarc; b=iBm9CrNsVQjhLjQ92zHKI/Me4mo6+1WT7gZb4zx5kOTK5vdLG7LGSgBz8kG/+yMTsiWOTERS9npVpaI4+AdQU102VrfYxK7grwsyCoLutKJIg0b2Kyy380AscxcneRGVhyY3h8SCJQU//jYwRzyG/6K46KeUupzOQQF8/+O+ICM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098864; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=1JiIEt3yGg5HPcE3kQ4SQjm2oZBNqFx24lYyJ3rca6I=; b=Txm4Umu21/tstmygdPi1TloZ4HVcpuAvCFQ6mufQz20faG87pB0fnHhG+aIuiF9L28pmbRogzP8yLuHBjDkrntb38GvQW+oyUq/Ax+Y4+LBGnz9KWITexA7sPMUOqSSCrUVX7c8jeJ5YNROZLx8iiXtfnbYc77O9vTksvcxocD0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098864325657.6101637719036; Mon, 9 May 2022 05:21:04 -0700 (PDT) Received: from localhost ([::1]:35384 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Nq-0004TI-OD for importer@patchew.org; Mon, 09 May 2022 08:21:02 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49906) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22c-0007WQ-TX for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:06 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:45640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22a-0001IW-UC for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:06 -0400 Received: by mail-wr1-x42a.google.com with SMTP id w4so19070775wrg.12 for ; Mon, 09 May 2022 04:59:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=1JiIEt3yGg5HPcE3kQ4SQjm2oZBNqFx24lYyJ3rca6I=; b=k6a6FnzjtuLxRa5xTeEomWQuTq6DPNw8ibtIjtsBC9NZ21odfRDf81YqddlqA5y/xX I8UcBLLPPWON0VfPeNj8QlqiG2sBRjvNhmSOuIsq06f7c7XXj5Dya63DEo9n/jAtB8Ek FLkMEAmw2ub9UNELvGb/P6sSwtiJW03qfxWTY/Bm5VeL5zgMzxiEqX6MNUiHk5ifLhI6 aXgkdvneKrel8+ooN9IfKl0SkKTbXcMbUiFPm8+OstpIhUNPdV6g0V39PxYLGvQJ//C+ vz5Hq0YbzJMccixSZxwUt+KzG7/Ppy5dfjOA0dBpGcdMT5aBIwJC+MxgHco43aSLEzyD 2OUw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=1JiIEt3yGg5HPcE3kQ4SQjm2oZBNqFx24lYyJ3rca6I=; b=MQ5Kj3oFOnZIEH4a7L2MOKTxf7lcJpbRLLE4hL4T2bd/6nxC4TxyBAxUYH07t5Kl/9 SSAWEPAAqXy83TEdLbngfIFduewe1IlUjR+i2LQySqv147AIMhMJYodlGyQTNaAz8OgN WpwvJXTRBFbAVlsSYe+DgGzQcsGjWO1zZVmxa6mlVXpGcNtxTd+fbz/pis7RzgRqfWeD CmPhlNMQdTak3YovBt5Pxqch8HG/hhoBfOrp0BSjNWpUfYJ+smi2J3PADix7YU7IN+ZI 9S+lU1LCv+nii2F0l0rHjdYrbj1E7OAkR/on+FtqtYiAX4FAj2NNNXzyHWmI4JEisU3J sQbg== X-Gm-Message-State: AOAM530mBWMu3WTytfYvkEh7FAnRHCMeWG/ASWsdhhH2QfqJB0+jpF2y 43DF3F53chQYhklSAMhBFomoTF6z4T1YpA== X-Google-Smtp-Source: ABdhPJx/aI8PgXmA+9tz5Pm5lKvO+q4B3O8CrPQABVGynC5dP0cxlh46442WDhR2TImoxQhW5yYhcQ== X-Received: by 2002:a5d:598e:0:b0:20c:57ef:6083 with SMTP id n14-20020a5d598e000000b0020c57ef6083mr13535905wri.457.1652097544166; Mon, 09 May 2022 04:59:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/32] target/arm: Implement ESB instruction Date: Mon, 9 May 2022 12:58:33 +0100 Message-Id: <20220509115848.3521805-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098866403100002 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 ++++++++------ target/arm/t32.decode | 18 ++++++++-------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 17 +++++++++++++++ target/arm/translate.c | 23 ++++++++++++++++++++ 6 files changed, 103 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343bc..b1334e0c42e 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d9..f2ca4809495 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d62..f21ad0167ab 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 76499ffa149..390b6578a89 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -960,3 +960,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +/* + * This function corresponds to AArch64.vESBOperation(). + * Note that the AArch32 version is not functionally different. + */ +void HELPER(vesb)(CPUARMState *env) +{ + /* + * The EL2Enabled() check is done inside arm_hcr_el2_eff, + * and will return HCR_EL2.VSE =3D=3D 0, so nothing happens. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b80313670f9..5a02e076b7f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1454,6 +1454,23 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index 4e19191ed5c..87a899d6380 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6239,6 +6239,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* + * For M-profile, minimal-RAS ESB can be a NOP. + * Without RAS, we must implement this as NOP. + */ + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s))= { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch32.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098865; cv=none; d=zohomail.com; s=zohoarc; b=P/CE58d9iRaPJ3dDuFnVndeNgU4SqEp/A9wRX24SDhMeaYhyAyV83soJArreSgCI04JhTaL6xa3CvMvRrzRKt5GeObLAvx0z+5fO3mPPB0pV4zf8iV8hzGvSdU3dGunADalt0Wv5nfhP7B6hWQhTYMbkKJX1vuLq0W5vjCWpit8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098865; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BIbbh4ECZCDM5wPUP3NeE8Zmw3wBRxjd4KnilvrbrYc=; b=aC8ag6wdCkikahF0NKi47uI4LnJ/zedvhVHU0nyoTvEwjVUBj5LSqfjZq+p+/h+NlfkemcEeKGZYZw2CHg60A3Jv562yS6nZ9xTxhCh5aivaKI2W9Z86Ash6yKlRKw/d2yyLToL5545grncrunsn08iuNjzm/S+AmfV828rLSHQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098865392488.9313365318085; Mon, 9 May 2022 05:21:05 -0700 (PDT) Received: from localhost ([::1]:35566 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Ns-0004bE-3N for importer@patchew.org; Mon, 09 May 2022 08:21:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49946) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22e-0007YQ-6L for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:08 -0400 Received: from mail-wr1-x434.google.com ([2a00:1450:4864:20::434]:39677) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22c-0001K6-By for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:07 -0400 Received: by mail-wr1-x434.google.com with SMTP id d5so19112727wrb.6 for ; Mon, 09 May 2022 04:59:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BIbbh4ECZCDM5wPUP3NeE8Zmw3wBRxjd4KnilvrbrYc=; b=OmaCwLWEqQ+U8KN6P9vWnPRQwLuN/khdFN6anC4BYUI9w4U1PSQqNyYKtaTR8nDBBQ Q//Kw4L6085U/EQfb84cUhWIO/sJTUNQ8QUgjf3Se6UXSlVMeksX61TjNWfJpdEBIua8 92i67BUHkpob3rEMs2DBcrrUihCfz5/o04uH9Yb7Gacm0ekydKzO03kcgSfrNYH5xWJE JfYeOywi/4HfR/jXm3hxeEp8HxpCnftPr6af2yMPivqNnumKuRGLa/JGT7s9VQAKLazA u7Gjxtbbx5e7Bz0MpLXjMu2hbEeij73E8vRlKJNdb73AHE8LFRvRv5sc9qAEpe+jK+Dv ISfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BIbbh4ECZCDM5wPUP3NeE8Zmw3wBRxjd4KnilvrbrYc=; b=nbGO2BLRPTMukdlYaJJRVVXHA0bQ2XdaamMz/oxtOe06IKxhMKr9Ws7IJJ7jJNQtIT AUVtkvu2VqdK2GpkeqhEHA2ngCTB0bGXxboSKgjaM4VtsJS1hh+/lL/m/NFoSj1iBdmR CvKdzZ4e2p2m83pnPBlOFzAykfyYI+BXROa+9e0icD8Usbhl0JK8C8Ui8yMNGYuuJ/EP NjofsN7PmTp7duDKei+iTrx4RDsB85Gwun4FzNhd1HzRS+r0KggZQOd1LlFgidKDFEv4 yV1ZuiQvfVyhoSITyQNmA3uAPI70n/IFeJ+edsub3KqYRPf/TyA2T6wIbnAQrwMgi9RY 3TWA== X-Gm-Message-State: AOAM531/CRRCip+yVYUVhbvqoDoe03Lk6tiWVWEK8zMNlv0+vKpXf5J/ DCBx+X2O8s9WL7a24ko/w+vtDCeupnJDUg== X-Google-Smtp-Source: ABdhPJxtxT+PU62nUtaImOop47nS50qvcE8jvxSxVsHeB5CrpiMf3wOPqDPhVhSUlyrXtl9ikTc5Xg== X-Received: by 2002:adf:d0d0:0:b0:20a:d93f:e252 with SMTP id z16-20020adfd0d0000000b0020ad93fe252mr13546232wrh.78.1652097544917; Mon, 09 May 2022 04:59:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/32] target/arm: Enable FEAT_RAS for -cpu max Date: Mon, 9 May 2022 12:58:34 +0100 Message-Id: <20220509115848.3521805-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098866389100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0acac6347c5..81104080003 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -42,6 +42,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_SB (Speculation Barrier) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 88d3cef93e8..35881c74b20 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -744,6 +744,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 337598e9490..c5cf7efe95c 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -69,6 +69,7 @@ void aa32_max_features(ARMCPU *cpu) =20 t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099091; cv=none; d=zohomail.com; s=zohoarc; b=GkLS1Yz36AE6QF7FEIM+tyquG/qyDg4pwvCHQT8yALZ58l54I5fumNwaQuU1MXfqXY2kfcMuFGsRZPes7S+iyymIa7AkSvIgSeEX7nmdz6Jr/kxw7RloFtwg28UwyGaxNWXn+lfYLz15BVywki7Q0LWfg9mm5WKFZbi0lFYnu/M= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099091; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OhRdJfnini9q7/jjQO5HIr9d+z6cd7iuez+VhkZ7LaE=; b=eNa+5078diVo1v5hhvSqm0bUAsb7a+ycYGXndIGNduT7mvbZiVnRgErqO7P2roPcEjcXL30edwFl1bkoyaFWQwvdnS599HcDDJdwIaGmMkW3BbcF6+Rke0Ua4YsRSe4oZci0jepNr0bjpnqCTTwFpTN1GkfGeYSX04aFkx43So4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099091105547.9436271820758; Mon, 9 May 2022 05:24:51 -0700 (PDT) Received: from localhost ([::1]:42114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2RV-0000qS-KF for importer@patchew.org; Mon, 09 May 2022 08:24:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49954) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22e-0007Zw-Q5 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:08 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22d-0001KE-4k for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:08 -0400 Received: by mail-wr1-x42f.google.com with SMTP id c11so19084579wrn.8 for ; Mon, 09 May 2022 04:59:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=OhRdJfnini9q7/jjQO5HIr9d+z6cd7iuez+VhkZ7LaE=; b=kEmkA9vK4xkoYPXwWkGpx3j3OSYeHGJbvjI2STEhovWpPHgkZXe+yOVysKeT34kFDW pz2MoLeyNIowaTDYaX6gSxmHLPJJIHziDADiiO/nmFakOFyT6RDHpEftT6Tyw+LQvz9A leKlpQhczJkkzv50xroaPz7cECzFBkyF+Du5Au+Vtb6H5REPl20L08yNrl++K4tiqT0Z k5WtCQwOfwrr2zevmsTBaa12COxaESnE2aIrY0l35R2cgcSgWQOhaeHtWJGOsuuM8ZWo fM8KAwF3+8Fis/A/fCcPhADQj6tQZqhFFJPu3IDnFrFf4PV5s+3a1hnrIqEHDFAmq6qd JnDA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OhRdJfnini9q7/jjQO5HIr9d+z6cd7iuez+VhkZ7LaE=; b=axuyVYSIU9tyqKJwDgGtLp0KRiuIBGbE/Y2z0oxoYN/MfMO1gn5KAtEsaDg6GDMtor zpohSI4k8yFtFv5WOS9myxQT2yzCbZyIfSGAR1hUz5gYoz5cxX98npgDju7scj0ABRyh xpRwbv5nBImhBS2peCxANKowZ93NifK0CC2ALb+qiDUq1EieINEnM93mjjvamV3ACeE/ lttk74TPgYUjDc4SSV0sS5o6kTK2fIh31LabXQVoiSpb9voUcP2BDgqH8fET/326VT0J F+ULP53yRIFZyEJG1ktGH+0+YPsAzPvYGEZ0zZcIBk1VH1yxwk1jm0WgF7wnzrAnlIe6 VuPA== X-Gm-Message-State: AOAM532nS6C9Yo3hc3awA2EtitGck4ufF9U0JYvNNn6OJic2sREzaKTh 66vpDwCrBkpuDHJEwg+WDkbUXwjYTwC9eQ== X-Google-Smtp-Source: ABdhPJxPSnAovJumKE4gVp9Anfyu/ylkJ8p7DM3Pqpx5wJ58y0YCD+Hzvcwx9PwqSr3T/1yn05W9Bw== X-Received: by 2002:adf:f40c:0:b0:20c:c5e3:7e12 with SMTP id g12-20020adff40c000000b0020cc5e37e12mr4992467wro.1.1652097545762; Mon, 09 May 2022 04:59:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/32] target/arm: Enable FEAT_IESB for -cpu max Date: Mon, 9 May 2022 12:58:35 +0100 Message-Id: <20220509115848.3521805-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099092755100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 81104080003..b200012d89b 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -25,6 +25,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 35881c74b20..10410619f90 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098356; cv=none; d=zohomail.com; s=zohoarc; b=EoF+iyqusKTtR8vk9THSnRTMtBTEhTX6v0ewJV41EBSGfwFd2lcGE7TrnCEEwQMoPGUl60u84BmlWhQgOle8w5Nl8shTPXJKPi9Sp5N/QrzH7t54P7I4ekf5sQiB2bT01FWVWVKaPOWXsmJ4WeejV5BbWXb7miff5VbnQBrIo4g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098356; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=almVrNVpuLpoIepWO4cILFV+4VahPiB3xxYGOPFdNE8=; b=Oo7wHKqeVkzOBXJG+NtoIhFHbKH3uhFstX1xZoqCM0+EPmiHE+hkdA8iLGLkWk5LTynh16goBsnh9/n4zJ9gEBLtWbGxqlMyNMBk6wdL0XJx05qczFxxODgRw3it57VmcwsPrwhqwrW1D2EdqXbl2oKv8Pqeclx7Zr1/tww4K8E= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098356190383.0460031906624; Mon, 9 May 2022 05:12:36 -0700 (PDT) Received: from localhost ([::1]:42916 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Ff-0007Qr-46 for importer@patchew.org; Mon, 09 May 2022 08:12:35 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49956) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22e-0007a4-QV for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:08 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:37625) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22d-0001Ga-5Y for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:08 -0400 Received: by mail-wr1-x42d.google.com with SMTP id t6so19116578wra.4 for ; Mon, 09 May 2022 04:59:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=almVrNVpuLpoIepWO4cILFV+4VahPiB3xxYGOPFdNE8=; b=NjffDT3iobI943d2HUI4yACEbIYkLq7x/n5WyxYoWnYJVao3PWpnxQXy0Pj4FZKv6e PmORjCjNvZt+icfquGi+tzSJFg1AHDhxig36AF8VbB1sTkfMATVQW1o2VxU5ETcJQnL9 L0pyhPt/RJ7c7sQ3Ll58V0IF+npwaXurC69tBWBALuJ26nvuraMCg6i3H7XzdUbzXQTJ vKuPyINM8OjPTqLhByAfcx34R3foN9hw0dKta0msnOdY/PJWDvYltXgelRAvQoo+TFTc wDxdvn2fprivszOTVL7Gm2fyOXCeaYJ4tTIUHDBJ0UqODn0sovh7q1poDtKAaLymJ71Y ugKg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=almVrNVpuLpoIepWO4cILFV+4VahPiB3xxYGOPFdNE8=; b=CBuLuB4NFjl1CL/Fai2iQ4JdbYFRBi3i5z4XXnu5CNZPioAG+L6k+ofAaDs5AuQxM0 tIwAcvSZnn+FSAM8xGQfwgO877YFmiU47HF6GLQLjZzCxKYuoEj1Q/ZjXbkpxrv+OvS0 JfV23a1iQrTjP5QDHljQpJO68bKecSmTjSKq7LDoHEYKfrHY3xpXz6/lGNKG/v4X4KUR ML6UmmIkJi6Yu9HNg5br3WpiuHVRwmAnK5LmzjWI6oYx2DIj34l6sFL8VTM0cGWgIrue 2z6obZbUYmP5m+iYjL9PTjVsZwWgpofVvJ0bgJJ/vyQVWI5g0nWZDNRyDifS07GxGBs5 BPow== X-Gm-Message-State: AOAM531XMJcPjvQJPaIXdk/qHvVt8fHHYU2aAPxLrcUe6bf/F0msVIn7 qCwNrGTF6bfMLTdmXh2DWSS6xKrxj6PA7w== X-Google-Smtp-Source: ABdhPJzHvUcqqgCJs8YDvoZCvuERGLzRDMk7fDas2u7w2GzQKfbjhspl6SMRCLA9g/PMasjkmHLtgA== X-Received: by 2002:a05:6000:1810:b0:20a:d512:96b9 with SMTP id m16-20020a056000181000b0020ad51296b9mr13450377wrh.611.1652097546525; Mon, 09 May 2022 04:59:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/32] target/arm: Enable FEAT_CSV2 for -cpu max Date: Mon, 9 May 2022 12:58:36 +0100 Message-Id: <20220509115848.3521805-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098357112100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b200012d89b..b2a3e2a4373 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -12,6 +12,7 @@ the following architecture extensions: - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CSV2 (Cache speculation variant 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 10410619f90..25fe74f928b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c5cf7efe95c..762b9617073 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -68,6 +68,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099309; cv=none; d=zohomail.com; s=zohoarc; b=Bys10XKe2jX+mtrKe+CLPw3M+Hm8oaolou+ZhCyTD9X2t1VfHmLfloAvaMlm399LJE8CusTrXBSnM3yQjjlmrRsMBtc4a7OInP0uAQOzalf2+kWShV8rkIYYYlygkWLuwQ/ML/ic8QcH/lFUUcoMSQa7VIn2HbB8KE5pt+guzO8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099309; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/KwXv4BlDQuOReLyYKnpu/uH4XylEzL/YqcY+RA23x8=; b=B6+E9g+Cgf6qC0Iq47WioxwBPaRfQ9JyTQA7Jl/6JfGU3YLUPG1343tRLG+8NIOZHYJDDJxhv5S5pPK19h8hAKiIAQPkXk6ugaStG9S5Sbv703ODXsCzLi57hQcCfObqKg+q2gz6VwtqMdT6EvhU6Mm6/+IORoirMds15AQ7PqI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099309588194.81593507129605; Mon, 9 May 2022 05:28:29 -0700 (PDT) Received: from localhost ([::1]:50858 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2V0-0006nL-Nm for importer@patchew.org; Mon, 09 May 2022 08:28:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:49978) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22g-0007eW-2J for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:10 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:38580) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22e-0001Iy-5G for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:09 -0400 Received: by mail-wr1-x435.google.com with SMTP id k2so19091116wrd.5 for ; Mon, 09 May 2022 04:59:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/KwXv4BlDQuOReLyYKnpu/uH4XylEzL/YqcY+RA23x8=; b=ETsqwWfYKvWmDa5OL3G8up9XfzlBpw+oToiaPw4dc4y52V/GFuukZpheq3XgDNUxmn DiaSw4fVg3SBJDypqxr6FktDPxupl0BexD5uKw3YO5CF++5Ejqr1QtYGR1bdRJOnECi2 GnMDy4cZQ9SJz83VDXqYx0PM1dj3nxKNlG49JXqCq26VmU0ZQfuIho+zHJwR632b274u 0c3uhLM5TaCqm/HY9tNGDKiBQ2F1zrbvrBzsqub3deR6JMRS82WQwboAJ0znLQ+30M1c TNBjrylh7cvFaBLN6Z2Aj0aDrxAxZ8rXAGUEoukMoLfg/TtW36jQoAlOzlpyppsQ2NWv SGCA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/KwXv4BlDQuOReLyYKnpu/uH4XylEzL/YqcY+RA23x8=; b=pqMq9dFKhV4IkNapyyiAnYx/b4xvGM7covwlpJGUkgViZ8l7UIf1dAdkRUHh1ggDgs VOt5zwgJbd71pYXREo6xU0R0Vwy9tK5NukIogtqd/igU53KoM+taggD5LqjLwMNI2cbo DUQKduQ2PeLnGWUi2aubKGZhB7n0MZbPAloHXHOH7O8RvgZGj26bgBqTg+poQC4Ap/qc tT7PV7IDnb68rZl7179XADLJXnibVwEHFKSnm6WZw3rWzmSAAOkqkYa4gD0VSjrq4KlT 7JYbBHsi/4hUnURAZh7O/HqDaeAOg9bPbUmnWoeQ2wYEr5EfjXtlEdyVl4zrK0FSgFBd /bDg== X-Gm-Message-State: AOAM532fErkVubxGubHstscAmvQi57TbADRKa7qLOeZ0reCvtODfSC// x7Cr6qVNSpIwqLXEuSAtqYCONXwlzIn/8A== X-Google-Smtp-Source: ABdhPJzEyFJz4C4gvvICc2PoIrUyRisw4R5XwgPYpUAiusKzJgzguOOR8tDKXgy3mOso/tRy3x4PPA== X-Received: by 2002:a5d:6d0b:0:b0:20c:4ecb:1113 with SMTP id e11-20020a5d6d0b000000b0020c4ecb1113mr13323857wrq.203.1652097547421; Mon, 09 May 2022 04:59:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 21/32] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Mon, 9 May 2022 12:58:37 +0100 Message-Id: <20220509115848.3521805-22-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099311975100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-21-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 16 +++++++++ target/arm/cpu.c | 5 +++ target/arm/cpu64.c | 3 +- target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- 5 files changed, 86 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b2a3e2a4373..9765ee3eaf6 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -13,6 +13,9 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CSV2 (Cache speculation variant 2) +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aade9237bde..18ca61e8e25 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -688,6 +688,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif =20 #if defined(CONFIG_USER_ONLY) @@ -1211,6 +1213,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4022,6 +4025,19 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >=3D 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key =3D=3D 1) { + key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >=3D 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 652a84cf849..59df597e052 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -230,6 +230,11 @@ static void arm_cpu_reset(DeviceState *dev) */ env->cp15.gcr_el1 =3D 0x1ffff; } + /* + * Disable access to SCXTNUM_EL0 from CSV2_1p2. + * This is not yet exposed from the Linux kernel in any way. + */ + env->cp15.sctlr_el[1] |=3D SCTLR_TSCXT; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 25fe74f928b..07b44a62bef 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4857d2dbb80..432bd819195 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1770,6 +1770,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D SCR_ENSCXT; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5149,6 +5152,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D HCR_ENSCXT; + } } =20 /* Clear RES0 bits. */ @@ -5800,6 +5806,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, =20 + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7223,7 +7233,52 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { }, }; =20 -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + uint64_t hcr =3D arm_hcr_el2_eff(env); + int el =3D arm_current_el(env); + + if (el =3D=3D 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] =3D { + { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, + { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, + { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL2_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[2]) }, + { .name =3D "SCXTNUM_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, +}; +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -8365,6 +8420,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099591; cv=none; d=zohomail.com; s=zohoarc; b=Lq/MTEKPGU09C6j78nxF6iALGqU4e3Cwoor5PnzV03t+Uw4dzp0Bd/6yLVzr/jf+M0nsxzUnpn1ym8pzPjVWKKkhFKnEBJ6w/bf3jBLVbWNptxO5Yk0vXKrL1hsuh0UbVAHSf7rm/ddarGkT33VIX4+B9Fp9nc1mqwXPz6wr/eI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099591; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=XpvaNYf3N2LXESEBCGwFXMc1KzcepH0wfVYS4gErJ5s=; b=ORwSiSfg0/fJhPOUz6GlxUGELig0jKoICtqqvPebsrJ38UGT62xifyyZXA9zTQV1UkRSP4SWL+rCZwP4pRjCFxOgoEtV8Nsu+yRjQJLOiitgBbtf1CPm0vw8vWQJ8tkg7H9AF5Q8hOBY5INt98UtregeAoGz6TJ/CZfvYLo8mow= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099591330153.42953281765267; Mon, 9 May 2022 05:33:11 -0700 (PDT) Received: from localhost ([::1]:60090 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Za-0004ft-4g for importer@patchew.org; Mon, 09 May 2022 08:33:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50006) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22h-0007i3-20 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:11 -0400 Received: from mail-wr1-x432.google.com ([2a00:1450:4864:20::432]:44800) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22f-0001Kn-D6 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:10 -0400 Received: by mail-wr1-x432.google.com with SMTP id b19so19092384wrh.11 for ; Mon, 09 May 2022 04:59:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=XpvaNYf3N2LXESEBCGwFXMc1KzcepH0wfVYS4gErJ5s=; b=QGVeTiZ2s5Pokafrg3gkaW2/8XM8++JXnXbbVh2kEoXRv09KoV0pR4M/ei1pipang+ nLdEPMv14Ud13sed276zQfP38qDisMH/wFOV5nJSrOsoXpE8VfJtrODMn3CXPxlMyaGC q/3XygSUlMCuiQLqARgSMgsIbUXcxtIgiDX9RKHV93HWGyESyO2UTNIkGUyuC35NG9Rc jUuOBEf1p31VdZt2q6qH8eL9aBvB3npYHV6bEp97xBjHW7ju0XqiD9bzyAtLaPirmVM9 KwCCYXAuxb7IK592w1hmATvuFg3FofsUagqU/DMVDhQIuDM34G/Ml02NBcBjUpy5dqzy UUJQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=XpvaNYf3N2LXESEBCGwFXMc1KzcepH0wfVYS4gErJ5s=; b=vkvyBVKsiu1TVCSngh3Hd/zjYaR5AheB/12CQ7zlYhB6ecnv+TLU/B3v6Eg9ztgxHg PJJxQhQDFPuV3vIq39CSpg1M5fS+O5wNlB2S2+TSAB3+o/izNUa1HGXROfkgEr5OAtri 6upiWul2Iz0MsMmS3n0lhwFCvYZMNkFQeQNZa7E78e4IVAvTqW8C8E9FSuk+SocnFtDC NrgQkqYYdQ+mTPC+SrL5p75evgt1X/rFLj7oMLtEZx1Q0M5c2vpoXDolZhiVXm+3FzG/ ceDO7UPqQheVzFxU3dOOensU0DUN3OkEt6NOD8AYjo+R5fLf+nQbg9qeesSGHHlcPWe9 +uIg== X-Gm-Message-State: AOAM533TCGiSTIkOzrtNBDI3jjKYxckxKfKPmDyw8nRziJsweQPi/HPB 1WQ32eyUzXulZLjIXhxXowWZg7584AClRw== X-Google-Smtp-Source: ABdhPJwfschSLve547eBVWPdOC0axP9AaQciwdLeIms6HEHIOGYv7+xoLgP10za2g/M7Ze3rUL8o0g== X-Received: by 2002:a5d:45d0:0:b0:20a:d002:b80e with SMTP id b16-20020a5d45d0000000b0020ad002b80emr13475809wrs.447.1652097548178; Mon, 09 May 2022 04:59:08 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/32] target/arm: Enable FEAT_CSV3 for -cpu max Date: Mon, 9 May 2022 12:58:38 +0100 Message-Id: <20220509115848.3521805-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099593129100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-22-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 9765ee3eaf6..48522b8e1cd 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -16,6 +16,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV3 (Cache speculation variant 3) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 07b44a62bef..40f77defb51 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -749,6 +749,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 762b9617073..ea4eccddc35 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -74,6 +74,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099093; cv=none; d=zohomail.com; s=zohoarc; b=Ma3al2iaTBdvPKxWKlZz3oD8UGHWTMkSdqYTzPK/jFVYMTOL8zoIUPCl5GssK7Odsvdvd7DvXBNdocByPkgrFDbuvJD1OW0u58ogy1CzYleBkRSBfwTTZpTeA1yEec1XBWSu65/KPQhNaGUolzbMWl4EkFl0gQlj0wxM0SIwaAk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099093; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=+3olo7e85VH/YZ4COonx8SmNnB4UzXRKEotRzbQ80o4=; b=aI1/CSxrOCIMv2QvLQ3OZE2e2AgSti/6AGsqyI7lMZ7td25+kQoFwsGlvmX/8StblsYAv9dlJGBEFJdub0EzjexZ7lfuasGhu+o7CPiHbtrh9NlMncpFwt/Yr2vbGDJ0gDMqXsWha0hlSnyA5DmDYmmJRG6zJRY870sWsDD+jXM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099093667215.38654378344336; Mon, 9 May 2022 05:24:53 -0700 (PDT) Received: from localhost ([::1]:42294 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2RY-0000xk-46 for importer@patchew.org; Mon, 09 May 2022 08:24:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50022) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22i-0007l9-2o for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:12 -0400 Received: from mail-wm1-x336.google.com ([2a00:1450:4864:20::336]:35741) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22g-0001L4-Df for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:11 -0400 Received: by mail-wm1-x336.google.com with SMTP id c190-20020a1c35c7000000b0038e37907b5bso10651126wma.0 for ; Mon, 09 May 2022 04:59:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+3olo7e85VH/YZ4COonx8SmNnB4UzXRKEotRzbQ80o4=; b=u5Vj86WSM2ffMzDw5tMtLV3nUvfOVVSQzfOE10UVk+jUMtv6oxRPkjkffdPp/rBSKo /gBFbmtUvz+xum5zvwNLny66nLOFytvSb+JqBgDKxrd3Jxz2jp0FH8ul55kQJpbA05+0 BKdlbVPeQsnVmADlvxySPYa7Noh/VKxgdcCvEwOZhTfTqcwHpk43xtsLcGIYDWsyBFv3 H05ZjTiTE+HjVTLMSHc7MmFeOmeAHWtcn/A3FUyBGz0A4NZvK+MaTMFId7/EpUpaPWzx R2Gh81sQ2YmDs+sgt1EyawqWxhUkLvHksdYxtpTvoE8oMFWOK54cojY+RvY0THNYj4ze diYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+3olo7e85VH/YZ4COonx8SmNnB4UzXRKEotRzbQ80o4=; b=6zEWJIzH48lMVhUGGHzrim62ZUS0iPHXI6IeIQr7AkorVEXgE6CAv/b9kvE8h3NaOQ Ea+rGIHdjG+cQcckPZatU1BI6EOiMcYh01O64aC6hRRiNPz+seR2qyE7NlheggbXPBrp Q3uO/bHEuxjqQwjPAkAPyLht1Ir9vro9BzRv3dWEh41XCXvvn5ySINF5HeanYk1AMs8Y 1p53t//CQXiYvpghe4AcEjlOr9LZlGnO0yX7qyNvMU9fV6eL8D2dx8BVtybHKRnv2d0S NX6X9pRDjnvfJDXChX4zixVn/cgn5TyG1NOd+UF7349g63ousTnpC7/mepDjp4buZegw V/pQ== X-Gm-Message-State: AOAM530PlZY01qIInQKa9PAg//4zqqV8ZJK83hfE9YS3vz+gkdNfLdqB 0XfpkawKQbNHHTU0K+DvKQ3SbuWQWmTSgQ== X-Google-Smtp-Source: ABdhPJx/GNEnxD6GCdIeysjmWR945Tmdq9p3xXMLUNUBZEZ6rdVdE2ereNKo9l1QpvSpzQiOSfKV2g== X-Received: by 2002:a1c:7414:0:b0:394:1d5d:27f2 with SMTP id p20-20020a1c7414000000b003941d5d27f2mr15812603wmc.37.1652097549047; Mon, 09 May 2022 04:59:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/32] target/arm: Enable FEAT_DGH for -cpu max Date: Mon, 9 May 2022 12:58:39 +0100 Message-Id: <20220509115848.3521805-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::336; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099094404100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-23-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 48522b8e1cd..8ed466bf68e 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -17,6 +17,7 @@ the following architecture extensions: - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_CSV3 (Cache speculation variant 3) +- FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 40f77defb51..f55121060dc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a02e076b7f..6a27234a5c4 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099309; cv=none; d=zohomail.com; s=zohoarc; b=b/22jQUVPOVFlMs4sxZ4UFql0jQBaR31wCQpvocMPvzxLs78gtIRSpm8HmKF9uT3/ZVy645SWlUneIQ3lSiHJs2nwrsiqxdVf7xMnmrsj/tJiuisQ490KcTeFtg3T/MeFTnrScHq5TUKdDHyoBNDgHsC9aTxMhPtH3nCDbvbWWc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099309; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/lpv2cPi1QsrCoVR7BqND3LjQ1uLgD1c9+4prWrFMIY=; b=aI+SxVAoiBq+GznQ4CS8ytSbX+VtOQkcESmQN9ipHgOxrygDlZsMMBitm2yc/VuswFrXsK/03U1YX5oYOR5xhwAxYZT9figzRR8HiJMRo+WnfU9aYVpANKHBE8FKfKYj+rypYGROEiRsRR591YzBHb/igQXx5MiZlQ5rCi2D40s= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099309605516.6202082020923; Mon, 9 May 2022 05:28:29 -0700 (PDT) Received: from localhost ([::1]:51010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2V2-0006tW-7q for importer@patchew.org; Mon, 09 May 2022 08:28:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50030) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22i-0007nA-Hq for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:12 -0400 Received: from mail-wr1-x42f.google.com ([2a00:1450:4864:20::42f]:41880) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22g-0001KE-Kp for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:12 -0400 Received: by mail-wr1-x42f.google.com with SMTP id c11so19084579wrn.8 for ; Mon, 09 May 2022 04:59:10 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/lpv2cPi1QsrCoVR7BqND3LjQ1uLgD1c9+4prWrFMIY=; b=pwhPb6q+USsUPLF2lWcOj4E9qkuvs8jSSp1Oantv9cKQZuyYnO9O+j63T99SbUIzZa NHA6NULtqPcxQ8rEeeDLM80nyMOZME5fbNx6K8gnjb1jP3dMb+q41ZP3/Jvrz0a9ITr4 wpHDdyCxnsoGnu1iog32icBgVwO+A61Ij1dSx0+liDA9+3EV3xigibmJi++ia9k8my50 rtfChfdiKVFNisaryl4U/IaXlYqwwbU/oyo6WzRCpIdTrjESsQ7LQe3RI8KcocX/tKqj zkZasA76CLJ6xWub3yKPQxAvl4/9tC4J5PujCxX/AlxHTUWvp1WRQsf3sKqrdhJE1ejR tb3Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/lpv2cPi1QsrCoVR7BqND3LjQ1uLgD1c9+4prWrFMIY=; b=OC8tUWvHsntcNAy7STpnwiCkr+Iio2HiYvaXr25FTKl6eS22RMyCyB1ZZEuIiZ4h5g HkuEICTMKvlOi1s4Ro/hC0IUEQ+Fq/vmXXv43lDKvlycP/uxxDIKQgINSpOzhzSFrsBk Tz3JOuVlhZu5Pn1SEjv9fz2n9jx6YbdK1qxEptEP7mLHUD5asFWzyVhZIHF7AHoXr6x1 GhdcxGnk6ts9v/+OvVBFI9z1vF+PW159d4m4jiCxXkiYXb0yc7oHkmfbIS07+1sSyfkV Ux57rxQXCOHeDr/GYn8OtEXMC/M2jIgABQcJubvR6hXUkfk5l148OhXq57HpHTR6G9Hr aM9w== X-Gm-Message-State: AOAM530DHgunWA+7XL8JhRMOS9zLJf5l7VST/ImAoCzZnJyQ4t2dwzta vmP/uqNv0GxOf0CpS/jCFmXC0wwJh8ejJw== X-Google-Smtp-Source: ABdhPJxTqpHyAzrrSf/PXqPDy/p4l7l6mf11G+5BtEjARtMqo36lX1SI/CaDn8M8lBpk+zo7ABBrEA== X-Received: by 2002:adf:f6d1:0:b0:20a:d5ca:6dc0 with SMTP id y17-20020adff6d1000000b0020ad5ca6dc0mr13811285wrp.292.1652097549900; Mon, 09 May 2022 04:59:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 24/32] target/arm: Define cortex-a76 Date: Mon, 9 May 2022 12:58:40 +0100 Message-Id: <20220509115848.3521805-25-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42f; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099310280100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 5fe045cbf06..3e264d85af8 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 23874019639..2ddde88f5eb 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] =3D { static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f94278935f5..12bc2318ecb 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -202,6 +202,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f55121060dc..adfe6b26be7 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -194,6 +194,71 @@ static void aarch64_a72_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -881,6 +946,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652098875; cv=none; d=zohomail.com; s=zohoarc; b=ErnMJyFDtpUfaS+RHzjVkKSvJxzlTNRpVOVsAUpSMNFDtIpKUsivCDkqU+sKR2Q4oZjjFcw9wyt0HrCP/DEqmk6ZT4inRFBisBUCPXanNwzq1AV4UBbUk4LW1NuBvVwe9v73alvHwNNlx+pg+KN1mwabFkOjkLcjzYXeJ2IFaCk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652098875; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gvIVM7y/OILbDxrcgpLmhBrY6fNb+2S83OGiai4zK8Y=; b=cbs0BgpNENdGoGHBM5QBCZLVSvqavvvPn3LP0NDTjDN5wSwZXDhoZpF8ye1uBbfEuk+bidACB1d81TQE/E+zN+jxxP0xn5yuvoKkk/N+NfrZz3Mj7+uf33O41JUocXCWwKbHEGWhj87XA+ND+z1RHRh+ahwpFcFv86CbsnQ+xfY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652098875055136.3094417759463; Mon, 9 May 2022 05:21:15 -0700 (PDT) Received: from localhost ([::1]:36174 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2O2-000554-1Y for importer@patchew.org; Mon, 09 May 2022 08:21:14 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50068) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22k-0007s3-0H for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:14 -0400 Received: from mail-wm1-x32a.google.com ([2a00:1450:4864:20::32a]:35730) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22i-0001LM-6z for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:13 -0400 Received: by mail-wm1-x32a.google.com with SMTP id c190-20020a1c35c7000000b0038e37907b5bso10651166wma.0 for ; Mon, 09 May 2022 04:59:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=gvIVM7y/OILbDxrcgpLmhBrY6fNb+2S83OGiai4zK8Y=; b=cQxqmszrPWVCDJHnwbatVfI0y2Qmm/lUY58pI6TPOGFe/PY6d3MM8uQD6snuorfyzk r1eQJHYblAIKi/wgStgRzkHmqpiFl4QZeQ7WcXLs/HLX3mO1PUlbkuctZIT6W9gqJN+D Pi8eZvCG0gxQc/d6qrF9YKw0B9cAMKnNtSfBFaaFvYLoYhgJdqaFEvurXqKWZpyd4/HT WVNMXOs3HhWvasYNNO3tlKvi5S2FuERzsrb+mAh5AJMbzzr9G6Swrv2RDT/3U5jeJHOT RqMDM9v9SzRc5qTYhz2kC+tcHaA+cn3+zjVZujTgeIKOHqVKSCF7ZKzeV8gMI4PiqUsl fKMQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gvIVM7y/OILbDxrcgpLmhBrY6fNb+2S83OGiai4zK8Y=; b=OiyqMhgX4JV5TRJkKuzRnIgL3LLptsqIZ+971TCHjXp8Pm/ufUjolNzuzvirtvWJWc TiykXChEwQIG41PW7ravlUWMLMEfC6EqIicDi0qAXrzuczsnOEou4rjtN0QMfAfrbWdO WF4xVSPxzNkHp/9hGsehjzBIqUv5e9gCTGt+foQXPJ6tYeraN8gIVehundvsW1YHjS2o VXsp8nNMD2Y2GL9mDXi0klJMn6ZLy8omzuRzrGyHMxypQJoAOeCua2aKHmtVgR4ZjBEb PfeLa3o3qbiTdCk7np+/OJPt7Bt02Tf5m5mV5aE14fgnjp4wcVjp7YyWepc5neYkPweR 39cw== X-Gm-Message-State: AOAM530D8qs+dx/qA21tv+GS5P96Qc+HvMNNWYCI71Aaf8gsL2IQQnJn NG7RIcF+VMr+gj09GoPvUGkOPVwgdZm+AA== X-Google-Smtp-Source: ABdhPJzgB8RA9x2n4WMx1pD8c5iPTYCkeCHDn5SjWYAI75AeHQ5U8q0lkwu2i6AfV0qk42fXX01vkw== X-Received: by 2002:a05:600c:5105:b0:394:7d22:aa93 with SMTP id o5-20020a05600c510500b003947d22aa93mr14277202wms.107.1652097550670; Mon, 09 May 2022 04:59:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 25/32] target/arm: Define neoverse-n1 Date: Mon, 9 May 2022 12:58:41 +0100 Message-Id: <20220509115848.3521805-26-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32a; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652098876208100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220506180242.216785-25-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 3e264d85af8..3d1058a80c0 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) +- ``neoverse-n1`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2ddde88f5eb..dac8860f2d0 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,6 +146,7 @@ static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 12bc2318ecb..da7e3ede563 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index adfe6b26be7..04427e073f1 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -259,6 +259,71 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; } =20 +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -948,6 +1013,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, + { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099511; cv=none; d=zohomail.com; s=zohoarc; b=li6RtCBehIi+JL4oSeel+ruBZT4+G78kYHvYCPfSCyS4aCDNusotohIeA1k47QifhYAOeWA/58LCZUYxweAzAQiZQTSRTUZRIHr+oGCBta3T6u+5B7X9m/iw1Kqqem32CVnQFUXaZjoWi1nruAxKY3Xm0Z/5ByrWSeAP8A/qQFg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099511; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CHxjayFyhr5I4QGmzb4c6k5c4ekfbOJ2eilTAyumfL8=; b=VyT0f6UlvObyF14j1k3q+4XNbOAexffbsGGLuTL02bBhGh+6FQoNOYb3qYKxCeuiDO5wz3MkVdvV+KocxaZNfDknHxS/B9lYf0EZ3dBDEm4GC9DTEHjSwEmbklZhF78zmfZ35Q/7iVQN/VyoFfYxEiDUujOmeJQYE2GXqwGzJco= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099511742585.1164398908014; Mon, 9 May 2022 05:31:51 -0700 (PDT) Received: from localhost ([::1]:57822 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2YI-00038X-OU for importer@patchew.org; Mon, 09 May 2022 08:31:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50078) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22k-0007tu-EH for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:14 -0400 Received: from mail-wm1-x335.google.com ([2a00:1450:4864:20::335]:38682) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22i-0001LV-Or for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:14 -0400 Received: by mail-wm1-x335.google.com with SMTP id 1-20020a05600c248100b00393fbf11a05so10617420wms.3 for ; Mon, 09 May 2022 04:59:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.10 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=CHxjayFyhr5I4QGmzb4c6k5c4ekfbOJ2eilTAyumfL8=; b=Yi1lT6KanPpBoe+NsJfg70qRGUAcu0QBBSI1m4uXpJUX0f6qsCaNB4P0lKf/Ou8QCP yTf0a5qUPuZapQEIG2SGgNacAqIzV0w6GyttKxFYsdS8P9P2zWWLpehYAqUJvDvvj15H cSxDEFVBPmM0zyioddmjxE9S+cQpU3P8Ck1UywjpqQ2Yfe79GAkHquHLnGd0zp4iB5nD 0WlLU6N31lK9vuoq7NDjQIm3cpKM2ZtmPPQfbLkiAUenFxcjZTg+cL9gA5MwEmI/qbll KXcHi/9AWbOhg8E+KfBrf10Gwxvuf5ek8ULUQsQXr2aaSi+Bl1rwSMlUahBnv3qRIJ75 cArw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CHxjayFyhr5I4QGmzb4c6k5c4ekfbOJ2eilTAyumfL8=; b=540PjjfgpErE66kXBajHeRaSqVE2w+/5f/0rGsbv19qQB/seCy+iu0Oev1YmcOSpqc I4drnaCEYhzhOcBifYCwsnQ8ykSmPC/JL8KDFZakOL0zD24K6Mt50JF6HcvyjavDzvDq BEFzHbWhQDJ/1wF+C2kV33Roq76yW8cqRr1NSE+1x1/wCoU2pmV1DLRStXTH92Eo3ndi Vb5V254Ltwl68OTGxzJGFI690cryVntrEWqAB5Rr9tuztkR1xOuhKMPQYixjgLEdXNZO ISKU2jVH5fBouuv6C3KZftnw6g3w07q824KLoVKTm/if8DvwYlR2Zf+eTKU5lsndgCuu o67w== X-Gm-Message-State: AOAM532zH8Ts2cPOcLGtaQgS9VTYeOZXNIw34IjyQUNhIpunHnhlawcJ 1M8XJp/XMOB3SzhQNpPMXUTsf5xvUcewYQ== X-Google-Smtp-Source: ABdhPJygO3VzmttG6ocfV44a0agjpmDoHvyH4GQGVsnRp4kW18trYUR05w2VzVRBWYGHJQ3Ta/LCew== X-Received: by 2002:a05:600c:6005:b0:394:7ba4:5e62 with SMTP id az5-20020a05600c600500b003947ba45e62mr14997828wmb.25.1652097551512; Mon, 09 May 2022 04:59:11 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 26/32] hw/arm: add versioning to sbsa-ref machine DT Date: Mon, 9 May 2022 12:58:42 +0100 Message-Id: <20220509115848.3521805-27-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099512805100001 From: Leif Lindholm The sbsa-ref machine is continuously evolving. Some of the changes we want to make in the near future, to align with real components (e.g. the GIC-700), will break compatibility for existing firmware. Introduce two new properties to the DT generated on machine generation: - machine-version-major To be incremented when a platform change makes the machine incompatible with existing firmware. - machine-version-minor To be incremented when functionality is added to the machine without causing incompatibility with existing firmware. to be reset to 0 when machine-version-major is incremented. This versioning scheme is *neither*: - A QEMU versioned machine type; a given version of QEMU will emulate a given version of the platform. - A reflection of level of SBSA (now SystemReady SR) support provided. The version will increment on guest-visible functional changes only, akin to a revision ID register found on a physical platform. These properties are both introduced with the value 0. (Hence, a machine where the DT is lacking these nodes is equivalent to version 0.0.) Signed-off-by: Leif Lindholm Message-id: 20220505113947.75714-1-quic_llindhol@quicinc.com Cc: Peter Maydell Cc: Radoslaw Biernacki Cc: C=C3=A9dric Le Goater Reviewed-by: Peter Maydell Signed-off-by: Peter Maydell --- hw/arm/sbsa-ref.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index dac8860f2d0..4bb444684f4 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -192,6 +192,20 @@ static void create_fdt(SBSAMachineState *sms) qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); =20 + /* + * This versioning scheme is for informing platform fw only. It is nei= ther: + * - A QEMU versioned machine type; a given version of QEMU will emula= te + * a given version of the platform. + * - A reflection of level of SBSA (now SystemReady SR) support provid= ed. + * + * machine-version-major: updated when changes breaking fw compatibili= ty + * are introduced. + * machine-version-minor: updated when features are added that don't b= reak + * fw compatibility. + */ + qemu_fdt_setprop_cell(fdt, "/", "machine-version-major", 0); + qemu_fdt_setprop_cell(fdt, "/", "machine-version-minor", 0); + if (ms->numa_state->have_numa_distance) { int size =3D nb_numa_nodes * nb_numa_nodes * 3 * sizeof(uint32_t); uint32_t *matrix =3D g_malloc0(size); --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099786; cv=none; d=zohomail.com; s=zohoarc; b=WdRkg7tXNiPdZ1UjTvAlu1sZu/oSCb+NUccx/ppkmjWe5/9lAh9yjs8ufRD5Aarnprxc3tmYrXzBS3P/nGQZ39CvhfOvsilAMpwd1UbVBRB6KNDllH2l1FgUFirRAkiMdvkpnl2SsT12is/r3rkprJ6rsj/N5ZOIKSIxia0xD2w= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099786; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YLPDbkbC5BUT53wo2jLeCb34qH34ZBTypIl7O2mGU7o=; b=jkKWjv7tUpDuVenOMzivwN8smsUdYy/2iHjl5R+D2RU1LxOEG210dmisqegACw/OXflHNt+PvkZwireon+n1OthZmItcWpNq5mhoA17nQxNswCs2kK6cw23BrbRlWk6RfstHHDacGEEifSlcCmgkabKWeFv4Q/OKNcWqcFUmkwo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099786455101.21013605789278; Mon, 9 May 2022 05:36:26 -0700 (PDT) Received: from localhost ([::1]:38394 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2cj-0000sF-8m for importer@patchew.org; Mon, 09 May 2022 08:36:25 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50082) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22k-0007uS-PP for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:14 -0400 Received: from mail-wr1-x42a.google.com ([2a00:1450:4864:20::42a]:45640) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22j-0001IW-55 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:14 -0400 Received: by mail-wr1-x42a.google.com with SMTP id w4so19070775wrg.12 for ; Mon, 09 May 2022 04:59:12 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.11 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YLPDbkbC5BUT53wo2jLeCb34qH34ZBTypIl7O2mGU7o=; b=jKEKt9mSyDPu2mqArGI5a1O2mZydnsLJEfX7bkpeUBS1gqAnBzymOSwfjlGk+wOIZa kbDa32xe2je0ZCN9VfZF+ppMvtrQmEkvWAHLwk26BFkL4a03GP3YB/qmS2WRw/Bie3y7 bRlia1h6VQYcCjYOXAWdeuqPhh1bfgSn6AhkClYazqcqOTadthW//1aZCMPajEhr5DvW PDRjLOjLBY6isEAzqX79ocly52lJ0zxclTVOquO7DNCPsttHQY0ht5d9YV+IbQMkg2h3 6J4LmfqQgQjpuM5NC/Sb5Hgc8VreGU7/4If86TVvt4s6NgKAUQ2nIhcSmoPigTrekp1t 85vg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YLPDbkbC5BUT53wo2jLeCb34qH34ZBTypIl7O2mGU7o=; b=Y9Q71GDK/pwn5jDg7XJPTjXq7YOup2CeFC9feedA5q4HtlS6l8IJwWObfIA3sLPU1j TW/3adOAKXWjp816utoLQOYaMvPOlCBaQVtfW5UHBuWT75g1mHF+0NXUjUu5WxAJwRwy 4AsFcqYqm9jV6YFUq3QNCLTqqXScwfhmfKncvjJYW8a+veApF0H91kB7Q589t4DJpPNV O8Ooeq1PWwQP9PHjeKhJdbpkNzctZkNwTEP6MuAG/Y4/G7aaKMFhbq19D/3Z7apqtFNr +P+scRtYYvQ6eZFibXb7u8aqgUXPVv/s1xTnzZpa5+glPgKUexPenuqvOLD+r2FwFMwz g3Vw== X-Gm-Message-State: AOAM531KUp7Lr2dwETH+rwHzI3f8b3TIMFzm/y60/qVzqqS+2ET8/zRi 4yGS+iyam7aOL4XUvLUeY3qARp2uznwJMw== X-Google-Smtp-Source: ABdhPJw/gmj5yi7t769q7AoUMo0G5LEje0xU00MkhfmBu5ilE7Wpj2GOowlgROEToIxP6brDCcQ8yg== X-Received: by 2002:a05:6000:178d:b0:20c:b1fb:abe9 with SMTP id e13-20020a056000178d00b0020cb1fbabe9mr9442318wrg.452.1652097552362; Mon, 09 May 2022 04:59:12 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 27/32] qapi/machine.json: Add cluster-id Date: Mon, 9 May 2022 12:58:43 +0100 Message-Id: <20220509115848.3521805-28-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099787039100001 Content-Type: text/plain; charset="utf-8" From: Gavin Shan This adds cluster-id in CPU instance properties, which will be used by arm/virt machine. Besides, the cluster-id is also verified or dumped in various spots: * hw/core/machine.c::machine_set_cpu_numa_node() to associate CPU with its NUMA node. * hw/core/machine.c::machine_numa_finish_cpu_init() to record CPU slots with no NUMA mapping set. * hw/core/machine-hmp-cmds.c::hmp_hotpluggable_cpus() to dump cluster-id. Signed-off-by: Gavin Shan Reviewed-by: Yanan Wang Acked-by: Igor Mammedov Message-id: 20220503140304.855514-2-gshan@redhat.com Signed-off-by: Peter Maydell --- qapi/machine.json | 6 ++++-- hw/core/machine-hmp-cmds.c | 4 ++++ hw/core/machine.c | 16 ++++++++++++++++ 3 files changed, 24 insertions(+), 2 deletions(-) diff --git a/qapi/machine.json b/qapi/machine.json index d25a481ce40..4c417e32a5d 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -868,10 +868,11 @@ # @node-id: NUMA node ID the CPU belongs to # @socket-id: socket number within node/board the CPU belongs to # @die-id: die number within socket the CPU belongs to (since 4.1) -# @core-id: core number within die the CPU belongs to +# @cluster-id: cluster number within die the CPU belongs to (since 7.1) +# @core-id: core number within cluster the CPU belongs to # @thread-id: thread number within core the CPU belongs to # -# Note: currently there are 5 properties that could be present +# Note: currently there are 6 properties that could be present # but management should be prepared to pass through other # properties with device_add command to allow for future # interface extension. This also requires the filed names to be kept= in @@ -883,6 +884,7 @@ 'data': { '*node-id': 'int', '*socket-id': 'int', '*die-id': 'int', + '*cluster-id': 'int', '*core-id': 'int', '*thread-id': 'int' } diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c index 4e2f319aebd..5cb5eecbfc9 100644 --- a/hw/core/machine-hmp-cmds.c +++ b/hw/core/machine-hmp-cmds.c @@ -77,6 +77,10 @@ void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qd= ict) if (c->has_die_id) { monitor_printf(mon, " die-id: \"%" PRIu64 "\"\n", c->die_id= ); } + if (c->has_cluster_id) { + monitor_printf(mon, " cluster-id: \"%" PRIu64 "\"\n", + c->cluster_id); + } if (c->has_core_id) { monitor_printf(mon, " core-id: \"%" PRIu64 "\"\n", c->core_= id); } diff --git a/hw/core/machine.c b/hw/core/machine.c index cb9bbc844d2..700c1e76b88 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -682,6 +682,11 @@ void machine_set_cpu_numa_node(MachineState *machine, return; } =20 + if (props->has_cluster_id && !slot->props.has_cluster_id) { + error_setg(errp, "cluster-id is not supported"); + return; + } + if (props->has_socket_id && !slot->props.has_socket_id) { error_setg(errp, "socket-id is not supported"); return; @@ -701,6 +706,11 @@ void machine_set_cpu_numa_node(MachineState *machine, continue; } =20 + if (props->has_cluster_id && + props->cluster_id !=3D slot->props.cluster_id) { + continue; + } + if (props->has_die_id && props->die_id !=3D slot->props.die_id) { continue; } @@ -995,6 +1005,12 @@ static char *cpu_slot_to_string(const CPUArchId *cpu) } g_string_append_printf(s, "die-id: %"PRId64, cpu->props.die_id); } + if (cpu->props.has_cluster_id) { + if (s->len) { + g_string_append_printf(s, ", "); + } + g_string_append_printf(s, "cluster-id: %"PRId64, cpu->props.cluste= r_id); + } if (cpu->props.has_core_id) { if (s->len) { g_string_append_printf(s, ", "); --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099702; cv=none; d=zohomail.com; s=zohoarc; b=cLht7cRuH8zC49G+Xw0uyDhngAkIQVpKrYSBGNusEpskxX5OSBuC96UlSxADBta7LdfWUKZdlVx8BPYIjDGkAhjlfFI1sBCODVWB4UCKo7ePqdmwsBLcL8nRF94O/pS0SL9wK86WwozkXBlfM6GoNlNn9jBGpGmszRawufo+dCU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099702; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/2ZMkN9Xsn+WNKUQIXzmZMqbQpeIw+bxxGpIjA8E3Ao=; b=dig6goSUBWylj1WGT3/h8xR6sKSsloVr2EIeBgpxafqf1Tphn1K3dw0yf7mzmRp7rSj9rvN2yZHOeWNaPLgDce1RMSK61LFfv2FSddS07Z4Pak/6yu1egoI9yGWnagdeR0J3tvcYkDYAQMCjnV6v6zCmEobP4/uyj1S/cQDGXXk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099702551387.91971189504966; Mon, 9 May 2022 05:35:02 -0700 (PDT) Received: from localhost ([::1]:36080 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2bM-0007Vr-SN for importer@patchew.org; Mon, 09 May 2022 08:35:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50102) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22l-0007xx-RK for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:15 -0400 Received: from mail-wr1-x431.google.com ([2a00:1450:4864:20::431]:43791) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22k-0001GV-2x for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:15 -0400 Received: by mail-wr1-x431.google.com with SMTP id v12so19069501wrv.10 for ; Mon, 09 May 2022 04:59:13 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.12 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=/2ZMkN9Xsn+WNKUQIXzmZMqbQpeIw+bxxGpIjA8E3Ao=; b=l4ZNMlirTm4jFEKyH1tpc0j3xlzehgGzioDJWL05w9XOgLsaJIeq6w5tszXyD543nZ t7jajeAuCPan9Di0Q2t7NbGHQRxi4Led7im8J2Hjc8tg/DzkzuWLdex8kJyL/+KbEE9z n9Q1DnUkvSv0U0poBmNY7fGVYkwgvoTgjsmZk8VgwdJQCwaSF8LCLKaTA0sg80WHJaQ4 pdcsCfjZPwHveFc9c4DCQLEgAKp04P2Nb/+ILeTyYQtWH01wVC0Q9R1bR3fH2Cg0iUuR ej6x9JtB5uz529eUQob89StfF5Rj4Rk1FEfS+cOnyraA4c7edmaibPZ9lrWOgpJHXCKu sCMA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/2ZMkN9Xsn+WNKUQIXzmZMqbQpeIw+bxxGpIjA8E3Ao=; b=auVq7LqxBcujvIN4aQ+LqvkNwiEdhWmYr/Euhyh5tXeETUOSU7IQ5j4DZdMrGJBnSX Lf+x909VcfqTLaoGEGydpXwuM46bq+ehzBZvx591cAZtgNE42GxUJnk55oor+GA+qnkL fRVxA1nHOcdsVock55IAP1JkOYNTKMLywbOzzI/vMP53YFLuUFOuujWyLO2oLhvSXXF1 94obOxsMu5IeHTV5dBk/lCCXi2BEJezeqKh6tsMsLmaQ6UQRn8hMiqXJCc/fi9BwlzbY raVKRA5Bc6d6T5bkzlUNSMs5h8T/jAgsD9b0tMFt/uHYkXMzLEcASF3VVXnTLTFGLkKg e3KA== X-Gm-Message-State: AOAM533bRnkmuUoGgkY5g3QrqpP0lilen1/1+3NiubwVIrY9bZCEexpQ lWclcNdtugEJqD6x3+7234M7qr2dL/8rFg== X-Google-Smtp-Source: ABdhPJyqYCgRyZnWW1/pLVjE1clg8t/VPQ0ztvIFlu6X0Q5/vB/AlWpYZozBEhfLVHo7o2PQIDllMw== X-Received: by 2002:a5d:6d0b:0:b0:20c:4ecb:1113 with SMTP id e11-20020a5d6d0b000000b0020c4ecb1113mr13324221wrq.203.1652097553312; Mon, 09 May 2022 04:59:13 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 28/32] qtest/numa-test: Specify CPU topology in aarch64_numa_cpu() Date: Mon, 9 May 2022 12:58:44 +0100 Message-Id: <20220509115848.3521805-29-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099703812100003 From: Gavin Shan The CPU topology isn't enabled on arm/virt machine yet, but we're going to do it in next patch. After the CPU topology is enabled by next patch, "thread-id=3D1" becomes invalid because the CPU core is preferred on arm/virt machine. It means these two CPUs have 0/1 as their core IDs, but their thread IDs are all 0. It will trigger test failure as the following message indicates: [14/21 qemu:qtest+qtest-aarch64 / qtest-aarch64/numa-test ERROR 1.48s killed by signal 6 SIGABRT >>> G_TEST_DBUS_DAEMON=3D/home/gavin/sandbox/qemu.main/tests/dbus-vmstate= -daemon.sh \ QTEST_QEMU_STORAGE_DAEMON_BINARY=3D./storage-daemon/qemu-storage-daem= on \ QTEST_QEMU_BINARY=3D./qemu-system-aarch64 = \ QTEST_QEMU_IMG=3D./qemu-img MALLOC_PERTURB_=3D83 = \ /home/gavin/sandbox/qemu.main/build/tests/qtest/numa-test --tap -k =E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95= =E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2= =80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80= =95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95= =E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95=E2= =80=95=E2=80=95=E2=80=95=E2=80=95=E2=80=95 stderr: qemu-system-aarch64: -numa cpu,node-id=3D0,thread-id=3D1: no match found This fixes the issue by providing comprehensive SMP configurations in aarch64_numa_cpu(). The SMP configurations aren't used before the CPU topology is enabled in next patch. Signed-off-by: Gavin Shan Reviewed-by: Yanan Wang Message-id: 20220503140304.855514-3-gshan@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/numa-test.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c index 749429dd27e..976526e5275 100644 --- a/tests/qtest/numa-test.c +++ b/tests/qtest/numa-test.c @@ -223,7 +223,8 @@ static void aarch64_numa_cpu(const void *data) QTestState *qts; g_autofree char *cli =3D NULL; =20 - cli =3D make_cli(data, "-machine smp.cpus=3D2 " + cli =3D make_cli(data, "-machine " + "smp.cpus=3D2,smp.sockets=3D1,smp.clusters=3D1,smp.cores=3D1,smp.t= hreads=3D2 " "-numa node,nodeid=3D0,memdev=3Dram -numa node,nodeid=3D1 " "-numa cpu,node-id=3D1,thread-id=3D0 " "-numa cpu,node-id=3D0,thread-id=3D1"); --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652100093; cv=none; d=zohomail.com; s=zohoarc; b=baIzYSZ5V76+CtuXYm1MkqeocAwwN6VSJb1re1qBO4OIQUARvWb+iZaOBas+BJPM39Kq2ZtxvMzS64aLaBLPnNsTRO2EjLpbChdrHYOhlVohLGbvY+2rSaj7FO4jJBNlTCvSSsEsNTjravnW61XnsYBu2TktoJ9rOZzEx17tHQo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652100093; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=6W3Bgjhq7uaaxAYbIx+7B2aztwb5IVXKMxHtE0WnVww=; b=G/DJ1Fv4OFELGQXnDIv01fkLE0ZRj/TonLvA9WK8EC2Vi/8yE89BwlWJrCVk8GYNOkNOncPFEHAIfwYUfIp4RaLHr13YvJy7FyOMXKcvL8j5KeIswU1IJX5EhJncCAt9l5arJIN7McL1ZyNHkKblSdSP6VqyAStW1CjbH6ErGuQ= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652100093937113.71083721622733; Mon, 9 May 2022 05:41:33 -0700 (PDT) Received: from localhost ([::1]:43038 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2hg-0004VY-Jt for importer@patchew.org; Mon, 09 May 2022 08:41:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50114) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22m-00080v-HL for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:16 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22k-0001Gn-SY for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:16 -0400 Received: by mail-wr1-x436.google.com with SMTP id e24so19108668wrc.9 for ; Mon, 09 May 2022 04:59:14 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.13 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=6W3Bgjhq7uaaxAYbIx+7B2aztwb5IVXKMxHtE0WnVww=; b=CPn8Bn/vAYWKn46fra/DRUcRidfnJryBmxNl0fvRCsXtffs50QG+/N0qbv3ncn7d1O jnjvuaD8ouB6A8jyBx08uvlZ4lfPEWfauxhJ7HOMQVFeYWB/R84XOw1rwWdmCxD8EkgM kQ3fsO8JDHWQxOiunUE55uJGoKfQt22o1X99bfyoClewSaABTgh+5+rq4v1/CJ6ESguy DBeJma18ICQ3f2Gui+wrepq3sE8iQok63takUTdqQPywp5KSDJ4mTo6NN2oDdGg3UkXA N3DwVNyCjOgbcBpAuBuedhNIDK8YRzZoDj06kV62M5rTSn7Fcq7Oe3psX5WZbjExjKtf gSpQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=6W3Bgjhq7uaaxAYbIx+7B2aztwb5IVXKMxHtE0WnVww=; b=dlGc4onaubhUi1k93ogPupjhjBpG1eTmyqocPR30ForiMAx93KPwNup96MEZ5cYR/S NNrkvzLg+kVrRKIkPtwd7TAu1k1yF7UYPUKm+vF+yabikMojhUT6hi5uN/E4kwo8wY9c xdadRqz4d6iZInaMLks+DLCsoq9ZZj4yXvTVgAaz+GdSnV7KXvblc+KDSqLFdO3cDSme lzp1khG/ZV8RCWeKU73pJUJzskvwKANWoFORSuaVTkW/ADGQw0i7qhAIVMjcrKOJ7XhM dHwLyljO7uSZaJ+mkeo2lUZHW8CYUOp5Z8WPMVJ9nWCkBvHbsWv970tIgwB5/5xwaIkS 3NvA== X-Gm-Message-State: AOAM531Yn/pA0pemELecIbClI63KrEb7cC422GAVBsGfhwFbMzGdh/bF YrKry+fN15X2+1ixDQHlemzdwUWqOxfI2Q== X-Google-Smtp-Source: ABdhPJwLylZfdMDGNQVnFtSsA9JSGXunisMMJyrFHGBj/6XMxfIJ0h5qTBzpo3RAI2lhyUx9ViI4eg== X-Received: by 2002:a05:6000:1f91:b0:20c:d301:2a57 with SMTP id bw17-20020a0560001f9100b0020cd3012a57mr229462wrb.400.1652097554161; Mon, 09 May 2022 04:59:14 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 29/32] hw/arm/virt: Consider SMP configuration in CPU topology Date: Mon, 9 May 2022 12:58:45 +0100 Message-Id: <20220509115848.3521805-30-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652100094991100001 Content-Type: text/plain; charset="utf-8" From: Gavin Shan Currently, the SMP configuration isn't considered when the CPU topology is populated. In this case, it's impossible to provide the default CPU-to-NUMA mapping or association based on the socket ID of the given CPU. This takes account of SMP configuration when the CPU topology is populated. The die ID for the given CPU isn't assigned since it's not supported on arm/virt machine. Besides, the used SMP configuration in qtest/numa-test/aarch64_numa_cpu() is corrcted to avoid testing failure Signed-off-by: Gavin Shan Reviewed-by: Yanan Wang Acked-by: Igor Mammedov Message-id: 20220503140304.855514-4-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index da7e3ede563..c25023a083a 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2562,6 +2562,7 @@ static const CPUArchIdList *virt_possible_cpu_arch_id= s(MachineState *ms) int n; unsigned int max_cpus =3D ms->smp.max_cpus; VirtMachineState *vms =3D VIRT_MACHINE(ms); + MachineClass *mc =3D MACHINE_GET_CLASS(vms); =20 if (ms->possible_cpus) { assert(ms->possible_cpus->len =3D=3D max_cpus); @@ -2575,8 +2576,20 @@ static const CPUArchIdList *virt_possible_cpu_arch_i= ds(MachineState *ms) ms->possible_cpus->cpus[n].type =3D ms->cpu_type; ms->possible_cpus->cpus[n].arch_id =3D virt_cpu_mp_affinity(vms, n); + + assert(!mc->smp_props.dies_supported); + ms->possible_cpus->cpus[n].props.has_socket_id =3D true; + ms->possible_cpus->cpus[n].props.socket_id =3D + n / (ms->smp.clusters * ms->smp.cores * ms->smp.threads); + ms->possible_cpus->cpus[n].props.has_cluster_id =3D true; + ms->possible_cpus->cpus[n].props.cluster_id =3D + (n / (ms->smp.cores * ms->smp.threads)) % ms->smp.clusters; + ms->possible_cpus->cpus[n].props.has_core_id =3D true; + ms->possible_cpus->cpus[n].props.core_id =3D + (n / ms->smp.threads) % ms->smp.cores; ms->possible_cpus->cpus[n].props.has_thread_id =3D true; - ms->possible_cpus->cpus[n].props.thread_id =3D n; + ms->possible_cpus->cpus[n].props.thread_id =3D + n % ms->smp.threads; } return ms->possible_cpus; } --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652100155; cv=none; d=zohomail.com; s=zohoarc; b=AIdXrskmuTqYkksA7gpA3HdgFGjGOl/qdsbEaxEwlprxU8L+3r0VHEXOv4nDKHKMN4u68hZzp38CcV+Nl+jC9zZL/UIm5tndhgKaFG4VBTKaZKwKQs0MNBiga/9ws8MVreDmls+0x2ecIsSFtg+Kbobymz2Wd9bYTSAc/k2DpN0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652100155; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=egnDhnogUFgFI8NqjtDufQtOvQlPRiqNP9maTORnA4Y=; b=BLIoXGx5k1FpwLF8KYNG6FU68hVkfBEG4z21/Vmkm1PMnPT7NQx8dCOMFQE1wzx/YcCJ9Hx2cQUcYo4DFy6KV+Ip76OIzwTkK7PY6Pjd6hza+y6OwPT8VZKdqfOEqB+W6bhaE6eTOOw+Tbw/rZlSLtmLTUwrO1bXe31pIIDVbLc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652100155674194.2121483982388; Mon, 9 May 2022 05:42:35 -0700 (PDT) Received: from localhost ([::1]:46094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2ig-0006uy-LM for importer@patchew.org; Mon, 09 May 2022 08:42:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22n-00084Q-L6 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:18 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:35697) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22l-0001Gm-TB for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:17 -0400 Received: by mail-wr1-x42d.google.com with SMTP id j15so19134476wrb.2 for ; Mon, 09 May 2022 04:59:15 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.14 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=egnDhnogUFgFI8NqjtDufQtOvQlPRiqNP9maTORnA4Y=; b=xARfycHHZW+7WWW36+c73ICNdjD0DN00UKN9s+aaJfKMEmkXmMvdPYKrRPIiL1svKs 0k0qNgaw7N4XM4yyEhnNgV1FF7J74WN/eaIyGM5Hq511Fmj+/mKBMYzZnjd73xw7vA+L w3CUHNaGdHJKVXW+HV2l+jR1hoxqjAq1oFBIGXOikFFked0x3Ru2/vyPWL2GMrU3JlAl kJthWaZcpNISn9vlR3qfDQGck0ZDRGu0shuwFJb5+cSnqA2Tzo1ZImg6F6JNlIDDpGXh /vo/RYpF1fF59CL/F1lLJKBY0Kd8llJstW72+dbXkqKuqNu3JloADEwpFDlr1m7tMOFd YE1Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=egnDhnogUFgFI8NqjtDufQtOvQlPRiqNP9maTORnA4Y=; b=hxVgyIIes7lhZ+BlX996RPr/a6FaftoEdbEAu3f38slW9+Tw1I3fueoQSt2uXaFmTL 8wsw42WK2oGJc9bz5kX8Qm4/9T/Kju1Xeb0fCelct7TD2XE2DKGRXbe+pUOJMtknKc/P kAz6dGHYpz2f7XK3WLCGZmcQdkFwrQt6NyIsWEqf7UgiIAiXkuO1u+ukeVd+/92IvQsx Ixl6hQBe2RaviPrQRBZi+f+QmLlS99qX/Xv42962oUde30dqbbBeGYTOlx5G5kMlXFHN UFp1zJpd0amAQ6zYpQSkv3uVV/VxMsylMgr3vL3h5yO4ctRac8+DwOgrcqZcqsfaASMJ WPfQ== X-Gm-Message-State: AOAM5326vdwwsy7tZ8lbXzRghLH/WjaLPi6hZCXb5bl9CF6et0sRQ8XL 21Uj+KHpqTOIFjJrJpYUnM0chkLyHcUO1g== X-Google-Smtp-Source: ABdhPJyijoNLg9bVrlv9n28NHesTZOF6Sgn93diA2SO3DDZtCXcc0oOKXwOTJHLoy+FGq4LxuRncfg== X-Received: by 2002:a05:6000:2ae:b0:20c:57b6:32e1 with SMTP id l14-20020a05600002ae00b0020c57b632e1mr13351598wry.285.1652097555057; Mon, 09 May 2022 04:59:15 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 30/32] qtest/numa-test: Correct CPU and NUMA association in aarch64_numa_cpu() Date: Mon, 9 May 2022 12:58:46 +0100 Message-Id: <20220509115848.3521805-31-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652100157325100001 Content-Type: text/plain; charset="utf-8" From: Gavin Shan In aarch64_numa_cpu(), the CPU and NUMA association is something like below. Two threads in the same core/cluster/socket are associated with two individual NUMA nodes, which is unreal as Igor Mammedov mentioned. We don't expect the association to break NUMA-to-socket boundary, which matches with the real world. NUMA-node socket cluster core thread ------------------------------------------ 0 0 0 0 0 1 0 0 0 1 This corrects the topology for CPUs and their association with NUMA nodes. After this patch is applied, the CPU and NUMA association becomes something like below, which looks real. Besides, socket/cluster/core/thread IDs are all checked when the NUMA node IDs are verified. It helps to check if the CPU topology is properly populated or not. NUMA-node socket cluster core thread ------------------------------------------ 0 1 0 0 0 1 0 0 0 0 Suggested-by: Igor Mammedov Signed-off-by: Gavin Shan Acked-by: Igor Mammedov Message-id: 20220503140304.855514-5-gshan@redhat.com Signed-off-by: Peter Maydell --- tests/qtest/numa-test.c | 18 ++++++++++++------ 1 file changed, 12 insertions(+), 6 deletions(-) diff --git a/tests/qtest/numa-test.c b/tests/qtest/numa-test.c index 976526e5275..c5eb13f349f 100644 --- a/tests/qtest/numa-test.c +++ b/tests/qtest/numa-test.c @@ -224,17 +224,17 @@ static void aarch64_numa_cpu(const void *data) g_autofree char *cli =3D NULL; =20 cli =3D make_cli(data, "-machine " - "smp.cpus=3D2,smp.sockets=3D1,smp.clusters=3D1,smp.cores=3D1,smp.t= hreads=3D2 " + "smp.cpus=3D2,smp.sockets=3D2,smp.clusters=3D1,smp.cores=3D1,smp.t= hreads=3D1 " "-numa node,nodeid=3D0,memdev=3Dram -numa node,nodeid=3D1 " - "-numa cpu,node-id=3D1,thread-id=3D0 " - "-numa cpu,node-id=3D0,thread-id=3D1"); + "-numa cpu,node-id=3D0,socket-id=3D1,cluster-id=3D0,core-id=3D0,th= read-id=3D0 " + "-numa cpu,node-id=3D1,socket-id=3D0,cluster-id=3D0,core-id=3D0,th= read-id=3D0"); qts =3D qtest_init(cli); cpus =3D get_cpus(qts, &resp); g_assert(cpus); =20 while ((e =3D qlist_pop(cpus))) { QDict *cpu, *props; - int64_t thread, node; + int64_t socket, cluster, core, thread, node; =20 cpu =3D qobject_to(QDict, e); g_assert(qdict_haskey(cpu, "props")); @@ -242,12 +242,18 @@ static void aarch64_numa_cpu(const void *data) =20 g_assert(qdict_haskey(props, "node-id")); node =3D qdict_get_int(props, "node-id"); + g_assert(qdict_haskey(props, "socket-id")); + socket =3D qdict_get_int(props, "socket-id"); + g_assert(qdict_haskey(props, "cluster-id")); + cluster =3D qdict_get_int(props, "cluster-id"); + g_assert(qdict_haskey(props, "core-id")); + core =3D qdict_get_int(props, "core-id"); g_assert(qdict_haskey(props, "thread-id")); thread =3D qdict_get_int(props, "thread-id"); =20 - if (thread =3D=3D 0) { + if (socket =3D=3D 0 && cluster =3D=3D 0 && core =3D=3D 0 && thread= =3D=3D 0) { g_assert_cmpint(node, =3D=3D, 1); - } else if (thread =3D=3D 1) { + } else if (socket =3D=3D 1 && cluster =3D=3D 0 && core =3D=3D 0 &&= thread =3D=3D 0) { g_assert_cmpint(node, =3D=3D, 0); } else { g_assert(false); --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652099102; cv=none; d=zohomail.com; s=zohoarc; b=L6hpHFhYm2ZnD9I4qoh/BwTLwodN7xmFajZP3k11ax7L0Cv/fm2K6nxw3m+ACp8NQIWBjI7GsJw42x1O3l8PmQiDOaCxG0cnHnDDjowG2z7Ppq+1fZuKNQkC0DBMauvDs50V9ijTCcs84OGV/DRgQjbNL1N3xq0nMHtIwdpur04= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652099102; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GAKojUArTipjlz2CUBGk94csiNAnp/cdOHeIZmJ/G7k=; b=UL4v4ybZyzpFDyat2JSwFmSZxrxKaxhT8wxSsBUi4HV/KUtDc11msQyODK+3+IDj6UvedMGH6bjC9ON+fZ487OfCFlSnW7zyJaNlcWtkTRGPuuNhsk3T/PyVkW7KPzFvGpmIOw5FQDJYupx8F3w6dqC6qFbDw7/0rRZpxne9lio= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652099102931828.3468075712872; Mon, 9 May 2022 05:25:02 -0700 (PDT) Received: from localhost ([::1]:43186 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2Rh-0001ZP-SP for importer@patchew.org; Mon, 09 May 2022 08:25:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50158) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22o-00086r-U2 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:18 -0400 Received: from mail-wm1-x332.google.com ([2a00:1450:4864:20::332]:39715) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22n-0001MO-C1 for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:18 -0400 Received: by mail-wm1-x332.google.com with SMTP id 125-20020a1c0283000000b003946c466c17so47404wmc.4 for ; Mon, 09 May 2022 04:59:16 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.15 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:15 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=GAKojUArTipjlz2CUBGk94csiNAnp/cdOHeIZmJ/G7k=; b=a6suQOZdhGln2FMk/CT5buKH0UElF3/j1XNo9et4bw33WoQtHs4W0LXGF2Nxbi38Nv QerNQEpYthuSNLAfG33r2xsoUC9758SOHyGsAwgDGkypkmkq2DBN+iTmH5tgKzIqro+A epWR1XBsRnX7cf5rHiwEWDnzjx2wo96AVSS4FjWJPfyfLEohlzdljuFp0qcovJeWUs4j /XlxKatr/9HIgPLH2md2hYz+NbPcWy6DJG/s12nCCZCKed+D2N1mJwtP2U81wo/2JsyK +9au6IS+aoQLua9+xgTApDvN7QojDaN6vu2hV8fZWE0LrPxNzvEKvKrrIsibFbFXX4Ep 60Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GAKojUArTipjlz2CUBGk94csiNAnp/cdOHeIZmJ/G7k=; b=3OHzU8sEUsLhuK9TqGByiuLXNrrN+GQkv4IEslA6fsBfLgLTxjm+NpTmnqKiOFGNHB +zLaHhXhqDw8l525HxrX3fYNtk4jdzSfplSb1fyL1YKPTQGbe0wBp39aqZe19uqxaAXc m0GR5q9f1Yze00btmwEiOJcDJwndIL2HYauAKUYeUShg8PoQ2/uWcc61TPiopT/FdrGH crC7EqqEUr+CkMwGeRttLMuyOhvfC1Ah/yGb/gx+JUhYlFrRMZM5kFnHAD/D32tpt98L HDgJOItX8SndP4mUQNOVjCtD+z0hD0N0sUMwPtNRM5L0wtH0i6/RqNaIMhTqRonZSEKr Gm9A== X-Gm-Message-State: AOAM5333ThC4wrKKWfYAUkDM30Rrfv8kCUKyCpnNY1QGlI+eRWhyzyeW kp4w7kPz8YxrXO/Bv4CzZH/3HjtM/5sF8g== X-Google-Smtp-Source: ABdhPJybtteFGKKe+afAYBYTrmmO9T/SObzgzj0VpDhMXPvfg5Lk0zzIWDhNDPaBivU25KNe760aiQ== X-Received: by 2002:a1c:4b12:0:b0:394:3558:a95e with SMTP id y18-20020a1c4b12000000b003943558a95emr15556137wma.147.1652097556035; Mon, 09 May 2022 04:59:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 31/32] hw/arm/virt: Fix CPU's default NUMA node ID Date: Mon, 9 May 2022 12:58:47 +0100 Message-Id: <20220509115848.3521805-32-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652099104516100003 Content-Type: text/plain; charset="utf-8" From: Gavin Shan When CPU-to-NUMA association isn't explicitly provided by users, the default one is given by mc->get_default_cpu_node_id(). However, the CPU topology isn't fully considered in the default association and this causes CPU topology broken warnings on booting Linux guest. For example, the following warning messages are observed when the Linux guest is booted with the following command lines. /home/gavin/sandbox/qemu.main/build/qemu-system-aarch64 \ -accel kvm -machine virt,gic-version=3Dhost \ -cpu host \ -smp 6,sockets=3D2,cores=3D3,threads=3D1 \ -m 1024M,slots=3D16,maxmem=3D64G \ -object memory-backend-ram,id=3Dmem0,size=3D128M \ -object memory-backend-ram,id=3Dmem1,size=3D128M \ -object memory-backend-ram,id=3Dmem2,size=3D128M \ -object memory-backend-ram,id=3Dmem3,size=3D128M \ -object memory-backend-ram,id=3Dmem4,size=3D128M \ -object memory-backend-ram,id=3Dmem4,size=3D384M \ -numa node,nodeid=3D0,memdev=3Dmem0 \ -numa node,nodeid=3D1,memdev=3Dmem1 \ -numa node,nodeid=3D2,memdev=3Dmem2 \ -numa node,nodeid=3D3,memdev=3Dmem3 \ -numa node,nodeid=3D4,memdev=3Dmem4 \ -numa node,nodeid=3D5,memdev=3Dmem5 : alternatives: patching kernel code BUG: arch topology borken the CLS domain not a subset of the MC domain BUG: arch topology borken the DIE domain not a subset of the NODE domain With current implementation of mc->get_default_cpu_node_id(), CPU#0 to CPU#5 are associated with NODE#0 to NODE#5 separately. That's incorrect because CPU#0/1/2 should be associated with same NUMA node because they're seated in same socket. This fixes the issue by considering the socket ID when the default CPU-to-NUMA association is provided in virt_possible_cpu_arch_ids(). With this applied, no more CPU topology broken warnings are seen from the Linux guest. The 6 CPUs are associated with NODE#0/1, but there are no CPUs associated with NODE#2/3/4/5. Signed-off-by: Gavin Shan Reviewed-by: Igor Mammedov Reviewed-by: Yanan Wang Message-id: 20220503140304.855514-6-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/arm/virt.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/hw/arm/virt.c b/hw/arm/virt.c index c25023a083a..1a45f44435e 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -2554,7 +2554,9 @@ virt_cpu_index_to_props(MachineState *ms, unsigned cp= u_index) =20 static int64_t virt_get_default_cpu_node_id(const MachineState *ms, int id= x) { - return idx % ms->numa_state->num_nodes; + int64_t socket_id =3D ms->possible_cpus->cpus[idx].props.socket_id; + + return socket_id % ms->numa_state->num_nodes; } =20 static const CPUArchIdList *virt_possible_cpu_arch_ids(MachineState *ms) --=20 2.25.1 From nobody Wed May 15 08:50:42 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1652100385; cv=none; d=zohomail.com; s=zohoarc; b=jR0CU16BmDrptc8gePVxM5rnLMhbV3Leyzw9p3tvHq5Sw928urEhzat387B2Lx4QO8G89tGn437OLvJL2HLr9AO9BAxh+Qduid5XaAOeoyRBj4Nn8GJy0bTWUDIHnVAFFoW6kMz48Rfh6LcB3TufhQq58jrLMdNWiEzhL5TS2q0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1652100385; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=aYXIZAfUyumvHztGuBmfJ493wl1SWQhTJkN41sNVXpo=; b=Yid5WmfvTrS2egt8+KEhqkWRR6cwQ8kCPXa940IeIfAYv3b79vnFc2D39TUQppf/0gfGfV3Bt58QGA4okZyj8F1PP5E83AFBPQDI6+sR/qkAWqrEILweoff9TsWixmXrJ2UffFfdstXt6P0JwObvc9huDAN6vyuS/74ujwp1hGg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1652100385643108.74811699104396; Mon, 9 May 2022 05:46:25 -0700 (PDT) Received: from localhost ([::1]:54592 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1no2mO-0004XX-9P for importer@patchew.org; Mon, 09 May 2022 08:46:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:50166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1no22p-00088B-GK for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:19 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:42926) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1no22n-0001Gn-Jv for qemu-devel@nongnu.org; Mon, 09 May 2022 07:59:19 -0400 Received: by mail-wr1-x436.google.com with SMTP id e24so19108668wrc.9 for ; Mon, 09 May 2022 04:59:17 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bs6-20020a056000070600b0020c5253d8bdsm12199928wrb.9.2022.05.09.04.59.16 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 May 2022 04:59:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=aYXIZAfUyumvHztGuBmfJ493wl1SWQhTJkN41sNVXpo=; b=daBMO3S3dZ0hlNjXy6GD80QDKPKSa9jz99hOUzLdyJdahyZqnsoiAi1OE+TCP5++HM L3a6jGkhKL8duPBZj1l+42jLbtgADJol6Kh/EqfPjeMKyjdcwnqtFIssCHLDClnCEJnT gUwLmbiUdQ/GIS46z+aBaCWqL/UsEwyGxeF3+XDIWvDH7cn3RsPqg53Eso5RNAY6tcI2 PjWIGwUHueFRoGIjHxFxlT4oaHsYgeojg3XcEzf1hhFDa6fF9ESJ63/4Y3xPdYw2BNZh uPnk62ojcTs5S5FFlZTV48wWrqPo1NNQf0HN8/LcU78vCvw5wdaH9IoyS7E5Y56/z7DG snhw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=aYXIZAfUyumvHztGuBmfJ493wl1SWQhTJkN41sNVXpo=; b=jSXbEjhuo5aq6DbJjNnVH//ZXyOBRjufnrJuUWUGvKkkgSOaBm8I2i5n+DoOsA+piF FS5ae9nW+XioXZ+JKhT11Xa6viI8zUnYvPUz4PFa12Si8i18/X/L+q+9xjWRqX/Od+A4 NYDvDrLcSdihrgHH7X/79QBJ3obeqTShoA9VgvrjCzsFvDAsvpy45G/XOwMyj96MibM1 ngps5SAVz3zhVfaq8TJQk6ZmHseKQboqI/0UE8N7RO0REIDYox8yHKaZqt21KhodR2TJ 57H1LEoj4unRwAghUDPTLClwtp4kwNQRyjd03WvIB7T2b/OU5TQjjkS7M0oxhDr5bbZN t5dg== X-Gm-Message-State: AOAM530bcWtK4z8CxO8e7bVuAUXLTKiULRW4cLVRpCgag1NABZM0XgTb 5vGqfkRUo7gMOr+zA15HAaAQYe3pVVWRUQ== X-Google-Smtp-Source: ABdhPJwrLTUgygQva0W2aRB8BuTkKUKr67iWE/n8EhjMipCMEWcjuxUyoBZJ7zVe1QmGlM5dOXDQZA== X-Received: by 2002:a5d:4052:0:b0:20a:d8b9:9d4b with SMTP id w18-20020a5d4052000000b0020ad8b99d4bmr13201130wrp.612.1652097556877; Mon, 09 May 2022 04:59:16 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 32/32] hw/acpi/aml-build: Use existing CPU topology to build PPTT table Date: Mon, 9 May 2022 12:58:48 +0100 Message-Id: <20220509115848.3521805-33-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220509115848.3521805-1-peter.maydell@linaro.org> References: <20220509115848.3521805-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1652100387099100001 Content-Type: text/plain; charset="utf-8" From: Gavin Shan When the PPTT table is built, the CPU topology is re-calculated, but it's unecessary because the CPU topology has been populated in virt_possible_cpu_arch_ids() on arm/virt machine. This reworks build_pptt() to avoid by reusing the existing IDs in ms->possible_cpus. Currently, the only user of build_pptt() is arm/virt machine. Signed-off-by: Gavin Shan Tested-by: Yanan Wang Reviewed-by: Yanan Wang Acked-by: Igor Mammedov Acked-by: Michael S. Tsirkin Message-id: 20220503140304.855514-7-gshan@redhat.com Signed-off-by: Peter Maydell --- hw/acpi/aml-build.c | 111 +++++++++++++++++++------------------------- 1 file changed, 48 insertions(+), 63 deletions(-) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 4086879ebff..e6bfac95c7a 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2002,86 +2002,71 @@ void build_pptt(GArray *table_data, BIOSLinker *lin= ker, MachineState *ms, const char *oem_id, const char *oem_table_id) { MachineClass *mc =3D MACHINE_GET_CLASS(ms); - GQueue *list =3D g_queue_new(); - guint pptt_start =3D table_data->len; - guint parent_offset; - guint length, i; - int uid =3D 0; - int socket; + CPUArchIdList *cpus =3D ms->possible_cpus; + int64_t socket_id =3D -1, cluster_id =3D -1, core_id =3D -1; + uint32_t socket_offset =3D 0, cluster_offset =3D 0, core_offset =3D 0; + uint32_t pptt_start =3D table_data->len; + int n; AcpiTable table =3D { .sig =3D "PPTT", .rev =3D 2, .oem_id =3D oem_id, .oem_table_id =3D oem_table_id= }; =20 acpi_table_begin(&table, table_data); =20 - for (socket =3D 0; socket < ms->smp.sockets; socket++) { - g_queue_push_tail(list, - GUINT_TO_POINTER(table_data->len - pptt_start)); - build_processor_hierarchy_node( - table_data, - /* - * Physical package - represents the boundary - * of a physical package - */ - (1 << 0), - 0, socket, NULL, 0); - } - - if (mc->smp_props.clusters_supported) { - length =3D g_queue_get_length(list); - for (i =3D 0; i < length; i++) { - int cluster; - - parent_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); - for (cluster =3D 0; cluster < ms->smp.clusters; cluster++) { - g_queue_push_tail(list, - GUINT_TO_POINTER(table_data->len - pptt_start)); - build_processor_hierarchy_node( - table_data, - (0 << 0), /* not a physical package */ - parent_offset, cluster, NULL, 0); - } + /* + * This works with the assumption that cpus[n].props.*_id has been + * sorted from top to down levels in mc->possible_cpu_arch_ids(). + * Otherwise, the unexpected and duplicated containers will be + * created. + */ + for (n =3D 0; n < cpus->len; n++) { + if (cpus->cpus[n].props.socket_id !=3D socket_id) { + assert(cpus->cpus[n].props.socket_id > socket_id); + socket_id =3D cpus->cpus[n].props.socket_id; + cluster_id =3D -1; + core_id =3D -1; + socket_offset =3D table_data->len - pptt_start; + build_processor_hierarchy_node(table_data, + (1 << 0), /* Physical package */ + 0, socket_id, NULL, 0); } - } =20 - length =3D g_queue_get_length(list); - for (i =3D 0; i < length; i++) { - int core; - - parent_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); - for (core =3D 0; core < ms->smp.cores; core++) { - if (ms->smp.threads > 1) { - g_queue_push_tail(list, - GUINT_TO_POINTER(table_data->len - pptt_start)); - build_processor_hierarchy_node( - table_data, - (0 << 0), /* not a physical package */ - parent_offset, core, NULL, 0); - } else { - build_processor_hierarchy_node( - table_data, - (1 << 1) | /* ACPI Processor ID valid */ - (1 << 3), /* Node is a Leaf */ - parent_offset, uid++, NULL, 0); + if (mc->smp_props.clusters_supported) { + if (cpus->cpus[n].props.cluster_id !=3D cluster_id) { + assert(cpus->cpus[n].props.cluster_id > cluster_id); + cluster_id =3D cpus->cpus[n].props.cluster_id; + core_id =3D -1; + cluster_offset =3D table_data->len - pptt_start; + build_processor_hierarchy_node(table_data, + (0 << 0), /* Not a physical package */ + socket_offset, cluster_id, NULL, 0); } + } else { + cluster_offset =3D socket_offset; } - } =20 - length =3D g_queue_get_length(list); - for (i =3D 0; i < length; i++) { - int thread; + if (ms->smp.threads =3D=3D 1) { + build_processor_hierarchy_node(table_data, + (1 << 1) | /* ACPI Processor ID valid */ + (1 << 3), /* Node is a Leaf */ + cluster_offset, n, NULL, 0); + } else { + if (cpus->cpus[n].props.core_id !=3D core_id) { + assert(cpus->cpus[n].props.core_id > core_id); + core_id =3D cpus->cpus[n].props.core_id; + core_offset =3D table_data->len - pptt_start; + build_processor_hierarchy_node(table_data, + (0 << 0), /* Not a physical package */ + cluster_offset, core_id, NULL, 0); + } =20 - parent_offset =3D GPOINTER_TO_UINT(g_queue_pop_head(list)); - for (thread =3D 0; thread < ms->smp.threads; thread++) { - build_processor_hierarchy_node( - table_data, + build_processor_hierarchy_node(table_data, (1 << 1) | /* ACPI Processor ID valid */ (1 << 2) | /* Processor is a Thread */ (1 << 3), /* Node is a Leaf */ - parent_offset, uid++, NULL, 0); + core_offset, n, NULL, 0); } } =20 - g_queue_free(list); acpi_table_end(linker, &table); } =20 --=20 2.25.1