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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pPugSRT5glzJz0c1TvdvdRW/o0T2XpWhDabDguMkmM4=; b=bkdB5N6Y3g4Bamk90MmALREdPcVnQ3XmydClDf92fkOjCBMqkyCMAWfi4RxXJbi5Wd Skm1gcmuUhwu+aTJ1d7S+5Qs9ml18Gd0qiz2OoVQ/R96sJTkZpTk6lZYwTf0gLSI8m4p eGvLZj2r7XJG3czv8U4RbYXBsdIGksJRWBAb2LASjm+Lq7d3YsUUUeYD6FVBGUrh+qYl BQxDPumy1Fys6CwQ6FMD+b5TXhNBWic9WkOWrP4SdEN6yxtBp7h/b/M8HbY0l2HWGTqt 2G1wvojr8l7+Kdyl9Mq9BjYLuUWj/6XUgAIRy1+qtJYsrQ4iaUD9lX0HUA7+MyZGv7jc Ggvw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pPugSRT5glzJz0c1TvdvdRW/o0T2XpWhDabDguMkmM4=; b=QLQihT9u+Wdf+KPTKKQrAPskTSftSM1CFEVMYP1SG0+QXvgNtR/oK3/iDg/00mo8X1 IP0ZoO217Fn0Upvra/0taQKvbdhAEGuf04yhrvwKrXtgJH24hBxOOUL0SGTeaz8Yue0u FtFXgnt2vey5j0NzX1wYUWiNjy1Uim5KWKmoBzZBSh43xxc0bR7iQhBGep2P+jnLyR9C LrhRt9sqOKQ40Eg9VXTBmwoX9HaAryCjCjg8rKugH1hMV0qdPkSitdc480CaWvXnoHPW r4xxIcaPq0SHZcHSfcGZqfOjgNjLMJILLDC2s6x6a+nE/imcpqc3+7rhJGNSF3TA63Gy kK+g== X-Gm-Message-State: AOAM5303xlSpH5bLj+EG1XtnypFXD0Igm8nwROvYVwaZS/mCjvdMSoUY LyvieN79IWKJOG/E013iqhcmFNdqEX9myw== X-Google-Smtp-Source: ABdhPJzdLNgkqqin1c+Qq0ubTBC5Hpnp2ENbZrF1iqKsrkspFeUZAQodHsc1ACvdqeXCNJ1sst/8fQ== X-Received: by 2002:a9d:2f61:0:b0:5e9:4bfb:61cc with SMTP id h88-20020a9d2f61000000b005e94bfb61ccmr1435051otb.355.1651860167851; Fri, 06 May 2022 11:02:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 01/24] target/arm: Handle cpreg registration for missing EL Date: Fri, 6 May 2022 13:02:19 -0500 Message-Id: <20220506180242.216785-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860355019100002 Content-Type: text/plain; charset="utf-8" More gracefully handle cpregs when EL2 and/or EL3 are missing. If the reg is entirely inaccessible, do not register it at all. If the reg is for EL2, and EL3 is present but EL2 is not, either discard, squash to res0, const, or keep unchanged. Per rule RJFFP, mark the 4 aarch32 hypervisor access registers with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. Mark the 2 virtualization processor id regs ARM_CP_EL3_NO_EL2_C_NZ. This will simplify cpreg registration for conditional arm features. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Add ARM_CP_EL3_NO_EL2_{UNDEF,KEEP}. v5: Add ARM_CP_EL3_NO_EL2_C_NZ. --- target/arm/cpregs.h | 11 +++ target/arm/helper.c | 178 ++++++++++++++++++++++++++++++-------------- 2 files changed, 133 insertions(+), 56 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 73984549d2..db03d6a7e1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -102,6 +102,17 @@ enum { ARM_CP_SVE =3D 1 << 14, /* Flag: Do not expose in gdb sysreg xml. */ ARM_CP_NO_GDB =3D 1 << 15, + /* + * Flags: If EL3 but not EL2... + * - UNDEF: discard the cpreg, + * - KEEP: retain the cpreg as is, + * - C_NZ: set const on the cpreg, but retain resetvalue, + * - else: set const on the cpreg, zero resetvalue, aka RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + ARM_CP_EL3_NO_EL2_UNDEF =3D 1 << 16, + ARM_CP_EL3_NO_EL2_KEEP =3D 1 << 17, + ARM_CP_EL3_NO_EL2_C_NZ =3D 1 << 18, }; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index b4daf4f076..9ab8b65e7b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5056,16 +5056,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_FPU, + .access =3D PL2_RW, + .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, @@ -5542,27 +5543,27 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D tlbimva_hyp_is_write }, { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2_write }, { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2_write }, { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2_write }, { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2is_write }, { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY /* Unlike the other EL2-related AT operations, these must @@ -5572,11 +5573,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se @@ -6076,7 +6079,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, + .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit * alias is DBGDCCINT. @@ -6892,11 +6895,11 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NOP }, { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, @@ -6906,19 +6909,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NOP }, { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2_write }, { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2_write }, { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, @@ -6973,11 +6976,11 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2is_write }, { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, @@ -6985,7 +6988,7 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .writefn =3D tlbi_aa64_alle1is_write }, { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, @@ -7905,21 +7908,24 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D cpu->midr, .type =3D ARM_CP_ALIAS, + .resetvalue =3D cpu->midr, + .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vpidr_el2) = }, { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 0, .access =3D PL2_RW, .resetvalue =3D cpu->midr, + .type =3D ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, { .name =3D "VMPIDR", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D 5, .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .resetvalue =3D vmpidr_def, .type =3D ARM_CP_ALIAS, + .resetvalue =3D vmpidr_def, + .type =3D ARM_CP_ALIAS | ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.vmpidr_el2)= }, { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 =3D = 5, - .access =3D PL2_RW, - .resetvalue =3D vmpidr_def, + .access =3D PL2_RW, .resetvalue =3D vmpidr_def, + .type =3D ARM_CP_EL3_NO_EL2_C_NZ, .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, }; define_arm_cp_regs(cpu, vpidr_regs); @@ -8506,13 +8512,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, int crm, int opc1, int opc2, const char *name) { + CPUARMState *env =3D &cpu->env; uint32_t key; ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; - bool isbanked; size_t name_len; + bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -8547,6 +8554,32 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + make_const =3D false; + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? PL2_RW : PL1_RW); + if ((r->access & max_el) =3D=3D 0) { + return; + } + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8567,44 +8600,77 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, r2->opaque =3D opaque; } =20 - isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; - if (isbanked) { + if (make_const) { + /* This should not have been a very special register to begin. */ + int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); /* - * Register is banked (using both entries in array). - * Overwriting fieldoffset as the array is only used to define - * banked registers but later only fieldoffset is used. + * Set the special function to CONST, retaining the other flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; - } + r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; + /* + * Usually, these registers become RES0, but there are a few + * special cases like VPIDR_EL2 which have a constant non-zero + * value with writes ignored. + */ + if (!(r->type & ARM_CP_EL3_NO_EL2_C_NZ)) { + r2->resetvalue =3D 0; + } + /* + * ARM_CP_CONST has precedence, so removing the callbacks and + * offsets are not strictly necessary, but it is potentially + * less confusing to debug later. + */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->resetfn =3D NULL; + r2->fieldoffset =3D 0; + r2->bank_fieldoffsets[0] =3D 0; + r2->bank_fieldoffsets[1] =3D 0; + } else { + bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 - if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { /* - * If the register is banked then we don't need to migrate or - * reset the 32-bit instance in certain cases: - * - * 1) If the register has both 32-bit and 64-bit instances the= n we - * can count on the 64-bit instance taking care of the - * non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit version - * taking care of the secure bank. This requires that sepa= rate - * 32 and 64-bit definitions are provided. + * Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + } + if (state =3D=3D ARM_CP_STATE_AA32) { + if (isbanked) { + /* + * If the register is banked then we don't need to migrate= or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances + * then we can count on the 64-bit instance taking care + * of the non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit + * version taking care of the secure bank. This requir= es + * that separate 32 and 64-bit definitions are provided. + */ + if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { + r2->type |=3D ARM_CP_ALIAS; + } + } else if ((secstate !=3D r->secure) && !ns) { + /* + * The register is not banked so we only want to allow + * migration of the non-secure instance. + */ r2->type |=3D ARM_CP_ALIAS; } - } else if ((secstate !=3D r->secure) && !ns) { - /* - * The register is not banked so we only want to allow migrati= on - * of the non-secure instance. - */ - r2->type |=3D ARM_CP_ALIAS; - } =20 - if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); + if (HOST_BIG_ENDIAN && + r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); + } } } =20 @@ -8615,7 +8681,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r->type & ARM_CP_SPECIAL_MASK) { + if (r2->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860545; cv=none; d=zohomail.com; s=zohoarc; b=P+wtvXF0TVzhXonjR7heM5SLZmPTFlxY7xKUtvbQbiqOksaBQK51yXy2l5ek0z6YPcLQ4qt7M9zo4Kcyl+ZBapLfiCoLF9ei0PzET6oDW/Z4zr+42kMDsWoeorUIeURybvn+tEzUbkmY0WvP6JVO47s752SoJ0e9Bsunqmb6BHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860545; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ptjDtEiLpCOaJ8VQ+D/jSFXKE6U8bdHxVPiUtMKZSjQ=; b=YY0qiham16t31P0YG5qlBIY62iRSPCOJ7NmQI3PnKaMgTBebdFoMaQwYm8XK/GHsjhXvAaxx4Th+84L4nYAb+UnFTn7Y1+pxKH9qoVZcfhNtN7d0iuhVPXqpMuM4wHeP3WNxMlc13PKG0xpMd23b1nxd4Iw/ZQhYclZIE3S+7d4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860545878948.031164732983; Fri, 6 May 2022 11:09:05 -0700 (PDT) Received: from localhost ([::1]:59404 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2O0-0006EJ-QH for importer@patchew.org; Fri, 06 May 2022 14:09:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2I0-0005Ar-Uu for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:52 -0400 Received: from mail-oi1-x236.google.com ([2607:f8b0:4864:20::236]:35570) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2Hy-0003nt-6j for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:52 -0400 Received: by mail-oi1-x236.google.com with SMTP id m25so8306404oih.2 for ; Fri, 06 May 2022 11:02:49 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ptjDtEiLpCOaJ8VQ+D/jSFXKE6U8bdHxVPiUtMKZSjQ=; b=RCLVnvVdeGE9SNiAUiPdIaxXVU/ZrlMx9d5Pyp+3jquH2YDaWL87V1AnUvobolCKmH EY92UbqDvG391Of07UVOlKb5U7n53Pc8HL8Vf7nW16vfwvq3ROrcvRrEoIQdRwOi8wpB 7gYI90CNzTIAty2H/cw7r8zpVYMRepdg4jAxk4Vk2vyNwfzApxXuJJIbVulY5lC14M5v eTTiosrpIY3uYH8RVu19ryI6tutxZg9o9FVxPjlHwKVq2Q6y9yHad3m7AktHGR6F2LTk yLXCJ4a7AVimLwtUamnZzKr2Cx4d4pAhKp+A8yEqdQCp9TQ7J3v3d6JnStps/pUOOGx6 5xVA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ptjDtEiLpCOaJ8VQ+D/jSFXKE6U8bdHxVPiUtMKZSjQ=; b=ZXyxgF4xtDzpiWOdb/NcOuXMnPMXXYTJo4+vKQGwr9Ezh7LGTqHOJ+w0r8CuQt2V3O ZezefzCokpx7vh0P6qi4GQbna20MjGtr7XgsiA642vUWBKh+durC2e1UKPMfzPpseZoK ifGDuTNmPYU8QjcIdf8QSGwkdPBCxDV+WCx46m3EHn6zN/8uF0hfu7bxT2oMWNW+WHLE gw/mztvDqHIs9tIwJTLfPcUXeQTj0erYd1QMN9gkD01QP0oXs3yUwbaTECv02O4jWSiI SWu+2KRV6DKf6YfhTyTRxHwJ9fZ1+s+ZzkyuuPW1RWWD3oSdFcoHlFWpBA3VbQmOSEEa Z+Sw== X-Gm-Message-State: AOAM532ck2HMEmdwQRSJpcqihRkHDQRlVKrf2Fx+Gzp3gPw5OtpUbuXx uXZ3lSGfPYo1FlvqsO6NgK1zeK4EFYtKfg== X-Google-Smtp-Source: ABdhPJyX7zviMAo8qcd1AVgAzRb1aJcOOPI9lWgjUTJqeXgXr5qjOYLmKa5tKYYY0Q38WO5dmAo0Zw== X-Received: by 2002:aca:1817:0:b0:2ec:f542:c96c with SMTP id h23-20020aca1817000000b002ecf542c96cmr2097123oih.36.1651860169421; Fri, 06 May 2022 11:02:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 02/24] target/arm: Drop EL3 no EL2 fallbacks Date: Fri, 6 May 2022 13:02:20 -0500 Message-Id: <20220506180242.216785-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::236; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x236.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860546255100001 Content-Type: text/plain; charset="utf-8" Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local vpidr_regs definition, and rely on the squashing to ARM_CP_CONST while registering for v8. This is a behavior change for v7 cpus with Security Extensions and without Virtualization Extensions, in that the virtualization cpregs are now correctly not present. This would be a migration compatibility break, except that we have an existing bug in which migration of 32-bit cpus with Security Extensions enabled does not work. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 158 ++++---------------------------------------- 1 file changed, 13 insertions(+), 145 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 9ab8b65e7b..ea2788b3d5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; =20 -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0 }, -}; - -/* Ditto, but for registers which exist in ARMv8 but not v7 */ -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D { - { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, -}; - static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); @@ -7902,7 +7784,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_EL2)) { + + /* + * Register the base EL2 cpregs. + * Pre v8, these registers are implemented only as part of the + * Virtualization Extensions (EL2 present). Beginning with v8, + * if EL2 is missing but EL3 is enabled, mostly these become + * RES0 from EL3, with some specific exceptions. + */ + if (arm_feature(env, ARM_FEATURE_EL2) + || (arm_feature(env, ARM_FEATURE_EL3) + && arm_feature(env, ARM_FEATURE_V8))) { uint64_t vmpidr_def =3D mpidr_read_val(env); ARMCPRegInfo vpidr_regs[] =3D { { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, @@ -7946,33 +7838,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &rvbar); } - } else { - /* If EL2 is missing but higher ELs are enabled, we need to - * register the no_el2 reginfos. - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value - * of MIDR_EL1 and MPIDR_EL1. - */ - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_NO_RAW, - .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); - } - } } + + /* Register the base EL3 cpregs. */ if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, el3_cp_reginfo); ARMCPRegInfo el3_regs[] =3D { --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860356; cv=none; d=zohomail.com; s=zohoarc; b=Pl9O0YQ+OruDunNCneNCpJW/dPW3puRnpmM0qhGc7qv9jrhmJ9d+OtYQfbCVK2yU/eX1QFKFal6mcsAG0QG2B2nKDS6ihWxpD49DJS3fDcuTm6UWOxlrSI6W66vmNbNiQjX0Qe4+g70rxwndEwqPdE+vR93FqQGFQ53tBAKWy5s= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860356; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=4YqOGbb38qjiPY2dXCdLJrEWMXvDZh6b/gyG/7bmWLA=; b=NUjeTekYuk9TBcfzde5GututeoU9bK5S7BVfNxL1Bsd8Ky9ghZIUh4kwpLUdz0L/EjYHfoxIP+j1bA4JtRSMVxiJVmvw690VQa9NWYn+WgtgMuqty20VwARi9qfBatE0bA/y8tF8r+d6KhivSmeYqCrgb6iA01Gxs/r93u0lDoA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860356098634.3558548453981; Fri, 6 May 2022 11:05:56 -0700 (PDT) Received: from localhost ([::1]:51204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2Kw-0000eF-8X for importer@patchew.org; Fri, 06 May 2022 14:05:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59492) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2I1-0005CH-FO for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:53 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]:40650) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2Hz-0003q2-S6 for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:53 -0400 Received: by mail-oi1-x22d.google.com with SMTP id y63so8288915oia.7 for ; Fri, 06 May 2022 11:02:51 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4YqOGbb38qjiPY2dXCdLJrEWMXvDZh6b/gyG/7bmWLA=; b=IdsrfcLZ8C03H55YUSl/U83BSKIlU4ZHuCoBO/cHOqftzrO88aBwlrh9tD49aF7sB6 bhHKBX79dfoIw/6HtqDXrPwUeITfgPHbN6IIrNP0nVevYNGvFRy696qYGbTi9SgsY2dA 8rnGp40uhml0l1IpCavyvjBBl06oee8tWQBOPX+gsQNZGPazl2ntzkQ4D/pBDDNwo0wB mrQ5AtsX7XiKd8TnkyGjRKPeF7cUpFTvPzzNJRVtBTPG1UA4vOUDc8yhuFaGc7mo/Wrp 8oHSMVskAxu5TQu0tavzviCyqVv93tHH64BZMZ0DkZWQ9149ATNHae5QT5jgB2MwHq0y n2hA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4YqOGbb38qjiPY2dXCdLJrEWMXvDZh6b/gyG/7bmWLA=; b=ERKfjtcS3/Wy2HbbT6zEkkkknlr2BG+OMAQ+ZDptmlBY/z1Lfu3JAKNPMRUOqRhVZ3 m626tZkBYEFPQZV0Hxl70n38xVXNvm/NRBrI+c4bzT4aRouzqwiSFKxznfPcr7i+kLrG 77AAq1STrHnXbhe5Ucj4QArNdy+FxdTDLNqFH6EHlqKcEdqOzykaU91vFn3dwEziU9Kc klqif7ElkiVeTieDrvtMSp/wGaKGqdgin3YRZhca3pi5m5g37+UytlsayyD192ZXYMbr tJAWpZg0WyUQ3wtZ9psNH5SLvhuPIXvM28dqi/M1kfBY9IPyTyjTyMX64P3jqV27Bw/5 x7yw== X-Gm-Message-State: AOAM532DJLDCkt6eav8z1QTT9obEbHI4kPnw4ThulJqPhD7fIjpz/A8H 4gmZh7je/rl+NPUTgYYT2zqfiIKCpRlYGw== X-Google-Smtp-Source: ABdhPJy6cdvxPeXrU1R318y1wwScHHNZrLChiUwVd2EfoylTthTesOSYdNQCRXU/oSRN+UIQLyTCEQ== X-Received: by 2002:a05:6808:220d:b0:326:4eb1:6911 with SMTP id bd13-20020a056808220d00b003264eb16911mr2128189oib.200.1651860170775; Fri, 06 May 2022 11:02:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 03/24] target/arm: Merge zcr reginfo Date: Fri, 6 May 2022 13:02:21 -0500 Message-Id: <20220506180242.216785-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860356979100005 Content-Type: text/plain; charset="utf-8" Drop zcr_no_el2_reginfo and merge the 3 registers into one array, now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped while registering. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 55 ++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ea2788b3d5..72d05070f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6122,35 +6122,22 @@ static void zcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static const ARMCPRegInfo zcr_el1_reginfo =3D { - .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_no_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore -}; - -static const ARMCPRegInfo zcr_el3_reginfo =3D { - .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write +static const ARMCPRegInfo zcr_reginfo[] =3D { + { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 void hw_watchpoint_update(ARMCPU *cpu, int n) @@ -8233,15 +8220,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_sve, cpu)) { - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); - if (arm_feature(env, ARM_FEATURE_EL2)) { - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); - } else { - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); - } + define_arm_cp_regs(cpu, zcr_reginfo); } =20 #ifdef TARGET_AARCH64 --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860554; cv=none; d=zohomail.com; s=zohoarc; b=Q0Uu3K8PqIcl6i0WTPsePNsuhFmpAK7PKIQJ1Ws4DVuIC9q1RQPuPkNF2ZjtrwC7goGanywc7ZWdufGpKqB4UA90aQBuvq04fpQy9J+cFaODuL29gPH3lTKEZIxGOj7GWwBwn+gERhFpQNm11PPx4D5Rx8kMz+mLXehsmJu5NTI= ARC-Message-Signature: i=1; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zBDZ88vPTqEGnY2FKq55qff77wGeCpGFi1CrZCVsHDk=; b=nyWnOsr6qBdaLl8HsfRZJjCu5x+U4d0tsiENH35bL2NwRF+FuKWU2iNVM9xvf/fgPD FLZ76tET77saNgxIpuwjAUmaMkeQw+SBZvggyBYOaR7YI1LN8wxIVLvISaVKMvdRSH9h UuXWneBPgPnnyf/YO3bni6bNPTGoBIcSSRtSTGQZWu/iVBixoPB2VlEgjIR4qCuKbn5c pmYMnXoUcLzyZ97gBSr0V/aoa0cDp0aBPhLIQh34CTiG3azVf2y1+gBPB1mreF3E9eCU fPkw4/Xyifeco4lFVnxvE/9DsRFLCZjq3lqbIa/RGbJDBMwZ7p8CJr2g3I7439CEd8Du QW8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zBDZ88vPTqEGnY2FKq55qff77wGeCpGFi1CrZCVsHDk=; b=U3e+eJqXAphsrOPdDmXXmt73pS5MdHi14lxfiJSaD3dbKA6SiuFI2hOJYJPL6l5iLj H543HRpw+OZA0kzE7l2+KIFpkBZ5cYFi4RImzkm1aEudpT0qzS79GZTTcOZFCF9B3mjc HfpR2EYsOVGb1CiZ3Dm1xNGagZaTp+xvG8bQgDzmKjm6qetT2u8ZteoExWD0iHBk/IpY 1l13EjGSBe7J91iOlg50ZhCqDUBnAAwPU4vi3dpiXKMLZ7AIjo1wsum+yqQxQ3m6C3QS ih8d5lXxjQDyMWpK9zD3vxMDYY42P3duaM3187puuWVWAtYZ7rbW8aLYc3/axPcrvQlN ftYQ== X-Gm-Message-State: AOAM531bUkEdS8WgQ6VWspDK18W6OOBJeECsn0LXQnHuTGQX/Ayro0PM mGeecbr6NMdxEhT41cfO+yb2lwHPeWPyo8PC X-Google-Smtp-Source: ABdhPJwF0hBGBnXcsr7XdDe0BArkXJSZA96nxJFPR3CspkOW3ZfAyTTIRbrFnT5yY7bOF2dwLR8JtQ== X-Received: by 2002:a9d:37cb:0:b0:5cc:7a51:c984 with SMTP id x69-20020a9d37cb000000b005cc7a51c984mr1461553otb.98.1651860171954; Fri, 06 May 2022 11:02:51 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 04/24] target/arm: Adjust definition of CONTEXTIDR_EL2 Date: Fri, 6 May 2022 13:02:22 -0500 Message-Id: <20220506180242.216785-5-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860556215100001 Content-Type: text/plain; charset="utf-8" This register is present for either VHE or Debugv8p2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/helper.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 72d05070f0..7b31c71980 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 +static const ARMCPRegInfo contextidr_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, @@ -8215,6 +8218,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860441; cv=none; d=zohomail.com; s=zohoarc; b=XQHh2B5zJC6iUFsTGkgebIdtKi4cBC45jA+d7TO/OswrDe1jbQNCeigux9QutJu8joZ5asoLCcAMY1nYHeLAO1vJwpjGqCTO1wa4EYoXsKH+5jPkv4rrogvqreNJwGFVN1vpSujRZ04t2xKyU4w05FkuPr5ge1GgyHschELSkwo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860441; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RP7uxMyjyjVvNPdZI9ZcRwKJ1kV5jw0hdIhEr9Ry6LU=; b=e0f1qWYm0gixHkjT8xxa62woR1LoY9/uiOpXZHbvzQd4pv6vIQGzb/kGh0ZpaLKcyBqN7bAs5522jHqXQ5tiwFFYgKZWNkE4J0gJtsxKfMFiyk/Jul+T2mfIfa2LR8hluxoCZ6KRTmwzmv7NALSIAR3siuJ8qCwXXx3utWW4674= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860441903481.1205349806695; Fri, 6 May 2022 11:07:21 -0700 (PDT) Received: from localhost ([::1]:54788 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2MK-00038k-Qh for importer@patchew.org; Fri, 06 May 2022 14:07:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2I4-0005Ne-LG for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:56 -0400 Received: from mail-ot1-x336.google.com ([2607:f8b0:4864:20::336]:46692) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2I2-0003qy-Jd for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:56 -0400 Received: by mail-ot1-x336.google.com with SMTP id k25-20020a056830169900b00605f215e55dso5407097otr.13 for ; Fri, 06 May 2022 11:02:54 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RP7uxMyjyjVvNPdZI9ZcRwKJ1kV5jw0hdIhEr9Ry6LU=; b=m+rkv4PzkNdVHUyOisQWvBCRsUi4FRoADJA6lYX2PJr2S5rCPCT5l94cwGCAKR4YNd F2uGYLPoAU85+vbNQ7ugLSfeSNZbaNqEC5mf4+IwUTDlGNMDHlKtmzeblU32Hk/Om1cg 4zAN97xglXt0q/xiH+NGMICx0BIBmCIMGpkDenJuOaHdSC3AhJQO1S5W1WGv51fQ+eVM GlwT+uDdVCk/DUjco/3ZFQl7vk3NscertbsURpHAgj8apXV+Li9Z86X+7xnqOFLXZyJh Ux15EJeKijZ3FhgCOXA/2Gxs3mlkcdhVSD6KpNsWdYihhzT7Ii1lxlDuQKQRH5t6qhWX oCAg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RP7uxMyjyjVvNPdZI9ZcRwKJ1kV5jw0hdIhEr9Ry6LU=; b=irUtTB/n2h/uym4z3eH5ZGxxpo15fP6bS/5kLLMYZD2HzF2JHQ7JzgYsZ2ryoE9ycP hnbpCjEOfpAHuRe8tZiyo12gTyi/AiUP2Z4kI1jhUXann/eZrCsdEMFYHALNoN6sd7bv BcznajDAapVFvW7eDS//dq+3b3WMxGml/a2cfC4S7OEPnn8tnSfulLtN+2EdFeUbLsvH uLrNj5KAiQCleQBmi8ES1YlOXNpaLCya3o9wsoh353/d5qEDbljw8QyptAIN0gqeh+aO TZPTl74O5baYN9k7YDS8QlBOkZEY+p+Eu30y/L3ENxoh831h0dunvecEOt/nFSjr4/ap 8zTQ== X-Gm-Message-State: AOAM533RpDjlBvMJuexH2GpG3XwKapkxO0BX8Eawme2olJ9QWoOQ0nd0 wgqcz5EJVKuNO0csc17OAmOIRc2XBfSXscoU X-Google-Smtp-Source: ABdhPJzvV5Kd5bgDeFUxSjRes9IoHacISsGD/A4YRVfSEcSUSYyIvhhUx6A8JflNA/sFa2zHXiOCag== X-Received: by 2002:a9d:68cb:0:b0:605:f1c9:991d with SMTP id i11-20020a9d68cb000000b00605f1c9991dmr1477619oto.345.1651860173282; Fri, 06 May 2022 11:02:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 05/24] target/arm: Move cortex impdef sysregs to cpu_tcg.c Date: Fri, 6 May 2022 13:02:23 -0500 Message-Id: <20220506180242.216785-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::336; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x336.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860443547100001 Content-Type: text/plain; charset="utf-8" Previously we were defining some of these in user-only mode, but none of them are accessible from user-only, therefore define them only in system mode. This will shortly be used from cpu_tcg.c also. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: New patch. --- target/arm/internals.h | 6 ++++ target/arm/cpu64.c | 64 +++--------------------------------------- target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+), 60 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 255833479d..343b465d51 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1307,4 +1307,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteA= rray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); #endif =20 +#ifdef CONFIG_USER_ONLY +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +#else +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +#endif + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c841d55d0e..33a0a71900 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,65 +34,9 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" -#include "cpregs.h" +#include "internals.h" =20 =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; -} -#endif - -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2CTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, -#endif - { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ECTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR", - .cp =3D 15, .opc1 =3D 0, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUECTLR", - .cp =3D 15, .opc1 =3D 1, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUMERRSR", - .cp =3D 15, .opc1 =3D 2, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2MERRSR", - .cp =3D 15, .opc1 =3D 3, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, -}; - static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a53_initfn(Object *obj) @@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a72_initfn(Object *obj) @@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9338088b22..d078f06931 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,65 @@ #endif #include "cpregs.h" =20 +#ifndef CONFIG_USER_ONLY +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; +} + +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { + { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2CTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ECTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR", + .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR", + .cp =3D 15, .opc1 =3D 1, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUMERRSR", + .cp =3D 15, .opc1 =3D 2, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2MERRSR", + .cp =3D 15, .opc1 =3D 3, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, +}; + +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} +#endif /* !CONFIG_USER_ONLY */ + /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860551; cv=none; d=zohomail.com; s=zohoarc; b=hnm8AGYt4Aaw5I4du3ZWWzZ5IQGXJPcxhCbqk3kxhlhQnTDIdsWfeG3zvA6n4GaOXz5QdzpojEH+rI+AllUuA2udk1dDY5G7lh+hFwjSRM1RUw1WpqBEmuGkxxPpct6iD2qsZESR0HwyfjF4fyxLhHVzpnmMex+YqWrBz2IU1iI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860551; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=UglyDtIiGqvTEpM7++4FJGDf8c2/b7gl9ujFn0OBb74=; b=Ej1UqKl2x34MddRPdNThTjOqWJPszeUkdPlzKFtwMUlo27yxJn3/zZ/mnKYB4DPdO3UGbqavpN15dLKZS1mcQQC2P+5kAGVjwKsFP413haGEP8eSpKVVXBzQZRQduryMi7iRPGUw8VN23ymM+lFBUMOKlG5v/Jk7Lbblj1HJPJI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860551753781.4144473370583; Fri, 6 May 2022 11:09:11 -0700 (PDT) Received: from localhost ([::1]:59676 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2O6-0006QI-Ib for importer@patchew.org; Fri, 06 May 2022 14:09:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59614) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2I6-0005Pn-BJ for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:58 -0400 Received: from mail-ot1-x331.google.com ([2607:f8b0:4864:20::331]:35635) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2I4-0003rP-03 for qemu-devel@nongnu.org; Fri, 06 May 2022 14:02:58 -0400 Received: by mail-ot1-x331.google.com with SMTP id z5-20020a9d62c5000000b00606041d11f1so5424820otk.2 for ; Fri, 06 May 2022 11:02:55 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UglyDtIiGqvTEpM7++4FJGDf8c2/b7gl9ujFn0OBb74=; b=ns3Fm158nG1omQ6h+hpiBym00CFOu3j9iowyripCITbdE5w0dIU+kGW590kUbxsV+k tmYM1OT1zwqxRgeusaAzETHMSfx5mmwM9DBftDkM7PWmLzj7BzVx0AARPTk0FdRuq00q QfvsgDvHvDuNvR6EBP4MzCk7P0hDVhGDWavKwnUf3WugxYmJemzpX592xTvuD4jqn9xK z2R0UPa1tvTdvgdd2f+GpB98YwnjPbjGgX9ntUNCRrDaONKJVmDwRkjsGyLNd0s1Aphf f4ybOJohHqvzg7g9lSGRqYfL8tbzDtYQnY1FJ74j/8oG/LSc0xC6+lryDoXUtisID/r/ gNRA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UglyDtIiGqvTEpM7++4FJGDf8c2/b7gl9ujFn0OBb74=; b=QErWvEMJK9A/YBBsMu/N6hUDDoSKwP+NzCjD50fjVyeIY8sLW+8sAsqxYuXOFfJnWz kSzOpOUsTpgDgOSf1yB/8j1DHo/R/YSuferBJGF4Oom3vfagZPlDGpiUrIZdXtKsBozF CvmJtyVYb3WwHdIU9MJwoP0pU+LJfrfPm1DbcLSmkwyG7BjpD5q5VH03eZNOcXIWyVcB TO4nD/e4/Gg4+Cjl7oNv+XRmRN+qCjXt66tyOf19RVoVKGJaj+uo9DDKXb4s6SFEpBBu /khlzZxapd/a65XeVluhzLpXaSaluzbqi+dveJugjDX7fI20s21mLnCrER3zkQ+mIT/P xBZg== X-Gm-Message-State: AOAM532PcgYmP2+AG+LiSR36TpzKtk9LFadlMl6UqPVvt2Ng3+CMMrtu MpoPxKO2pg3So374fBGbQdvrtLwDmAr8gAFk X-Google-Smtp-Source: ABdhPJwt7Qj6U+pZqXMBOeqKPqZVJuEcWFxbfxJMkVEaJqvm4PKaE7o0HSCnPQ2sVu6oXkbt3Z7M3w== X-Received: by 2002:a9d:5f16:0:b0:5cb:51de:6761 with SMTP id f22-20020a9d5f16000000b005cb51de6761mr1509647oti.139.1651860174786; Fri, 06 May 2022 11:02:54 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 06/24] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Date: Fri, 6 May 2022 13:02:24 -0500 Message-Id: <20220506180242.216785-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860552233100001 Content-Type: text/plain; charset="utf-8" Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Create impdef sysregs; only enable short-vector support for user-only. --- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- 1 file changed, 92 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d078f06931..f9094c1752 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -994,71 +994,104 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t t; =20 - cortex_a15_initfn(obj); + /* aarch64_a57_initfn, advertising none of the aarch64 features */ + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; =20 #ifdef CONFIG_USER_ONLY /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. + * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. + * Only do this for user-mode, where -cpu max is the default, so that + * older v6 and v7 programs are more likely to work without adjustment. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif } #endif /* !TARGET_AARCH64 */ =20 --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hr9XVqQdGgVN9QhGevO5NcMkH7ocZJOMtPxHUW2biKk=; b=zuRChkffAAnJEbWXGmEPNva4T2icaZo3AiJflLEEAs7zu0rWzGERylXz3unj54Hqyi 93WmOOc0cTi3kXMyiHT0rp1k5RkuwHdHNkzQ1hWoh697PBiMbcWJOTmdjdeOdxAbAWzz iSJNtlejJmGcFySg8EIpaDXrCo4NHwoyC6/ViQj/XXghENjBMIORR9+BA+u8PYu+dVX0 bBkhoQzSmiw3nH70s5RENB7RLF77c4Te1RiRR6kQd3eOMJiWXR0L5o7UuMtqgpCouvs1 IR9lU3G4R4gdAwlpW3fp5+TGh35+i60B6LLYagym+PF6rYnyWPEDgjv7rsxIZPy6Ukdu 1cbg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hr9XVqQdGgVN9QhGevO5NcMkH7ocZJOMtPxHUW2biKk=; b=PDHiKG0eKz7LB8Wm95ZIV1GvSPuFDbn6gi7cp6iPuheWaqZ49cBEJ+k88QPOzgzRmR h3r/FGTNoEtD0/fSghFUk+pYidyUXLRDwLE7h0GnRg7S7qITONv64ESikNsXwQmBjYJs whWMI1DUUO9649LWtFZa5iXd79x1o4vjlvZYQyux45ljXLk1v+4H1NlhPJYyv6r2PPW0 cqzjA4yOZQDOB9zKaOm05LQKnZLAjuAxisGt3OBoTncTFSjiEf2SED+b0qG2fz30kqAH pBCjehLSXDBSO3FAeh3GxeQwBC1TboAGAT3NRCqNbLmmHTwiAAg9c3pTFq1tzZqwi7hN DWeQ== X-Gm-Message-State: AOAM530qESvqMrfZY/ZC8SFujFYAnc4SU84RJlDnnTzZiuhqpWuNkb2T +/eU9tM/nk6a2rWfPI2pW3EQlMVH4aSGtH/t X-Google-Smtp-Source: ABdhPJyhw1TAdzD0rBV+oifLcEgFtR6OzovfxgnRfCdlGOSU2OoLbyg//kgazw63Y/hzxmVA5LX2XA== X-Received: by 2002:a05:6830:2f3:b0:605:f29f:502c with SMTP id r19-20020a05683002f300b00605f29f502cmr1461363ote.24.1651860176362; Fri, 06 May 2022 11:02:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 07/24] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Fri, 6 May 2022 13:02:25 -0500 Message-Id: <20220506180242.216785-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860618582100001 Content-Type: text/plain; charset="utf-8" We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f9094c1752..9aa2f737c1 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1084,6 +1084,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 =3D t; =20 + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; + #ifdef CONFIG_USER_ONLY /* * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860773; cv=none; d=zohomail.com; s=zohoarc; b=Whv3qnPuRflO9xAvEG4A2CgpxgsULKJX19RTtDfWSVGhq/cEvYAkqSZQVxi+m1Dr5XodGQGd6/+IXm2Gj3ZYVZb1vtypZ+azDWOP3Terqyan1sEFQwUW50RyQJWdYmU+y4Xh+2CA0Qen2Fi/TFmZPwZ3kGdjnqwu3GiLotrVQWg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860773; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=PGHFtJCWwmKlydMV+7EArb7n4KOf/foV/LwhKZjMzG4=; b=mGOH4rsnNmlluJeNaoLQT0ZLTFmnGsLxgQ5nLvVRunAIUl0gBBEBaJoqfdUmi92ELyBdMj6Zv/xd7iocuV4rx7hF48YbWJPbSFFih1yn/6DBcIr6wRdrr9u98RzSWZWjoI3fuoThkkcVxPKba0bnkY3qPRaWT18N+w4HmpGC+Xc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860773677279.2635851811898; Fri, 6 May 2022 11:12:53 -0700 (PDT) Received: from localhost ([::1]:41416 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2Rg-0005D7-Hh for importer@patchew.org; Fri, 06 May 2022 14:12:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59684) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2I9-0005b3-NN for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:01 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]:45546) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2I7-0003sN-Ky for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:01 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-e93bbb54f9so7965018fac.12 for ; Fri, 06 May 2022 11:02:59 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PGHFtJCWwmKlydMV+7EArb7n4KOf/foV/LwhKZjMzG4=; b=guY6Sf5oem6IhmTAOYwgp0THeDNYdDp+VVs9KX+MISThnw0m2oZPF8159ljg+WW4gP 6i6Rth+vW6Q4BSxf9z1vdJMQkBnLxDQ9f5Gvhxj7F8EEfUsMfDK+g/f3oY/gyzMCMbMy qjdjBunS6qrKV96IlCaMB6uFkY5YD2bi7OKjP5+kzSxXuZ6SHA+iU2BvO72XH9Z4xTL8 ZzQJsCy0REfdBtx4eqbK+T0cg37uKj5LrotMLUEvqtnLZDeZKIXyl2HfCBcQSuQOkn3S kVpobDPcwkmnVUhILKWso69jhhTbRAFa/JrLYVrCR8OqGeU6eZpsVkIpcbo+A/jl7pFM KvSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PGHFtJCWwmKlydMV+7EArb7n4KOf/foV/LwhKZjMzG4=; b=xFw2ff5dFtP+ZILNwmAQTyNv04BwyLImvuAj+PYAqgay2+XPQ5ea1YzP+fOVUdLU48 ir+yupcnR5D7wdAz3je0GOhPb2JYGit6HY3Th+5M6qTkjZfJzYJ2+TyfkpC1o7B4ySCN dKLiwODdHcmxOuwKkbdygsOoiji8PFR9PdFz7t45na4HJhlEWqIvTGx8dxhE5mZbmCp0 AoTgya6W/H5K3JSg0tJhYsyEPgxnLIu7G80v7VeDeAQZtTWCl01MWL1Ky+KcTfTqNHzv lk/GTR2KYaIbaqmodWOyS8l6PuafDqBkEyxEkVf4+Lvs3mvuN5t63Ogv0xQ2j6aN9Nxw cSuQ== X-Gm-Message-State: AOAM530kXLYFWm0SibSldYzCUTE8cLfIYOQQc7CoKiEDd7MZnwaIXNOH MpCmp7VdHX7V/SmIm8/ccZp6HWeR21lFrOAQ X-Google-Smtp-Source: ABdhPJz/rX275rPyhtZx+aIle6tb+N3IaRXEeR8+XM+PhkrxnhSzYeth6/bNbhCmOxZTszm38gxEbg== X-Received: by 2002:a05:6870:79e:b0:e1:f5bb:4627 with SMTP id en30-20020a056870079e00b000e1f5bb4627mr4989324oab.74.1651860178032; Fri, 06 May 2022 11:02:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 08/24] target/arm: Split out aa32_max_features Date: Fri, 6 May 2022 13:02:26 -0500 Message-Id: <20220506180242.216785-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860775520100001 Content-Type: text/plain; charset="utf-8" Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 + target/arm/cpu64.c | 50 +----------------- target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- 3 files changed, 65 insertions(+), 101 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 343b465d51..c563b3735f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1313,4 +1313,6 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +void aa32_max_features(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 33a0a71900..6da42af56e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,7 +682,6 @@ static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; - uint32_t u; =20 if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ @@ -799,57 +798,12 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); cpu->isar.id_aa64zfr0 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D t; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9aa2f737c1..b0dbf2c991 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,66 @@ #endif #include "cpregs.h" =20 + +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; +} + #ifndef CONFIG_USER_ONLY static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -994,7 +1054,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t t; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -1035,58 +1094,7 @@ static void arm_max_initfn(Object *obj) cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - - t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D t; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.02.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:02:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z9jnYlb3diHDx/Tz1NJJu7ooSfZI5A88/Vi2Hs36v6U=; b=MZhgqYn5lzXpIWQxi4le+lVZ+ZsmcV8d73zea2AeM/qgfeZdbmhb5/mZ2En5L2ysFt 92gv9IJ8njmsNob50Ba/+ybnFklGn/92Go/bZCsCwqA97/fu+ThDNfABi3wG771lWHfa HmnGcod+9yHrbLkYank2TjXqqdPdokuHDDvol3UtsD4LPhYczSEK8bnUsS6i+4WiNN+F ayF8FgL+y6wkgQLhMVIucz2y74ipbfYLuPqzASp/CnAITZhVqicLqVAr+t54+LJgg+2r FabAukJdx6AVKdADO+3L1v5XmTFtZKVVF/8XiVM8leLKHxjU+2p+7/A+bYX1FgZlg5Vn +z5Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z9jnYlb3diHDx/Tz1NJJu7ooSfZI5A88/Vi2Hs36v6U=; b=GwEqDKDm8YZ5TZTX9IACZV1aHDe2X1Yx5eHKVcYKWZmN1H3d4yuB37FZvzcGpWRKdt CqTbsdI0YC+mV9y21YaVjMbbUSb3f06mnZCfdlQJJfOz1X+6G/oXVg+kYxxIcs//J5La AMpt7WOhOYGPgh5vXXoOptj7rdXsqNeaiEgmnezrHoU82D9T2NtNJ4vv7Vc54/6fuusi YdBoDX/So4RNn3Z2JB2WlAvFGVHbw4q9BzVkw4Lcaurao038+7S4WBX0MMn4lyKxZXN9 itz0phWc3ihDvdx43zryhC9B53Sbp5C41v8RwpKnkdVfhUAb1J4HAR+RE0obSNWyAcIq ftCg== X-Gm-Message-State: AOAM533OIPa+AEng0DzZLW8pdJKUoR4BROc21DWthSOpHr45X+zjhHCc bEbKwIJIYIU665mml+SuarkYrejh2X2+Tg6C X-Google-Smtp-Source: ABdhPJwh6pJPZKaPJgpuOoRl/yqZ5ClKfkVjQhIqzu0i+5mMxp4vaFAyGQ1Jt92ezZfmET2oqfk2Hg== X-Received: by 2002:a05:6871:97:b0:e6:30e3:31a7 with SMTP id u23-20020a056871009700b000e630e331a7mr4798114oaa.150.1651860179613; Fri, 06 May 2022 11:02:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 09/24] target/arm: Annotate arm_max_initfn with FEAT identifiers Date: Fri, 6 May 2022 13:02:27 -0500 Message-Id: <20220506180242.216785-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860962494100001 Content-Type: text/plain; charset="utf-8" Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- target/arm/cpu_tcg.c | 48 ++++++++++----------- 2 files changed, 74 insertions(+), 74 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6da42af56e..5fce40a6bc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -713,51 +713,51 @@ static void aarch64_max_initfn(Object *obj) cpu->midr =3D t; =20 t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; @@ -769,37 +769,37 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b0dbf2c991..bc8f9d0edf 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -28,55 +28,55 @@ void aa32_max_features(ARMCPU *cpu) =20 /* Add additional features supported by QEMU */ t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UA0u5zIb+IjVjwjFedkOJVeM7leXzM2MF4hE+Hu/fBc=; b=thPVG18bZksA4Iu3Pgbgd4oHouv8p7dZRJnlJpS9tdBGdtQ14syu3W3EMV5cl8a3Oc 3auMfcBvNYOrCZFNwR+4m8HS/QwNHKZNreLpaFsifDbhtgQtEUnSxiT2H9Q2nbd6VYe8 8MzkAUANt5TjiOC+8/DfmWBH8pkQVcj6TACBOYz3VyfOwP1w8gVIlz3S4RKKi05s3CH7 l7OHZNd36XSKV/1HBWpDlFEoEh3UabHjuEDX9bbwzuxSL0Nzw46ggBYZSa1gitmgG7u8 QHQmTwnPoEWrxqaBTNSyPvgitpFSyqCgUALd9gaONVnUHhRmlNntQE0zi0LkeB/IDpeK 8BmA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UA0u5zIb+IjVjwjFedkOJVeM7leXzM2MF4hE+Hu/fBc=; b=NxbH1oOoEnF81UrApJHykOSbRWug4wAEpQYW0Ak+il3VsLv6Yqn9MNlh1vDWNdXsO1 tfh5Cjg9fDfNDgVNCoa+yLw97f4msx46Pr5x6B1jSSfm6OwjeHv8bGOGc6bcIpMjYYNn O44WSbhHL72BdOgzLz0c3RVZ5z1qWjX92Fd5q8qSJY78aZsfz2EptWIXFnT2h1Dan8PV DO82j3dcsLGaVQrZGIkEfHmnrziqe9x/fT7dH3bWX0yLd4ieY5Gzj0/HhZf26OJgkwu9 7WZe8uCakloK3YBh+WAV+Jh2btQZTrp6nEUx5t0m2ZHR3d17ja9GWSbjGouHWLDtFezU nPSw== X-Gm-Message-State: AOAM532k7ln5/zCNNC2kV3+dDe0mtDisUBFklya4rBK8RxWz1uCiexH6 QTpUEZkyiwVaw+/jXMmR+PBpoG0S9gfoBIU4 X-Google-Smtp-Source: ABdhPJy41zqaCfcvz+jGapLPJ5ffBJp7CVxKbFj/0DtH35TZjuIXgbgzvqUzkhU9N41j68lObMULYw== X-Received: by 2002:a9d:74ca:0:b0:606:2168:8b63 with SMTP id a10-20020a9d74ca000000b0060621688b63mr1463784otl.249.1651860182218; Fri, 06 May 2022 11:03:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 10/24] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Fri, 6 May 2022 13:02:28 -0500 Message-Id: <20220506180242.216785-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::335; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x335.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861143077100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01176b2569..7995ff2712 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860847; cv=none; d=zohomail.com; s=zohoarc; b=eRh7dWRhIwfp982D0TmcFhXfJ5qjrL0bk0hQjOmEU62kgygoL1cAedV9ZO6eYwf3bxBywX0B0UOqzClV7bXCIY0f9LZEdf+CbLZZkmg6VqDPkwmmbt5SnOX6gizn0gC4CFYD2MUKsTVoLCQUhfor/XdS4QniwnZbiHiLtSeFLyg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860847; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BIWTkf1wrFK+RU/H3vuJZSVWXtZJEi+LVYp9vG7Klf8=; b=KbAfAURRNiHdU9ULGSo8yEw7QPhBsVXZjDUUgC9MQJBp+EW8maKosLZ9KDKcpw2ujm6pHFivOW2ZwGVyTaP8jygcCFZ44iMd/m03T7m4QO2QZiDHz0raMukx1iV8pIWsJ8iAijFmu1NCcBRBiYGJ8o6EM9EjbUS/2HjovrUymxo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860847941759.6868410572306; Fri, 6 May 2022 11:14:07 -0700 (PDT) Received: from localhost ([::1]:45264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2Ss-0007lQ-SZ for importer@patchew.org; Fri, 06 May 2022 14:14:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59772) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IE-0005oX-3O for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:06 -0400 Received: from mail-ot1-x333.google.com ([2607:f8b0:4864:20::333]:34382) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IC-0003pP-Ba for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:05 -0400 Received: by mail-ot1-x333.google.com with SMTP id i25-20020a9d6259000000b00605df9afea7so5424900otk.1 for ; Fri, 06 May 2022 11:03:03 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=BIWTkf1wrFK+RU/H3vuJZSVWXtZJEi+LVYp9vG7Klf8=; b=O83STiUUpUG4Loe8aD0NnL2XQD2Hz6AR6fXtJsao7086nBfCjp5KZo7PE23oDVPqeZ 3doZxdEs5D9QpUrIYvTVFwrUurW6yI+aANrAuMCtldSl9xeU8LnX68EZbWZ5+aDZKLKe ghBnZzpA8NhPMPu2vVvDxsPSVXMeVa8A+thEW+set7U6mTgdvSoSP+rfi996/1CAmkmm tXp5M/CN3/fnnz9gWvvn9Dkc6eP98iNb/uJ64pc9AcMsmQce7i6HKYrkDu4/zPURRw9X 3BSGeeRk90xHhtKEkwsDphVml2owLVZmVmCcbFqyBwiNsmQxAPax+m9bAFU91k2ImMRh RHSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BIWTkf1wrFK+RU/H3vuJZSVWXtZJEi+LVYp9vG7Klf8=; b=srO4Vep+12VWiBJa/sYBGwSe4EXSG/FpXe5KY7vI8RxYoUFC2waHwGuRmGFpdGQgUP rwPxKFKY2+e6bdHdWjYT8F13PGpgqV4eyVYlwxW5sk2eaOzm15R5UGIEvdfeu7uk7o2T igs2BVbcaTsz2EFhk+rm1iaxjxxpLmghenY9I9wiBYVSyBW6J7/dWbGQPMAvxO+iy8Oj etJM5nkmZZqRA7FAG+ynveQf8XzXhQk5BHRa7qA8cHul4jh/MfLZHyXmI56MsDrLKa+e cLuse/BJfhbLRuv3L4fadrk9jCBFIw3ZIaodx8lScHcyzUCT0IH349OU6O/C4cFDRD94 q8DA== X-Gm-Message-State: AOAM530wo4xTPQAXwKuTu+Bf4lv5BWxoAKF48JQjpSCzE6j78KRjY38u dEQo/mSdFYcwpIYijoFlEIAdEcO76qvWHutA X-Google-Smtp-Source: ABdhPJzjgcXxkYv3FnBI8T85iXGy5p4w9asyNfwxMpDKCWv1N4dP7QJ96VIqXYe+rTrNuq0zCaLZNQ== X-Received: by 2002:a05:6830:12d2:b0:605:e67e:edc5 with SMTP id a18-20020a05683012d200b00605e67eedc5mr1483232otq.326.1651860183672; Fri, 06 May 2022 11:03:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 11/24] target/arm: Enable FEAT_Debugv8p2 for -cpu max Date: Fri, 6 May 2022 13:02:29 -0500 Message-Id: <20220506180242.216785-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::333; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860849589100001 Content-Type: text/plain; charset="utf-8" The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index c3bd0676a8..965f35d8c9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -14,6 +14,7 @@ the following architecture extensions: - FEAT_BTI (Branch Target Identification) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 7995ff2712..2667aaf28b 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1806,6 +1806,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5fce40a6bc..202fd5c46e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -799,6 +799,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index bc8f9d0edf..b6fc3752f2 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,6 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860852; cv=none; d=zohomail.com; s=zohoarc; b=lyXHTGpucK7vGjU0WRpt1n5V1PBpZbBioVQyKmew9yEu0T3AQoi4Ukb3EtKRjE4X3KETP+siP+4xsEVU3WdwAvOJ+NQVMLIfyZWX8S+nZFw1FI6dWbbo5yqU5MMy3fIuikKkFctzGIZLLSG+vPr2rbRhZ+IzIonIQAOOjscguR8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860852; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=NgxsvnW311osB1m0PaTzB1/zyzTpUBL9MpOPjCAC0zA=; b=jP842CKEQ/Y5REfj8YaPyXBW05OxoBOSayAvWCyouHCXSHOQtHq+bgTZNSMWtefTxU8k66At8CWvxXgPYOmYASu1nvnmhRapyJ0t4LU0Z0yKbfRZkFGOFUh5DdVhIeR0M6DaxUGdC1wPDtHkIJziCRdhUgJpNbMxdiz1Hn5ngwM= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860852297874.9927977022239; Fri, 6 May 2022 11:14:12 -0700 (PDT) Received: from localhost ([::1]:45648 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2Sx-00083H-8j for importer@patchew.org; Fri, 06 May 2022 14:14:11 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59828) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IG-0005vX-1P for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:09 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]:46604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IE-0003ty-BF for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:07 -0400 Received: by mail-oi1-x22d.google.com with SMTP id q8so8277255oif.13 for ; Fri, 06 May 2022 11:03:05 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NgxsvnW311osB1m0PaTzB1/zyzTpUBL9MpOPjCAC0zA=; b=yFIq+Kci3xI/NMBh2KSYjJnVAeIWG6dqXE+NnqPHS5Yr7Kpzlurticn/L/AEhQkUE5 sjvn2RJ88ZSuw3pTVTppmIuanhdFhMINCYvyxuJP8BQ0WBBidyrSd84p5vbKKt2XNe3f 6YQXxRgmrm+ojesyF4ceARNkjmjnyockdSBNNsC+PuAqGpPDOP8nInIOda9pYHGqBBcF uh47/oiYI60o/AJxoeyZQghbi1FfQQctZLGlJLxrpXPCGb23nNsvT/AYsc53q0CAnH/E iiGUnwcM2KrhQi0mLqAcQ8kGeoRThOugCL1lkcG2q6i9h+Zon9qK545abGBp0ZoOZmhI 9BjA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NgxsvnW311osB1m0PaTzB1/zyzTpUBL9MpOPjCAC0zA=; b=cDBH72o6UzHeWvkRnlGEAKBAlrRRoUMbvJIHM6mRFJkILiAjvl4+9q+IDRwDujC02I tSORWp4wmxegPMldSB9Lvkcod+YV43JUNTsWAAgQnlKpmSWdmuYWWs+lAWp2y6poNmv9 RuX8RWEhyHeu0crKEGNjPHkE5bj3uNdCvtSltLdPmKeA0cMMYitwIK8BG/DMh7arRcoE JSIMNFpGtyH1ykJIGEjx9Fn27D7rlOJr1uZhPcpz/iepi2Hf6wJc7jOz/Uh4Mffm+M/L MAij3cqbLpVpj+62MRu78W5tfG7jyXCTXtukZm3b324Egv+nXja1msHyzSna7HFeGCsG 1i1w== X-Gm-Message-State: AOAM53357g64nN5a3/Dpz7A8akidQzorjrDtFDkoc+SKWQywl3GmmFvL /U4u9Rs2PAYj8pvzOAYTUrjtBw4u6ODIMVNH X-Google-Smtp-Source: ABdhPJw/GQypmEHO+ovhFNUw6oTgNBaUkq6IowTCLMirvtGKN+6fe0NkSwXh2GrV9E9cdul8kAlVFQ== X-Received: by 2002:a05:6808:2097:b0:326:6bc9:407e with SMTP id s23-20020a056808209700b003266bc9407emr5392575oiw.250.1651860185309; Fri, 06 May 2022 11:03:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 12/24] target/arm: Enable FEAT_Debugv8p4 for -cpu max Date: Fri, 6 May 2022 13:02:30 -0500 Message-Id: <20220506180242.216785-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860853601100001 Content-Type: text/plain; charset="utf-8" This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 965f35d8c9..0acac6347c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -15,6 +15,7 @@ the following architecture extensions: - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) +- FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 202fd5c46e..88d3cef93e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -799,7 +799,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b6fc3752f2..337598e949 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,8 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651860770; cv=none; d=zohomail.com; s=zohoarc; b=muKoNWlXJH8JlJKud+yCJgN1DlLhohiuTf/5dB4vom16MCQIOne/J5wWMhQP4t3eumqcEY7sM+mCA46Tun6a+MGFsPeCRIYK2bbrBBtZriYCIDmjRJzLaiWlBK+MaQRk5V9de/Io26yUe16aKQNBy7Db5rKOfXIPcJenSrAfTIk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651860770; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=gIDwI53sbDfS6sZLOTp4bVChNWHZq2iqQlUmdFQmUA0=; b=lcOFKlH2shR8PyRZCcvj5NhJZ9QXUMIVSYvH0LmOEbxYf7vZ715nm5eaukjARndu3NsMGcsbhrlpLqCoXNYHw+Qb6T6tbdXXaH7rw4t9UPGG9jR4lGIyrZksOcZlzoCy/4DVLvD+Wdm9cxEbuOEpi/CwaI7FjbbKONwkB/NxXMs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651860770774591.9674449810224; Fri, 6 May 2022 11:12:50 -0700 (PDT) Received: from localhost ([::1]:41250 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2Rd-00056c-LU for importer@patchew.org; Fri, 06 May 2022 14:12:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59858) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2II-0005x2-0F for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:11 -0400 Received: from mail-oi1-x230.google.com ([2607:f8b0:4864:20::230]:41739) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IF-0003nu-BR for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:08 -0400 Received: by mail-oi1-x230.google.com with SMTP id e189so8276376oia.8 for ; Fri, 06 May 2022 11:03:06 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=gIDwI53sbDfS6sZLOTp4bVChNWHZq2iqQlUmdFQmUA0=; b=aRFI4zneLPQxf9CcVlLWt780H/tT5AIzROUd+wJ7HRYpF4o0jb4LclaNatwsKxk/12 BKh6HpRag0rQY8QKEC94x2N6OkhO79gI9jfkGOuo1Veel7IIpL3FDlyqop5MHtL2gZol qvKx1k6UuuPHPgxka8GlpbEGtner8svwF5XNPQ3zcYL3lTvP3EVtFit0UUI2+fwKvCNM 2frxtGejcZY8FBTpt73BRXzp31wOBFOVDzkoZP/1gkJoD3BPSqfKqXUIeIw3MJKrCaeL lW1ygSy8TkYGkAzklsrI86/cgSUe9ed8zHn2FF2vn1UZq+y13oGODUqik7ChKyFZDe4V yhlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=gIDwI53sbDfS6sZLOTp4bVChNWHZq2iqQlUmdFQmUA0=; b=c/hj7wr/E7GFnnrTThU/ps2SFNiqefHfjcl+um+2GoE5LOtBDf2x97mt0PKzjSIp04 oMkqGuUS8CsDIogeM0Y5iWNGoWnAcRr3S5gNDoITIjPx/OhWSGVtQIdXLaRLzvH21sZW LgJcNAWB0v1d64OtDPjlCk7LyBbgF3ub1cmVIjpM2k0JtKzWd6d3yb2OI8hVp/18jcJW QEJUJaqQmU4Q+hY4vysy7L6si0Cmq4MJNqbZHKfq+wnNhz34vFCiGYYXXFsUPc7bRTDb Te/maKcHOQubTaVel/zG9uoL4M7cNlN6iiBPuGHJsfzqj6P5QUQnb60Hjpivz81X+MIG RiMQ== X-Gm-Message-State: AOAM5332ZMq+wOY0yVLAOWqb/sz1hckaNZG9UAUTk0TN2+p3NUfQbOG3 SbASlUkBZUYC+nOzelZjRq6irXh3NaddmEGM X-Google-Smtp-Source: ABdhPJxdRWq7ecbRKyP6vrTfOwjddHo4vXhh9XtmoA8tuRxf200umIdlCZWhy1q7Jz7Os//ytYNhSQ== X-Received: by 2002:a05:6808:1385:b0:325:efe5:b340 with SMTP id c5-20020a056808138500b00325efe5b340mr1923424oiw.249.1651860186658; Fri, 06 May 2022 11:03:06 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 13/24] target/arm: Add minimal RAS registers Date: Fri, 6 May 2022 13:02:31 -0500 Message-Id: <20220506180242.216785-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::230; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x230.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651860771339100001 Content-Type: text/plain; charset="utf-8" Add only the system registers required to implement zero error records. This means that all values for ERRSELR are out of range, which means that it and all of the indexed error record registers need not be implemented. Add the EL2 registers required for injecting virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Leave ERRSELR_EL1 undefined. v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca01f909a8..a55980d66d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -525,6 +525,11 @@ typedef struct CPUArchState { uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ uint64_t gcr_el1; uint64_t rgsr_el1; + + /* Minimal RAS registers */ + uint64_t disr_el1; + uint64_t vdisr_el2; + uint64_t vsesr_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index 7b31c71980..37c5e42bc0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5980,6 +5980,87 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, }; =20 +/* + * Check for traps to RAS registers, which are controlled + * by HCR_EL2.TERR and SCR_EL3.TERR. + */ +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + return env->cp15.vdisr_el2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return 0; /* RAZ/WI */ + } + return env->cp15.disr_el1; +} + +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = val) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + env->cp15.vdisr_el2 =3D val; + return; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return; /* RAZ/WI */ + } + env->cp15.disr_el1 =3D val; +} + +/* + * Minimal RAS implementation with no Error Records. + * Which means that all of the Error Record registers: + * ERXADDR_EL1 + * ERXCTLR_EL1 + * ERXFR_EL1 + * ERXMISC0_EL1 + * ERXMISC1_EL1 + * ERXMISC2_EL1 + * ERXMISC3_EL1 + * ERXPFGCDN_EL1 (RASv1p1) + * ERXPFGCTL_EL1 (RASv1p1) + * ERXPFGF_EL1 (RASv1p1) + * ERXSTATUS_EL1 + * and + * ERRSELR_EL1 + * may generate UNDEFINED, which is the effect we get by not + * listing them at all. + */ +static const ARMCPRegInfo minimal_ras_reginfo[] =3D { + { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.disr= _el1), + .readfn =3D disr_read, .writefn =3D disr_write, .raw_writefn =3D raw= _write }, + { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_terr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, +}; + /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should @@ -8217,6 +8298,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_ssbs, cpu)) { define_one_arm_cp_reg(cpu, &ssbs_reginfo); } + if (cpu_isar_feature(any_ras, cpu)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo); + } =20 if (cpu_isar_feature(aa64_vh, cpu) || cpu_isar_feature(aa64_debugv8p2, cpu)) { --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861342; cv=none; d=zohomail.com; s=zohoarc; b=azRejS2h3Pf5rfPrCr09jM6M8zc2hBElZsZ1BQPOyU/3gVpBTqnrT96kjHm+m7FG9/cUGdwQIfYAtnDjxu4t/q9rLd8gnWQFFD9jVwELmGBGtU+khyPdyiVsWz3ld8YAKp1E1qiCQ2Dr0D6TsRRb/947CnVzLAsz0enU/ErZVco= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861342; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=QgQ5KSLzutwoLc046w/8oKdisj0tzJaMrdZLKPhobI8=; b=mms6Tpy/zMftM1MeK+J/NpN1T0wx9XblkwoMxtYim18CLkRlovyl8dzaqhZO5/8KRkICb70x1uHs14RtqrUf+3ypkz2AtQvwCQdhj+r3w23Rgl23OV3Ch8Vl+ZwtNJlui/YakayAM3TzyDMwigpgDOmtQOHvZ/U86X3I5YlRf0I= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651861342062430.35350042873154; Fri, 6 May 2022 11:22:22 -0700 (PDT) Received: from localhost ([::1]:41082 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2ar-0008Hq-0l for importer@patchew.org; Fri, 06 May 2022 14:22:21 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IJ-0005xr-S5 for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:15 -0400 Received: from mail-oa1-x34.google.com ([2001:4860:4864:20::34]:45546) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IH-0003sN-O6 for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:11 -0400 Received: by mail-oa1-x34.google.com with SMTP id 586e51a60fabf-e93bbb54f9so7965018fac.12 for ; Fri, 06 May 2022 11:03:08 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=QgQ5KSLzutwoLc046w/8oKdisj0tzJaMrdZLKPhobI8=; b=igzE6ZVstxe+YSXa7OJlktNKrEuARDLIG7h/HIbOSjjoE+yGqX2cjxsIUmrRwC1O4b INAkI+jo45+9MqatTMSuVkIBwxbZuF/knTKElGlEq92KllSRFXEYwMSur9ZdDhvIJXzt p0gOQIdBEhh5Z/uGCiW5XXt3c41QXRHAeAj1k4/4Lzeeg4o0nfrkXebzBJsNkziMMKW/ SzT6eYswgeD81yPEg+OlurnjRQQFd+kxOYK9zg/ejsXqUVPgClamxeSMqZVqCe6mXr9c rzaQ7W4PSLwRRlEJpM4vL6EkqTaRp6SWoQ8GvILFLHOoQHDGiUGl1RpeMjUbZeTSKo1Y LmFw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=QgQ5KSLzutwoLc046w/8oKdisj0tzJaMrdZLKPhobI8=; b=Pc9CV56nzPMtJ2Gz+vXIQV1/5e5VkBoSh2rIpRB31oNt7BqCFOESaSeH6CXOaMoSNr EZA8xmRifM6I8FMqqgdF10JdtH02kPpenrPUsr4EFfIhnfdKFmBjtf5Q2AIQz8NkFo74 O0N+JekkG9/vHw6roTfUk65kMLG9GIXX48wyqUIhVHg8ddzaMph+yO62UYpCTpr6QsIe 3EzzidMAVsPfZaC+v+x6YRd45sc9BZjTFYiHkm89N+hw7ONfZeFg+a21rHB0Y3er2cNs O0oYISSzSupbVDKM00+qNuD4uuAGjgQFE4TQIgZCcPAJzXRRtH9v98w5ZThXTID82HZj s8jA== X-Gm-Message-State: AOAM530BUbHECONRh2R3tVdFRxM2FpuNWjW+0a+XJNq/zAMefF+w+2/i eqomdN4Gm/HjGONHct7Wb7F6ybp616DYYGYW X-Google-Smtp-Source: ABdhPJz8N0pZ3Qiy1D3FK4+hDTQ7Z5vkJ2J9EbY1Vs/pFwea9YvsGKSL00A46Z8eNl0jutYpTruI9w== X-Received: by 2002:a05:6870:796:b0:da:3d6a:101d with SMTP id en22-20020a056870079600b000da3d6a101dmr1863301oab.20.1651860188493; Fri, 06 May 2022 11:03:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 14/24] target/arm: Enable SCR and HCR bits for RAS Date: Fri, 6 May 2022 13:02:32 -0500 Message-Id: <20220506180242.216785-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x34.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861344145100001 Content-Type: text/plain; charset="utf-8" Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index 37c5e42bc0..b6faebf4a7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1755,6 +1755,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } valid_mask &=3D ~SCR_NET; =20 + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D SCR_TLOR; } @@ -1769,6 +1772,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |=3D HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861025; cv=none; d=zohomail.com; s=zohoarc; b=a/yXUPjTpkvFNOxupkVPgKzZdYaoXofoXFebNOSBWGviwPU09aztAS88nx0N7pcknP+8UTtePBauKqL2vudfMl/nmbUUGd2elVSGFnJ0rfyLYCzQIrZ2RoDTxrGNdf+IUKQV3TakbSIRkBu4fnfPItV4TP+NXMqNQUnUvUAVWAs= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861025; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MSyilv8jVM9t8fnclodxH6fJ9HoPV9SxyemQYeCb+qg=; b=aNARlHCxnb5RNmnlyAslHt3passG65yBcjB35XJ6H9tToxAXF+1kCkiqTic6Wnv1PbQ5zzHwk2sNILGKe7wZkSLeD8LR9C/frWA3Mz43vGUYHPdWJ5M/b9uVdo6uFCOhNYz74G5SPPwJBNTxPsSxP3qMeQfB5MKl0gZbzN+DlQ0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651861025708614.8465721819781; Fri, 6 May 2022 11:17:05 -0700 (PDT) Received: from localhost ([::1]:50902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2Vk-0003N0-CI for importer@patchew.org; Fri, 06 May 2022 14:17:04 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59938) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IN-0005zN-Ob for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:17 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]:33944) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IJ-0003us-Nv for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:14 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-ed9ac77cbbso7998333fac.1 for ; Fri, 06 May 2022 11:03:11 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=MSyilv8jVM9t8fnclodxH6fJ9HoPV9SxyemQYeCb+qg=; b=pXw8aj1BNNmsuKY+v8JrNMfR2Epjv0r3bFSE2CpGmWxqct4k5hYZAUB+GO2UlRe/Yd e14WeY6QaIQnaAP2ly3N6mEO9UqhR+C8oWmLvLa9naK2Qkz50xXXGsyET/U9PsxMPgoy 0isqVeNR8IhKWjPWWLWSBOCxofVDdHwRy/7zpX9iEBFrf92miKVdUe6sX1UW/qLoGqJw agGcE8Jwg6RhNper30H0K7Ih1vSDcCkF+iY/RAwo4O3/vMSyQeyJMz/4zgn7Yuk0TL9T OiAO1bdnbJenprUjartQnCgYfdWqPQNI8ynjMO0nqYfV3sYSzzL9oSHM7Oix110CUHFB GMyA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=MSyilv8jVM9t8fnclodxH6fJ9HoPV9SxyemQYeCb+qg=; b=EDTiEgUintzH9h4qGDIfkUO2iQmnCTeUH5nSosXcby9TvvJ2IhLNiqNWhgWnJBT4ag 6bXfOfE3qddofOvxxL28uUkTcf3VY/58Pf04F+43Gb7zHX3XZMtcXQf0Csfv93vZJiNp fbjL1pwp9XjyoJOLqJHqrYEWu8POuauaMOjxvB3mDtL+9I+E3Gt9G9fdtCdv1mOMT2ko lo2nhGBKjcJhWe4eG2cjFAeCGEbbFKhZ8y492qKiMirKgdzw+ng0gbjuqhMn6C0YJUlK JwZirKfxZCj57SXGvyr3MLWTXZsIIoL0GyTlb3MI5KXks/oLflU5jdBxY+ahQQKBCPUb HyFg== X-Gm-Message-State: AOAM532c5hH89yKjAGGxvk7N6Dyj9spa12kbJV5wT0GSHu/iOd44tcWT OKp1JR5dAKA7eahOKe6KNshd2WJImtVIibQ2 X-Google-Smtp-Source: ABdhPJwsMJMRznkT5kElUbfHwkfiX/TfOiqOEXjzP6GZxPSqmUa+MCE61vbisvOsvvRKtvrth6kKxA== X-Received: by 2002:a05:6870:a10d:b0:ed:971c:7ca4 with SMTP id m13-20020a056870a10d00b000ed971c7ca4mr4919386oae.166.1651860190649; Fri, 06 May 2022 11:03:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 15/24] target/arm: Implement virtual SError exceptions Date: Fri, 6 May 2022 13:02:33 -0500 Message-Id: <20220506180242.216785-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861026673100001 Content-Type: text/plain; charset="utf-8" Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Honor EAE for reporting VSERR to aa32. --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/syndrome.h | 5 +++++ target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 91 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a55980d66d..aade9237bd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -56,6 +56,7 @@ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ +#define EXCP_VSERR 24 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -89,6 +90,7 @@ enum { #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index c563b3735f..6ca0e95746 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -947,6 +947,14 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit + * + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, + * following a change to the HCR_EL2.VSE bit. + */ +void arm_cpu_update_vserr(ARMCPU *cpu); + /** * arm_mmu_idx_el: * @env: The cpu environment diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8cde8e7243..0cb26dde7d 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -287,4 +287,9 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_serror(uint32_t extra) +{ + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2667aaf28b..652a84cf84 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -85,7 +85,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } =20 @@ -511,6 +511,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, uns= igned int excp_idx, return false; } return !(env->daif & PSTATE_I); + case EXCP_VSERR: + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_A); default: g_assert_not_reached(); } @@ -632,6 +638,17 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) goto found; } } + if (interrupt_request & CPU_INTERRUPT_VSERR) { + excp_idx =3D EXCP_VSERR; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + /* Taking a virtual abort clears HCR_EL2.VSE */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + goto found; + } + } return false; =20 found: @@ -684,6 +701,25 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vserr(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index b6faebf4a7..4857d2dbb8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1863,7 +1863,12 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) } } =20 - /* External aborts are not possible in QEMU so A bit is always clear */ + if (hcr_el2 & HCR_AMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + ret |=3D CPSR_A; + } + } + return ret; } =20 @@ -5175,6 +5180,7 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) g_assert(qemu_mutex_iothread_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); + arm_cpu_update_vserr(cpu); } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9331,6 +9337,7 @@ void arm_log_exception(CPUState *cs) [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] =3D "Virtual SERR", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -9843,6 +9850,31 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) mask =3D CPSR_A | CPSR_I | CPSR_F; offset =3D 4; break; + case EXCP_VSERR: + { + /* + * Note that this is reported as a data abort, but the DFAR + * has an UNKNOWN value. Construct the SError syndrome from + * AET and ExT fields. + */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal, }; + + if (extended_addresses_enabled(env)) { + env->exception.fsr =3D arm_fi_to_lfsc(&fi); + } else { + env->exception.fsr =3D arm_fi_to_sfsc(&fi); + } + env->exception.fsr |=3D env->cp15.vsesr_el2 & 0xd000; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", + env->exception.fsr); + + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + } + break; case EXCP_SMC: new_mode =3D ARM_CPU_MODE_MON; addr =3D 0x08; @@ -10063,6 +10095,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) case EXCP_VFIQ: addr +=3D 0x100; break; + case EXCP_VSERR: + addr +=3D 0x180; + /* Construct the SError syndrome from IDS and ISS fields. */ + env->exception.syndrome =3D syn_serror(env->cp15.vsesr_el2 & 0x1ff= ffff); + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861076; cv=none; d=zohomail.com; s=zohoarc; b=GWq9QMa0abNSYAT3IfTGYCYuPrcGqwn+LWmhAuIKp/7wqPNOOnrYOui2xZeQ6NfqUWT1cVRV7JvpmRaPPdj1RLTFrLzjD1QzWkQ3kpaq54/B7FLj0FbqmifHTn8FOdIRxR0g0Onl0Awo5pgshb/IoG+VDfto9EqMsoteFMwIcm8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861076; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=abpiSeB9GnhU+yu70oxG40w5Q8oxipcU81kEqVLhpps=; b=N2luhPnoPCDbrTIxaHqsn5iTtFKLzNXzLOS8u9qJyggObwDSJB9g7/+Y3+uR/UY6U2msmh3ajT79K9BWZvlKE2tioPmUM0L6GoI7a0IlrMfCisefxw7Bxpu7ncC3uhU2wX05HHZ3iUlcLemE9kbWE+ho/GXagI8CcAoEliRuK98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651861076111517.1837824424493; Fri, 6 May 2022 11:17:56 -0700 (PDT) Received: from localhost ([::1]:54124 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2WZ-0005nK-01 for importer@patchew.org; Fri, 06 May 2022 14:17:55 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:59984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IQ-00060o-2T for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:19 -0400 Received: from mail-ot1-x32a.google.com ([2607:f8b0:4864:20::32a]:43692) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IL-0003rO-OR for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:16 -0400 Received: by mail-ot1-x32a.google.com with SMTP id m6-20020a05683023a600b0060612720715so5406568ots.10 for ; Fri, 06 May 2022 11:03:12 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=abpiSeB9GnhU+yu70oxG40w5Q8oxipcU81kEqVLhpps=; b=OYr3X7Odbaq60iM17/bQ5kRpIs27qSPFnKXbZ/+Ee8Hkdw8THdw9HgbziuEIhN6hce 9vp+Kh7txofeQVMDksbnh+LL5+dPlprKgQeV7SB+HqVTmbGT/xUVa2IagPPZ3oKumTa7 xR9uzvLUYqO10TFLINMrxJh6Txnjbm4PSa53jIKCAfggjWl2aEJH/Yd1wq/P6820ojNa KnBVrLL7PQUGVyjnCNKZGwVbUqaam10YfogBvntNmN1hRLOIi9QEf73YTNQNWV45lJxw TizYni/R4ogGYAIEeHAmC0IQ0g8XfDO2f6I4s9DeFTa2GSKUUZZxky9pc3a3J9tUFxb5 rnWw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=abpiSeB9GnhU+yu70oxG40w5Q8oxipcU81kEqVLhpps=; b=NSuWWpGwSTYMZAvs/XIhduSteLa09wC5vVCGob5ag30jph/5xwdoPbNltpEYOeAbm2 2cSDZ9U/2FHdXtNBugXgGAgBvLDued64e7HDP4VGK/1wL8r85CJ1C1u8cgyjpyTfeuk+ TvAiMbWnuMunfqlE6n9miMWNIMAh/WcBukWoOAowA4R6S9jpo0rYatu8ivA9pH55H5IC u1EgPKsWxVZqlARdQjo9+LyyXFFyBWJg1YGNRzrmuHaQsxddMxH+tTHXmzJ8MWRY4sjk O5Ulwv5szgl8KlnlOcwXZR5Bp/+0x2NBG7oHvTmvFKlmDcBTPXTlp/ZI8XUYmtrFVIAb XGkg== X-Gm-Message-State: AOAM533nBEC2hKoIzxjty4A2vXPlZBMbG7hNWODOXF+tsLlcAZFs7RW/ iyxxU/Uqaad15D3SZELVpUD0TGSRnyXlIcrK X-Google-Smtp-Source: ABdhPJwLgQqFW6vQgr96ghZ6JKYLqoxcEJOo6A7hNMydgKBe53YCQTZP74KdN4XOLXkBEsxElVHgpQ== X-Received: by 2002:a9d:6545:0:b0:5cd:b111:86fb with SMTP id q5-20020a9d6545000000b005cdb11186fbmr1449234otl.342.1651860192414; Fri, 06 May 2022 11:03:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 16/24] target/arm: Implement ESB instruction Date: Fri, 6 May 2022 13:02:34 -0500 Message-Id: <20220506180242.216785-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::32a; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x32a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861076987100001 Content-Type: text/plain; charset="utf-8" Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Retain m-profile check; improve comments. --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 ++++++++------ target/arm/t32.decode | 18 ++++++++-------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 17 +++++++++++++++ target/arm/translate.c | 23 ++++++++++++++++++++ 6 files changed, 103 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343b..b1334e0c42 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d..f2ca480949 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d6..f21ad0167a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 76499ffa14..390b6578a8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -960,3 +960,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +/* + * This function corresponds to AArch64.vESBOperation(). + * Note that the AArch32 version is not functionally different. + */ +void HELPER(vesb)(CPUARMState *env) +{ + /* + * The EL2Enabled() check is done inside arm_hcr_el2_eff, + * and will return HCR_EL2.VSE =3D=3D 0, so nothing happens. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b80313670f..5a02e076b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1454,6 +1454,23 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index 4e19191ed5..87a899d638 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6239,6 +6239,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* + * For M-profile, minimal-RAS ESB can be a NOP. + * Without RAS, we must implement this as NOP. + */ + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s))= { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch32.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861136; cv=none; d=zohomail.com; s=zohoarc; b=fu4tqpQZ8bvKp0NPa5oeAHqPg63+H623GXFJ7/E1rNGjFoEw6rEnv3x1GQjdnXRIw3kBZ0da4/zUl0op4pFsL2RDmhaQihSMy59LOo39gfw7XEjQYA20akpqfD1orAxEWV1TxTGqcYxkczSaXB2WfEXc4QgEWVGUbMhvA352I6g= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::331; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861137073100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0acac6347c..8110408000 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -42,6 +42,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_SB (Speculation Barrier) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 88d3cef93e..35881c74b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -744,6 +744,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 337598e949..c5cf7efe95 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -69,6 +69,7 @@ void aa32_max_features(ARMCPU *cpu) =20 t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:14 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GY2odDA192T0ClkUF75+bPEfdCFgpsNoLihYttz/3zY=; b=cvFabjusyDYtYvLDBIguxD4+mL6yFsulBytm0WpGIPvS4/opCcsgQGv+XyhkdrtFtf DAJMJGmF5qxWb/U7etAXdT+vckIy0GmnkD0rW5wzAjnsgiYDoagPZYFZ1IWNQ57EaWwp F7QowXRqrYT+TIph9KeyZPU15qK/fXgdP0mNI/IEQox6+nN7779Qrj07xMIKZjGG5/9H v5mmg4GPyBcH6CfjIuiG21Sg+f9S/yeYIbBnLsqcGpGA9h5rzfEqAVClKy4Szw0K4Hag 2iqmAvMY3n058oS2gjlJs+oeIfeiy15+Y18PjtaJAyeIfWHPbMTcT78QsvFzyWaBsXaB nqiA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GY2odDA192T0ClkUF75+bPEfdCFgpsNoLihYttz/3zY=; b=PFC0U1ssao3UbVTVJnWI5eTdvxH5U1DqywRXbg7fB7KLkVNRQN3nrSYuO542CyCruo eCggGQnUFBTrKErpEVN3XkKONKFKn8mdWHR7UE0RVooQt1CoFSduW/C4IKbbM/Fgatlx yCXQdGAMRGRSnHMCE5HhhmdUTLYzSUfYs+K9953D0YTbgDJe4iRJY+LfEwu3wPI6ddrU 37iwfcD7cZ9WrU/2taJGrWGRFd5poi02LOVUAkEHYdIOCk6SICkF2lDjDNon62NQN8Fc sgWBvjSuCHyJRpYJgA8PwhrD1muVZiaLwejW2oIB7FenyL0IBiB6+FSM7xI/JElvI5XF j7Pw== X-Gm-Message-State: AOAM5329az20xwGeE6eKEAbsrEDHtIRvBMimA1briJbegj2gHdeCiK0C nlWwnTVyqHoiWo85m4s//TNCOw5jsRZs2tDW X-Google-Smtp-Source: ABdhPJxvX8XsVsDLKL9IgB4DAwrwCPfXOqcvjgdu79yVbaZMIvtmJ0KLzAnw5dPwrmSfvMItLDiQPg== X-Received: by 2002:a05:6830:4420:b0:606:64a6:1deb with SMTP id q32-20020a056830442000b0060664a61debmr1095139otv.236.1651860195231; Fri, 06 May 2022 11:03:15 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 18/24] target/arm: Enable FEAT_IESB for -cpu max Date: Fri, 6 May 2022 13:02:36 -0500 Message-Id: <20220506180242.216785-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861096882100001 Content-Type: text/plain; charset="utf-8" This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8110408000..b200012d89 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -25,6 +25,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 35881c74b2..10410619f9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861327; cv=none; d=zohomail.com; s=zohoarc; b=KSM3TAym9EPi6CR74VeYWJbEXqfNUYLnmGqxRF7+fccYlQZiQehBo+BtbiGTLJHh59G9S3/cJem9TwmAP9xTIz5U7ceV8KFs/wCeFRblIgkge5PfQ5PZoUHdUthlMCkhU355DDcuUhNULsc3L+T7/fQyu9FO1uI9okqeIezVEVc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861327; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=YgPJJBWxd6UwNbu8I9UhpjXUvb+eh/ewRL4C5SYoXZc=; b=kpFoEfmrIbYMN3cRiLz8RYIu5jzeNepD2LAvXPWQBCFsgiVkYbQrizXNUM2DUX6W+87P8HwCfkbijYPbPUClP0L2y0oZ5RvOWgbuVY7DKyfCfm4DOujR3ebtgo21E2R/rGS/b+ABbYiWGpYnVjo3S8rkSPVYmu7pC7GYO0flkWw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165186132711056.08315080975842; Fri, 6 May 2022 11:22:07 -0700 (PDT) Received: from localhost ([::1]:39796 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2ac-0007Pi-0Y for importer@patchew.org; Fri, 06 May 2022 14:22:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IT-00062i-SZ for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:23 -0400 Received: from mail-oi1-x229.google.com ([2607:f8b0:4864:20::229]:38700) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IR-0003wF-IB for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:21 -0400 Received: by mail-oi1-x229.google.com with SMTP id r185so3472827oih.5 for ; Fri, 06 May 2022 11:03:18 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:16 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YgPJJBWxd6UwNbu8I9UhpjXUvb+eh/ewRL4C5SYoXZc=; b=WSobL0sMyT0KRvtk81VICiJ55j7byygjWb0YuNKo6+3ZeAIHZgBJGD+vtK2aRILFVF Enwa8Jl2JMU/mZTbbZR1vwERz3HKhq1U7qa3w1vAYXTq6XHh246GAngBh6HhJLiRqIXQ 9QDW0rc4NKh69IYbrSfEjxtwEUzm4+3OZysDAakq7zBdeKOleE5GJcrcyChTIK6AjCRu RAS1MAhwqTuiWPh8F9AMSHfNCrfbkh61CXUvZlgBx18bRwYrRmk3ch3sePTFwizMcNNg 6XsWV01C9twC/Sl31VOgMTWJ120Ysfd3e83bewHYb2z6MQ57NGc/9zMqjfl6OCnkzxRx +1Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YgPJJBWxd6UwNbu8I9UhpjXUvb+eh/ewRL4C5SYoXZc=; b=plEa1kYRD9ARln42Y4Sgws/JaeA1EuTtmv6L1/mDvP1rGQf7P5MdejrG5EJSkCe2yZ QKX2dNElY87Z7QVqE9jYVAm+dXcPklHNsNi+0KhIwhEKjvUrsLGqXpDyHCiCesvcqBqc DwgfUa+Jlnxf2VhwsDjiQmMA3OVz+e0gbqqU1D67KRPae3JO0dVBjMcI4OvVkVT5Gg+Y mWZ7JXxnT+aTF1fz7ii6fcRuFwaQhsSH0ndoiNChCLuXTwH2Pv1RGk+E6f42+CSgkqVC DWhI0I1t06JpJvPAniE8XpofGWZouialjJ0Rd+9qUwtBPE1R0BWKR6z8/9fcHjO6zHyi 3MDA== X-Gm-Message-State: AOAM530YMyiJIy5qMuWfZFKYb4SqcpqMAIfuyFqmny0IYKEYUjcq3tU+ 71zrkLDXu2lH2P5ClX7m1BoLdo7uikZpbRFD X-Google-Smtp-Source: ABdhPJxWp9+0kpCYTqM5a1wMcLX6wzRa7vYHMLhh26KJHMeNaF2NJx+uh/WpYwFkn0KKS9mdX5vn+g== X-Received: by 2002:a05:6808:2095:b0:325:7ad8:6d18 with SMTP id s21-20020a056808209500b003257ad86d18mr5560151oiw.58.1651860197336; Fri, 06 May 2022 11:03:17 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 19/24] target/arm: Enable FEAT_CSV2 for -cpu max Date: Fri, 6 May 2022 13:02:37 -0500 Message-Id: <20220506180242.216785-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861328225100001 Content-Type: text/plain; charset="utf-8" This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b200012d89..b2a3e2a437 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -12,6 +12,7 @@ the following architecture extensions: - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CSV2 (Cache speculation variant 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 10410619f9..25fe74f928 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c5cf7efe95..762b961707 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -68,6 +68,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861259; cv=none; d=zohomail.com; s=zohoarc; b=EmMlrpJRvweGmoC27vQhBcJ1IKvnaFCHCvXBoTul+lO7MT5PVwxK3pCb7ur5wzsjFnGKD1tlg2Q/kCDcMvUuyTPnEcaALoWNht1Lm/WAEZEQoiI/L1vR4uKbX337cVDY5Q/xobe9oS/Wv3pYmENds+W1iI92z49YZVd8X+3u81k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861259; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CWNgNfzUCSh/G2d5uhrXTyqZyH2sX5sogtnqRYbuI1s=; b=TKJw+Pel6SYTLHsKFELRFJUGOV8xH+lrtUzTmOCxi712raryr8zRqUgh9b9WPrzRKY3XnKUdGnUuZYsj4STCOV6C+T6SXTUi8ywXEeBQavWZq3NV/dOhUIdRT+RZrVBR2hAjPQRwegYpmqVbr2uVfP8BlbdyE4ktPMfB3MvteeE= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651861259557575.1264172427765; Fri, 6 May 2022 11:20:59 -0700 (PDT) Received: from localhost ([::1]:35490 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2ZW-0004Sn-D0 for importer@patchew.org; Fri, 06 May 2022 14:20:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60166) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IW-00063x-3S for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:24 -0400 Received: from mail-oi1-x22d.google.com ([2607:f8b0:4864:20::22d]:46604) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IT-0003ty-JZ for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:23 -0400 Received: by mail-oi1-x22d.google.com with SMTP id q8so8277255oif.13 for ; Fri, 06 May 2022 11:03:19 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:18 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CWNgNfzUCSh/G2d5uhrXTyqZyH2sX5sogtnqRYbuI1s=; b=FRuz+JbgpPsLrYgiUxEgipO9c0Y6osor3Ociv3saDj5daaAEqV3RPqSHn3XyNwEEaV APDovkEXfnI/hL15/8GBF9l0I8qZB68TTl7BcWE9EvCNt+w/cQNHt36J3nDjZBLf7mdJ b4vJQtCM0eyPAwNCBcMOdGONxsw57wiJVxcZn5fZLHyU40W5/Ek/2PbamKOy5FsIgFfb VEnsoOmhwAKh06A/0MDNp4/HKmtC/rryLIfF6VzJdKa9Va2O+9LgiWJqZMajeps3gaD+ UHR6NXehc6A1NzKOPiP6rswBhAORGg9cSCt3hMPKPkD1MyBAD6UO+4o0E3bqK4Lor6dv 20WA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CWNgNfzUCSh/G2d5uhrXTyqZyH2sX5sogtnqRYbuI1s=; b=VzBqhQjTeUX2hb6Z8+JfZaIYzzHgMPUcYA8VwyULDZfaomsU8YqrnFEShXwWGvEx/q dXgN8TdrrjW/LQYotT3yaoLID/tEHqdoVI/XDLvNPSIjEAtRx6DaleMWbLsyBF2UxJH7 g2us4Yrm3LPlaGKD40H4AuNubTkt6qU2qZrzebrfPTmJylhG+ubqOh1P3xAu8T2yAko5 eVzxleVyefQ14mCUf4SOqYmuCa8IhT2sv6ZuOMGR30EkY8g4OgqBeca1EBrrrIZmdORY 4hZIMKuUoWwptmA0kPTkwNcikZWy/g90LMkyTIbg4XMhtYFSQBylM7Y8hhooNeW3xQIG ZM+A== X-Gm-Message-State: AOAM532iEH/02aJ+WRcbJfq6Iojc+gjRPeJiJFDy+utgtz8WsxWhpvpM lYxVYyEwmxIG6owrBVNNAtNbvoPSsvJUGXch X-Google-Smtp-Source: ABdhPJwhCNcjmZW87CPHfoHNd3xetgSJ4Nwb9wBUx8s0yc/Fm3mSdny6WxKc1B/52jjyhBaH4sRJ4Q== X-Received: by 2002:a05:6808:238a:b0:326:955e:f21 with SMTP id bp10-20020a056808238a00b00326955e0f21mr1531913oib.118.1651860198713; Fri, 06 May 2022 11:03:18 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 20/24] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Fri, 6 May 2022 13:02:38 -0500 Message-Id: <20220506180242.216785-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22d; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861261694100001 Content-Type: text/plain; charset="utf-8" There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum. v3: Rely on EL3-no-EL2 squashing during registration. v5: Set SCTLR_EL1.TSCXT at user-only startup. --- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 16 +++++++++ target/arm/cpu.c | 5 +++ target/arm/cpu64.c | 3 +- target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- 5 files changed, 86 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b2a3e2a437..9765ee3eaf 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -13,6 +13,9 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CSV2 (Cache speculation variant 2) +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aade9237bd..18ca61e8e2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -688,6 +688,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif =20 #if defined(CONFIG_USER_ONLY) @@ -1211,6 +1213,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4022,6 +4025,19 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >=3D 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key =3D=3D 1) { + key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >=3D 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 652a84cf84..59df597e05 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -230,6 +230,11 @@ static void arm_cpu_reset(DeviceState *dev) */ env->cp15.gcr_el1 =3D 0x1ffff; } + /* + * Disable access to SCXTNUM_EL0 from CSV2_1p2. + * This is not yet exposed from the Linux kernel in any way. + */ + env->cp15.sctlr_el[1] |=3D SCTLR_TSCXT; #else /* Reset into the highest available EL */ if (arm_feature(env, ARM_FEATURE_EL3)) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 25fe74f928..07b44a62be 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 4857d2dbb8..432bd81919 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1770,6 +1770,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D SCR_ENSCXT; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5149,6 +5152,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D HCR_ENSCXT; + } } =20 /* Clear RES0 bits. */ @@ -5800,6 +5806,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, =20 + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7223,7 +7233,52 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { }, }; =20 -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + uint64_t hcr =3D arm_hcr_el2_eff(env); + int el =3D arm_current_el(env); + + if (el =3D=3D 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] =3D { + { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, + { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, + { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL2_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[2]) }, + { .name =3D "SCXTNUM_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, +}; +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -8365,6 +8420,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.34.1 From nobody Thu May 9 11:31:17 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861281; cv=none; d=zohomail.com; s=zohoarc; b=cGQaj8r5TXDOVQPuJCtGtkNyjcAlRaIRiY/y8c1NfFURSbD5IYhUar/7Vyf1hLLwV/9sTkAhs1OExJLBb0AkuQ8X++yPFaO6qOSIPHPWeNKYaeGm3egmYgf1yJSiZtAcqRTsPuv5HpzzUOWettK8BiCznaH55Fy1io0VklzrjeQ= ARC-Message-Signature: i=1; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:19 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=43XuEEQaBW24fA/OpN/C0G+r/QXfL2oSSQvbYI2NnFc=; b=DDx14ellYOvEHSv1oirlyqCOE+oJ6npKUMD3D3hB4HJrM7dNBy93iuOxMW1gaXLQlO a5m4g9k2msCY3zKvN3MAjH44vUdM0OjU/lrwe3JHn6+dMKfp4rYPaEOvAfNJqI0Mc4v6 hScR5ITkFz1o8pjvQyb+NnP80w9CmlhokSJs86O1HiIV/bEcyADzM2LTgLQCFQgYhiVy 1x0HrnhnW9Ubb6zIB0LZ9r6ZQtI1vNKzPa6pl0/53aNY1pYSWbrB/nx36hYtMd45mbrx 27xOBHpC2BBW9NZjomH2RrEm0UJU/2/L9GdeyansBVsv9+HeXBCN5crtyBMUfJf4HHEf Q+NA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=43XuEEQaBW24fA/OpN/C0G+r/QXfL2oSSQvbYI2NnFc=; b=5Ns69ZKg/3oMm0MqrF0kjscVztOGWbnNtBsLPn8XOgFQ0W8J7NzBS25L62OJC5/eEj 0uFGz6qmcR1rAEEdHyP3FbuFRxDT5jkO8eAK3UPTNd2voqYFQLFucVCE9tFRFeKqmM7k yHiCYJ4b/AX46A3Gzb84AyAgPg9CJM/En+Tr/PG9Hee2mQcI6Ym4Se+YdC4XQuCofrTY /VZa5DXIFYwTZZaPwYgjNH+H/TtZLiBQdYmBUGKsuq4eo1JYtZ0jJ2Kd4TwphjzeD9Nm Tg3TlJbg8XvuK4m99prmjevReK6whcI0NbTncoj4qHumxpS2WqDeYwIJwNEz3aEPIPi5 gx6A== X-Gm-Message-State: AOAM533S2h3D7UlaztrWhvrTr9HP26W5bRZfBO/IVhYFRDuMYhOOHW+v PZrYJ2X6odDmvui/bmbMgN+Z9MTuacRCN3HD X-Google-Smtp-Source: ABdhPJxYipEW3J2Iw/i+UcwQCBodpd8I8W0mcZwiUE3mGg0MkDnm8cpIf7ETiAv3BAHShqR9SqoJDQ== X-Received: by 2002:aca:3788:0:b0:326:89e4:6ecf with SMTP id e130-20020aca3788000000b0032689e46ecfmr2580220oia.74.1651860200173; Fri, 06 May 2022 11:03:20 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 21/24] target/arm: Enable FEAT_CSV3 for -cpu max Date: Fri, 6 May 2022 13:02:39 -0500 Message-Id: <20220506180242.216785-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::229; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861281752100001 Content-Type: text/plain; charset="utf-8" This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 9765ee3eaf..48522b8e1c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -16,6 +16,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV3 (Cache speculation variant 3) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 07b44a62be..40f77defb5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -749,6 +749,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 762b961707..ea4eccddc3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -74,6 +74,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 --=20 2.34.1 From nobody Thu May 9 11:31:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861619; cv=none; d=zohomail.com; s=zohoarc; b=IAl7ukydyagZywFaPrVWdtHeiA7/CK2L98OXhirNg2/0qYQ7LStG07VYEQygm17/dec+kg0ePwFmzyUVDEeZ7uVrWEDBgcxfpe4CHRQAdAPlG36wqEOhHrdar5bvltuPd02NWqNi8k1Rmdhg4Skbzjl4uBXVrfKR8Ccx5jQmZOU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861619; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ffCp2E5F/+S85cFm2jKC10BX2N+sZzcIlrVCqyHFbrg=; b=iro72lFCX8UiRteGVzw54AVUeNfWoyno7zvC4+NmWpgUysQ5t+nKE5UvIVAEyss05bTTM4xrpB67Ti5RYj3XBe47pIIIkFK8yVVuR6/OTi0ym5oxiWj51H/cScDP2YCAuxf2/F8qzpPUGJXKoOqdmb5EHLncsixCQm0cBOK7Pkc= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651861619393994.7306109092611; Fri, 6 May 2022 11:26:59 -0700 (PDT) Received: from localhost ([::1]:52924 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2fK-000850-4d for importer@patchew.org; Fri, 06 May 2022 14:26:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60212) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IX-00069P-FW for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:25 -0400 Received: from mail-oa1-x30.google.com ([2001:4860:4864:20::30]:37095) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IU-0003sM-BJ for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:25 -0400 Received: by mail-oa1-x30.google.com with SMTP id 586e51a60fabf-ed8a3962f8so7984224fac.4 for ; Fri, 06 May 2022 11:03:21 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:21 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffCp2E5F/+S85cFm2jKC10BX2N+sZzcIlrVCqyHFbrg=; b=lkC6u9JmRmRhufAqL9fOvsaTmRzCYHXRHJ2J6OinN+iTNAklnfQp4ADrfCu83QdxxP HD/SA/puFPFeqZuU/uyAXJuA5kpaazM+WZdqQGkq9zO/lm9PfM0VFWHoWNjUsxBaBzQ8 7daejCVgZwUXCtq2gplPBDowkA4y5ByXqYOFz2W+WIi6+m6WmVd8Q2DebJJIYb5W57eG fYu/LgRnnP+NpQuy8B3hrTMR0+VGOwmPTXL7hXZNfPhRx9ty5oEO6XkSuvLOjag2Rf0X GOVkqLh+Z5OUmct3urBNJrp5ImXMNVNQir4wGfBFDBnSitGkgQ5lv7NxqVkiP2fdy8kM 1cSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffCp2E5F/+S85cFm2jKC10BX2N+sZzcIlrVCqyHFbrg=; b=dHaHNtwswdRb0ULnMmPxRkMn4zzSegUDIoMthCJp0koq6Nfkm+2/94Brxh+a1Zz8ao JaKwi/r3PiBQS2CF4pPNm4MQ3o2rqgQGAxxtwmXsOlH5F59zmdl2wX52NeRkxP3m/Jol bxVBJ20xIxI/Ye3whx+kLAtrMM19WhOhtBYgRq71f1xaqyRPO9h3s0PKaheMvPlJ7yN9 8muCXO03Z0kuuJff8sxK1sUCWtKcKR7RXr5P6y6/CTDjV+foeN/KJv6aVnb/Ru7eawks 3bD7vAus4PUuAxOUv3zDCvjptFUEkjq9QZRuDGUL6Qp79MYdtgY7NvJCsDCOvm3O4Eoe jo6w== X-Gm-Message-State: AOAM533bsEviOPpTz7nwVaqCuXPSUdf/BA4CDXT/bTYM1GypafRuhUzk NyluwP4fwMtNyvYht23hrixT7odTKD/j8JM+ X-Google-Smtp-Source: ABdhPJw/WhEnRy2g8O06Ze+Don6hAdJ6EMXA7afv3L6LouVCHALAMJw93b/JFbBkXxBddl7Pa2p/Gw== X-Received: by 2002:a05:6870:961c:b0:df:27ec:ed7f with SMTP id d28-20020a056870961c00b000df27eced7fmr1849133oaq.275.1651860201704; Fri, 06 May 2022 11:03:21 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 22/24] target/arm: Enable FEAT_DGH for -cpu max Date: Fri, 6 May 2022 13:02:40 -0500 Message-Id: <20220506180242.216785-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::30; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x30.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861621293100003 Content-Type: text/plain; charset="utf-8" This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 48522b8e1c..8ed466bf68 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -17,6 +17,7 @@ the following architecture extensions: - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_CSV3 (Cache speculation variant 3) +- FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 40f77defb5..f55121060d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a02e076b7..6a27234a5c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ --=20 2.34.1 From nobody Thu May 9 11:31:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651861433; cv=none; d=zohomail.com; s=zohoarc; b=H5x8PmGzO2muGtr9pZpQJyKvD0qU3aFn9RBDMVy1qpCqFd3bk7BjaALgyMWJ2ebzqADoPEQnyMYbO+vX0FOiHj3sC1GM8WxhB6G19CBH4xcW3tV2sDtQbwqwGXd4ecabiVyGjSoVKj5zh2vsh9Tm6wG71/KwAWQM9dz++PIMkHg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651861433; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=vEHioUTW07RbxrApJKm//wt4N/0RvoNJcCdNTfvqqX8=; b=feR5WXkBHqzrPHJ5JGnTJ/j/ADE7y91qn/I3GakeAhW9kAnhV2D7lC1UEcLfWodVyat5JJM4DJcgOKJ6b2NW5E2vMO+H4U4NxLhuLw1FVsd6rDzWNaWo5dLcR60u/omPsOJsenRxS/rNEf7r4tbopmEn9JPupgs0eHn3FOsZ7Ps= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165186143383668.51391150837185; Fri, 6 May 2022 11:23:53 -0700 (PDT) Received: from localhost ([::1]:45540 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn2cK-0002vi-HH for importer@patchew.org; Fri, 06 May 2022 14:23:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60238) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn2IY-0006BD-3I for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:26 -0400 Received: from mail-oa1-x2d.google.com ([2001:4860:4864:20::2d]:35213) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn2IV-0003st-St for qemu-devel@nongnu.org; Fri, 06 May 2022 14:03:25 -0400 Received: by mail-oa1-x2d.google.com with SMTP id 586e51a60fabf-e2fa360f6dso7989713fac.2 for ; Fri, 06 May 2022 11:03:23 -0700 (PDT) Received: from stoup.. ([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vEHioUTW07RbxrApJKm//wt4N/0RvoNJcCdNTfvqqX8=; b=PiWSewlYoqI+CnMLmCNqnktQIJ672IbZ4DVg68qjOyUmVnsJUmrVTnqfauoLWuK04u O9vbKBeSLuSAPFNh4zApThjJPUp+uqKN4HVpv/udPwFb5cKSc6KV0Pn+8Dpb+aa6Yo9N AZBMjt3HVFGbziniEh0tMvm6LMgrz4B7Ks33WcuzMmysNU05C8eiUd1yXzyzFWR/26/a Z7dG1aVdF5uIi+yoOJUuN9UsKfGjpiLfuH3kokbzgIDGlEG+CLRnsRojF1dXFuVN37Mh Bj2SxD+K3rsd84vIgH8NgNg6nPzN7BnlbhAI5fbzbmSqxva1hu/BdvBeOgXrvAAB37EQ 5rCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vEHioUTW07RbxrApJKm//wt4N/0RvoNJcCdNTfvqqX8=; b=s3xg0HH2+kCgXg544C0WCu8EHwEf6qQROToEkAcN//H5Zr81NKAqj7tvbBgj77w/mF E+9GB/YnAWJ1oqTxrTQiPGa0cCyMhnZ/zCAo5NeoDNM1cWRDV/KMWqeu/nxyrQBLt9Mf fWtYwoTq3Ko7lZ2tkHbY6L+JEUuPlOtQgXwLNEBBc79VUwCfFR3n6IzEJ/7DkOFbdr4T BArAx8ZndTPUs9DzkBviV83WhH1G50iOrz44Bup32uMOcow/m8l512P5pxW0OwC9MV9w 1iSKNAr1hY9QO1AHATnvxfJ7jNS+H571Ad4xER0xnKnndDGutQJI6BF+JyfofrBG63QR NVlQ== X-Gm-Message-State: AOAM530GpBIZQOxDFTR2Org9vFRjXszDPO4JjtHd1jpbRn8foaDuaWWA 5dY+OyzXcwxTYITm0i+mEUCEKu/PQ6Kt5PdQ X-Google-Smtp-Source: ABdhPJxGa3NepBHSejcHurEe53Zwvmkmgu0yVvVnktyT4JGYnffMYuUMBtqLJ5PjvNaYp7XvzJu+bA== X-Received: by 2002:a05:6870:45a4:b0:dd:b08e:fa49 with SMTP id y36-20020a05687045a400b000ddb08efa49mr1970286oao.270.1651860203202; Fri, 06 May 2022 11:03:23 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 23/24] target/arm: Define cortex-a76 Date: Fri, 6 May 2022 13:02:41 -0500 Message-Id: <20220506180242.216785-24-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::2d; envelope-from=richard.henderson@linaro.org; helo=mail-oa1-x2d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861434433100001 Content-Type: text/plain; charset="utf-8" Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 5fe045cbf0..3e264d85af 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2387401963..2ddde88f5e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] =3D { static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f94278935f..12bc2318ec 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -202,6 +202,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f55121060d..adfe6b26be 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -194,6 +194,71 @@ static void aarch64_a72_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -881,6 +946,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) --=20 2.34.1 From nobody Thu May 9 11:31:18 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([2607:fb90:5fe1:b497:51bb:ba21:d1a7:eac2]) by smtp.gmail.com with ESMTPSA id e4-20020a056870c0c400b000e686d1389esm1780002oad.56.2022.05.06.11.03.23 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 11:03:24 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zS8iy63zUNyzTAn358CLXJXvtW6Z0IyKqcTl9uBiuyg=; b=jGXk2LOSXxtMydGha3fsn6HDTV8xphHvC7b3ekIHlDFBYYxkvbRWXCDsWUl1KHxhgC 2mgidXrlp4MFUrExq/4EXCfgDq6JwJ4Obrr6/w5OH6gKAJf5FxRCFcEt+dAgtoe77XYx FjVGRPI+SSuOH07KulEOeQIdVf2yaww+GqrEBvBSIIJ3a+6kr+w1tRJiFYnZaQPs/Msm vgC1ONRqCluNa30Secmc+AydCwwE0ZmOPo88a2S04/ezus3c/MNDSt2hWx2F1QASO3qT lzN3n4hzmnnGDZNH3PODVUN67cN/MxSXc9fscwINQ5VqQ7bnBPkSMjMv2EiI7xYD0V85 T2mw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zS8iy63zUNyzTAn358CLXJXvtW6Z0IyKqcTl9uBiuyg=; b=qG1GPINLnxd5gJha3WKDzVBrtx0JljsvhSrTSIm55qzUqO9nftYawVS9iZnpQXUmEB O6C3TmTC9qDpOYdnqp/gljjrnAN7Weqd+vY8aa6M08M/Ht1VWe7Y0V4L0SWH/ldKOSt+ 2VbxEaosk2No330ZbiEFBCCOxUmPTEVgEQjnuRlaWZ5fXFExu0+1hWEUdWMfelMrX6g7 7GDWeVLySaK4pmg4yHbwYCne7s0XzrFtBfdHJ8y5b/NJoPu+dtjBGxzhVdZYE777QBpD uA3BJw5MJrYjbqK6CqrMPkw2kz5+OKBzzt4a/XtIRNPnNYcnuqeFtWCdoJdJUnrpUSxi 4qhQ== X-Gm-Message-State: AOAM533nN7KBBNRvyhkqayXPfnVexf5Z7k54u1OEh+4HUVLfjnZbrWq7 YanzbieQrmHe/xvqiTyFVjDFHYValls2uHlW X-Google-Smtp-Source: ABdhPJwyruyurZRhZL0wsvUF4RdVeAsPA48wwhGu2ICszGQXI1tqoBRmhqk+YTMckyY0c4aoFmngGQ== X-Received: by 2002:a05:6808:1b11:b0:326:4608:4504 with SMTP id bx17-20020a0568081b1100b0032646084504mr2066067oib.145.1651860204953; Fri, 06 May 2022 11:03:24 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v6 24/24] target/arm: Define neoverse-n1 Date: Fri, 6 May 2022 13:02:42 -0500 Message-Id: <20220506180242.216785-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220506180242.216785-1-richard.henderson@linaro.org> References: <20220506180242.216785-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22e; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651861869014100001 Content-Type: text/plain; charset="utf-8" Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 3e264d85af..3d1058a80c 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) +- ``neoverse-n1`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2ddde88f5e..dac8860f2d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,6 +146,7 @@ static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 12bc2318ec..da7e3ede56 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index adfe6b26be..04427e073f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -259,6 +259,71 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; } =20 +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -948,6 +1013,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, + { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, --=20 2.34.1