From nobody Sun May 19 10:57:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651854227; cv=none; d=zohomail.com; s=zohoarc; b=nkHCygRt+A6Af1IQ2KN62+3AfBfXa1ZxEs1hu/w8H98xJaojX7jQAcdWMnGLCbazGc2ARd6F/XRvilroKmqFuiZeYDWTGODHqIVd+JTZ0AbkHPAl3vZLUJ9omdGdWm8jXTmpQ+DzTirO0aCcuwDeNI5NdS4Dtx8VmCdfRBgKwms= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651854227; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bOxIOXkxIovtGJKfDrlFz7G6tvoSu0yK5tycQxFKtgU=; b=jE3nUjHrrFaMCBghYTL/Ij3WSeW9MGnjhgYSu0PLws61kFdtCbRlmDS2l5zWtghySB95HquVwLN6UXDB5M7SRpENuoF6GAzWcIV4SM22huerAtT12xtuaxWB0hTHtsYpXkeGKF7cBMThRhVXrLjr3hGQpANfXXQmcutu6zpBK98= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165185422789332.959923535198755; Fri, 6 May 2022 09:23:47 -0700 (PDT) Received: from localhost ([::1]:57264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn0k6-0007kI-Co for importer@patchew.org; Fri, 06 May 2022 12:23:46 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39160) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn0i0-0005NL-VW for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:37 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38837) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn0hy-000526-4i for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:36 -0400 Received: by mail-wr1-x42c.google.com with SMTP id k2so10681170wrd.5 for ; Fri, 06 May 2022 09:21:33 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j2-20020a5d4482000000b0020c5253d926sm3782082wrq.114.2022.05.06.09.21.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 09:21:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bOxIOXkxIovtGJKfDrlFz7G6tvoSu0yK5tycQxFKtgU=; b=LFJvEg7EPUuS+Imjoiisw6voPKs7IkJkmV4cPoO6Aiwi9HPYr1UiH9Yhm2rk1COJ/A rK07dAwJln5wVSyEIKsLRTKnlsSSJ/xxrFZQrdh1cmokSGFuHkrhG3vEeZ16NlOy8NQ/ H0xgGAdVqQDR7Nw4E6hm00y57zPdiPjPlkYhOJj9uof1A9bpxNNs2XSzkhedWrBS0Lix EchE+N8hrCs2a3s2WKKMYdvxl62pw8b+Htb8FeOl6gjSKf1fQWHZC9li60rd8OT+jh6f 9i81sNv7betxt+/9P9ImywfpwTkOwU08aNiqz1BzbawwmtxGhTIWyZ+Wyh5lBaItHDxI Y4Pg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bOxIOXkxIovtGJKfDrlFz7G6tvoSu0yK5tycQxFKtgU=; b=JP3gaVg3ruodNNIxuONpRxXdZM4V7EFybJ0JYMpAwkNLlNt0Nn7aYlp+KMLV5t6GXK axh3tB9zLolmydhJsz4qv/UYhszIp58uN0tICoGAgi4x/Pe+oXd+FH3IM24IF/mKEu1A RTPFx1FK1stMh7JUrfQVvjBJe3FpLU+LUHwPx5DvSYJO50wfY+QeasWJ21LGnEIfsxpS ai37iZJN68JpWlKurir+S2Jj71+2FBdfuSfgt1ZCqrDoI+qhAZtOTWJJ2YBwBWJ16qRJ 6MwdbNrPbRkg6eAGcHWlDTMbQRq+icrNitCVU2rwS3PmQnp+xeHRH4df1Wz9kHmOZihA GaWg== X-Gm-Message-State: AOAM530WEsFh7PfnycgFoU7E8muzO8O61dczgRM7dClF5AtntQONRhv9 Mil6pahjeyR+wbsaa0+wMU4QGQ== X-Google-Smtp-Source: ABdhPJxFxnbjNJSp3+7/oFRo6qr1i6zI+dp3AdwJ8VHujRyc99W7t7qmQQwW9+v5LlUyKNSjv8yh7g== X-Received: by 2002:a05:6000:707:b0:20c:4fd8:1d61 with SMTP id bs7-20020a056000070700b0020c4fd81d61mr3396746wrb.407.1651854092561; Fri, 06 May 2022 09:21:32 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/5] hw/intc/arm_gicv3: report correct PRIbits field in ICV_CTLR_EL1 Date: Fri, 6 May 2022 17:21:25 +0100 Message-Id: <20220506162129.2896966-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506162129.2896966-1-peter.maydell@linaro.org> References: <20220506162129.2896966-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651854229816100003 Content-Type: text/plain; charset="utf-8" As noted in the comment, the PRIbits field in ICV_CTLR_EL1 is supposed to match the ICH_VTR_EL2 PRIbits setting; that is, it is the virtual priority bit setting, not the physical priority bit setting. (For QEMU currently we always implement 8 bits of physical priority, so the PRIbits field was previously 7, since it is defined to be "priority bits - 1".) Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 9efba798f82..d3b92a36636 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -657,7 +657,7 @@ static uint64_t icv_ctlr_read(CPUARMState *env, const A= RMCPRegInfo *ri) * should match the ones reported in ich_vtr_read(). */ value =3D ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | - (7 << ICC_CTLR_EL1_PRIBITS_SHIFT); + ((cs->vpribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); =20 if (cs->ich_vmcr_el2 & ICH_VMCR_EL2_VEOIM) { value |=3D ICC_CTLR_EL1_EOIMODE; --=20 2.25.1 From nobody Sun May 19 10:57:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651854346; cv=none; d=zohomail.com; s=zohoarc; b=fMZtf8l4ySKj2DETQFG6IaMiEIAGdQNjegCi2m15+k43cXr/T0pDcXhc041dvNgKKwfRDLpbFePMyZggMEnEWXHBki2fQ+HORy6oFQBy5mcNnfwdmYjAVuOaWgaNycgKv5yRqMxaxT+Wd/MMY43jqiEjHcO4D2QVLvrW6ETGBWI= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651854346; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=s5hwKzJz7oHObalRn4AoZXqvpOR58c84KtTr/3Ljs14=; b=bmx1HuV7syGD1oX9ZvKGcqUYM/RTii5ZkNsetnVEG/CgGFTo8CCgFJmmWipswwJJcZY/oeSl6m1MtQPb6S0UJU+93tDIJl4j9c7u6jMhh6w17xoYXJ/rpCTfEkUhDjXpMvAfcDwPjwBto3r43RuyodWzDHj5z6TAVU0mKlx8I/Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651854345978596.8471663658293; Fri, 6 May 2022 09:25:45 -0700 (PDT) Received: from localhost ([::1]:35376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn0m1-0003VF-0W for importer@patchew.org; Fri, 06 May 2022 12:25:45 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39168) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn0i1-0005NN-3a for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:37 -0400 Received: from mail-wr1-x429.google.com ([2a00:1450:4864:20::429]:35467) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn0hy-00052r-PS for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:36 -0400 Received: by mail-wr1-x429.google.com with SMTP id j15so10713902wrb.2 for ; Fri, 06 May 2022 09:21:34 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j2-20020a5d4482000000b0020c5253d926sm3782082wrq.114.2022.05.06.09.21.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 09:21:33 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=s5hwKzJz7oHObalRn4AoZXqvpOR58c84KtTr/3Ljs14=; b=pLXF4dt1YULS2dJNp1N6sAxWyGU+7tQPTqookMr1nTArZbRuQGq6EW0AN+WYacusDS Ts1f0Sh1jRjEZ3AfGdAsgWHJb4PzEfmSTFaSW7H+VdP8SgaiQaptuLhJ/hqs4p5UqSQw UUVBnFaNlMvGMh8y5H3+bXAOhyxsertWQI7N+uJSXOuRAfIJR2CclmeBgdN86ti8vjMa 1zZYYuceJOnYKWE77jQHld+hePRci16VFE1JnHGwACjGPqpEdV5Pxl37IwZ3tlpLpl+d 3cZwfzyNAt+fosXCQsMrxOl2UUK/VpzkUuwEcpoRVA+x7JPWjDNxviS9HQKm9kQRSEBY Kykw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=s5hwKzJz7oHObalRn4AoZXqvpOR58c84KtTr/3Ljs14=; b=ufO8TZ+tN9coGagSkLt7GinvB5ExUed8wesJkd+tPa/Mpp7NeTpTiAntWCHY8P3Pz5 c6GMypj1VmqJDW0Zz2S0vtS1+1WhPlXw2qvU0hTvm50HDTIVC9gISkYiDfQdOA4y7vwK DAHdgWeVe/CYNRxDoPV+RVYytioK1IcIJ/4RbnQIzZtAvkfsmzqQiXSXnlRtg9Rk7/Gi gm+xerF+7t5lhVa3VP8Cdb6QuknU3v0N0zLGnOPChmLAJ7qxWd5Erufea5R9xD8DFJ2i zfiWie3564I2C0iTG62rbKyt1gmpI+vB/o8qq16gXXYVGrxSgra+e/Zedi1EoXTH/2SK pMqQ== X-Gm-Message-State: AOAM531oJevyWoIH3J3DV8DybiT9jn/hUKvJVoBkkF9yEpBqvvyJO2yH ljNppBjI9nI4V7H03aSdcejdlvbvgXHQ7g== X-Google-Smtp-Source: ABdhPJyhNxVDAiC6m84dnavs8hXp7Zj49R8iSAtkm0h3keczPIrG/L5rEMjNIlKZ+7AITPMr/ygl1A== X-Received: by 2002:a05:6000:1868:b0:20c:95c4:ed9a with SMTP id d8-20020a056000186800b0020c95c4ed9amr3302258wri.243.1651854093461; Fri, 06 May 2022 09:21:33 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/5] hw/intc/arm_gicv3_kvm.c: Stop using GIC_MIN_BPR constant Date: Fri, 6 May 2022 17:21:26 +0100 Message-Id: <20220506162129.2896966-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506162129.2896966-1-peter.maydell@linaro.org> References: <20220506162129.2896966-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::429; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651854346705100001 Content-Type: text/plain; charset="utf-8" The GIC_MIN_BPR constant defines the minimum BPR value that the TCG emulated GICv3 supports. We're currently using this also as the value we reset the KVM GICv3 ICC_BPR registers to, but this is only right by accident. We want to make the emulated GICv3 use a configurable number of priority bits, which means that GIC_MIN_BPR will no longer be a constant. Replace the uses in the KVM reset code with literal 0, plus a constant explaining why this is reasonable. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_kvm.c | 16 +++++++++++++--- 1 file changed, 13 insertions(+), 3 deletions(-) diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 2922c516e56..3ca643ecba4 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -673,9 +673,19 @@ static void arm_gicv3_icc_reset(CPUARMState *env, cons= t ARMCPRegInfo *ri) s =3D c->gic; =20 c->icc_pmr_el1 =3D 0; - c->icc_bpr[GICV3_G0] =3D GIC_MIN_BPR; - c->icc_bpr[GICV3_G1] =3D GIC_MIN_BPR; - c->icc_bpr[GICV3_G1NS] =3D GIC_MIN_BPR; + /* + * Architecturally the reset value of the ICC_BPR registers + * is UNKNOWN. We set them all to 0 here; when the kernel + * uses these values to program the ICH_VMCR_EL2 fields that + * determine the guest-visible ICC_BPR register values, the + * hardware's "writing a value less than the minimum sets + * the field to the minimum value" behaviour will result in + * them effectively resetting to the correct minimum value + * for the host GIC. + */ + c->icc_bpr[GICV3_G0] =3D 0; + c->icc_bpr[GICV3_G1] =3D 0; + c->icc_bpr[GICV3_G1NS] =3D 0; =20 c->icc_sre_el1 =3D 0x7; memset(c->icc_apr, 0, sizeof(c->icc_apr)); --=20 2.25.1 From nobody Sun May 19 10:57:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651854263; cv=none; d=zohomail.com; s=zohoarc; b=RsrKxlOTPrjlRVyrI0MMwiq/1/FvXv4Gl4lR48VtVHgqgylB6pK3y8KV+nbEF29tB7jvNfgxD1cLUOYMjLSJVk4IFumU9QlANm9u5kOlSK6wrbBS2vRl0xzv4bnwSptRCVUMZZqtOkC0Qxcm1ly/wH770GtVzSRV+v68uinF3E8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651854263; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rQ1TfyFqxyqCGdaZlMTRB102yDqEKoO1FsuQsTi1Fto=; b=Fa96X/pq32B5yMbHepl59JvlVs3KroT4EUyfQGPI/n8GyCYKJ4AhrUI3SNPz3D4hi9oXvf0O0FaLHMCPKzx9pXJ63LGEN7kouwEJyXa8OCukvk00mNgga8eeZMENlImmGjEiTHxNLOQsK6s2EbE9j0M2fLA6+T4l2yHhXqFrRTk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651854263129365.21393858267515; Fri, 6 May 2022 09:24:23 -0700 (PDT) Received: from localhost ([::1]:59902 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn0kg-00013U-0X for importer@patchew.org; Fri, 06 May 2022 12:24:22 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39230) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn0i3-0005OF-4M for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:39 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:39888) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn0hz-00053w-Ta for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:38 -0400 Received: by mail-wr1-x433.google.com with SMTP id d5so10687192wrb.6 for ; Fri, 06 May 2022 09:21:35 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j2-20020a5d4482000000b0020c5253d926sm3782082wrq.114.2022.05.06.09.21.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 09:21:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rQ1TfyFqxyqCGdaZlMTRB102yDqEKoO1FsuQsTi1Fto=; b=aKv7oQu4Y3pBVFBGmGzxlSIKcB9Rfjp1Qtyej7mWKd5F/68jQ7A4cFWeSrpPzxhgRC Kh/sFBW8pD8xRV2O1/JiYSuvyb+rjMPDrIBkkLBhykc2Fn3s/8a9gyOdzgqenSIumcpp HpGizsdT92zK4NKZ2KTcKVVS0jqs6hsTd7f8hTfu2nU278Tahvz6syXRRms65YqI6hvZ UqhDCYvE8MwNoyBJYTwUVQx6dZbiGOcqxUxEWmjhfwkEDWToLXqSMGbMoa354mgi1kk4 ydhlcxmkhhWsTSPAt1MAaEg2VRljIilSuzOJomhvHblgjblHb6QjZFkxKHCo5vFqlR4D Cj0w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rQ1TfyFqxyqCGdaZlMTRB102yDqEKoO1FsuQsTi1Fto=; b=nLh/UwlB/LZYW1xisjHdjNm7+pjlbb/dgnBC8TeNsXMN4Ffd/owPj+jRUKIGN0PR9T QiTbWgHWymq/ywzonMIu5HX3SNgrywfMowQrCAdFEWBy/4tBBgaFEnhqV/MI6udypsyS pQBz4N/nVlwUi/fN7HBOeilr2tlmkj6fIFVG5TxeK2wmYZKZ0uYTz7ic6EsIzvVhnU/0 CSCCgmwyzqc1rWCpFcthVMu1HndSKPyVEwsUOM4VdbBx5UVpH+55+UXaoXKVl4+g2qMd MnGA/mQAGnkVfOoyJiXxxJPov/lzd/R2dwvhg88Kb5yY2Eu5cb6nXSbbmF0ERj7FpNlY Fbqg== X-Gm-Message-State: AOAM530GNXI7hN4Y1s+qZ3XHez6UTsx+vETYqT8yCf0XZ8OA/PusRPzI AnkyqSkKWtn1rgI4lcvI3Yme7w== X-Google-Smtp-Source: ABdhPJydcOxVhOeOVSd3CXl8EiYYnDMWvXvmSKMH0k5kpfrSwroRYACn2kRcz4YbG7O4pC+6I3ex9A== X-Received: by 2002:a5d:60d1:0:b0:20a:e22f:b31a with SMTP id x17-20020a5d60d1000000b0020ae22fb31amr3272606wrt.680.1651854094422; Fri, 06 May 2022 09:21:34 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/5] hw/intc/arm_gicv3: Support configurable number of physical priority bits Date: Fri, 6 May 2022 17:21:27 +0100 Message-Id: <20220506162129.2896966-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506162129.2896966-1-peter.maydell@linaro.org> References: <20220506162129.2896966-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651854264245100001 Content-Type: text/plain; charset="utf-8" The GICv3 code has always supported a configurable number of virtual priority and preemption bits, but our implementation currently hardcodes the number of physical priority bits at 8. This is not what most hardware implementations provide; for instance the Cortex-A53 provides only 5 bits of physical priority. Make the number of physical priority/preemption bits driven by fields in the GICv3CPUState, the way that we already do for virtual priority/preemption bits. We set cs->pribits to 8, so there is no behavioural change in this commit. A following commit will add the machinery for CPUs to set this to the correct value for their implementation. Note that changing the number of priority bits would be a migration compatibility break, because the semantics of the icc_apr[][] array changes. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- include/hw/intc/arm_gicv3_common.h | 7 +- hw/intc/arm_gicv3_cpuif.c | 182 ++++++++++++++++++++--------- 2 files changed, 130 insertions(+), 59 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 4e416100559..46677ec345c 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -51,11 +51,6 @@ /* Maximum number of list registers (architectural limit) */ #define GICV3_LR_MAX 16 =20 -/* Minimum BPR for Secure, or when security not enabled */ -#define GIC_MIN_BPR 0 -/* Minimum BPR for Nonsecure when security is enabled */ -#define GIC_MIN_BPR_NS (GIC_MIN_BPR + 1) - /* For some distributor fields we want to model the array of 32-bit * register values which hold various bitmaps corresponding to enabled, * pending, etc bits. These macros and functions facilitate that; the @@ -206,6 +201,8 @@ struct GICv3CPUState { int num_list_regs; int vpribits; /* number of virtual priority bits */ int vprebits; /* number of virtual preemption bits */ + int pribits; /* number of physical priority bits */ + int prebits; /* number of physical preemption bits */ =20 /* Current highest priority pending interrupt for this CPU. * This is cached information that can be recalculated from the diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index d3b92a36636..8499a49be39 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -787,6 +787,36 @@ static uint64_t icv_iar_read(CPUARMState *env, const A= RMCPRegInfo *ri) return intid; } =20 +static uint32_t icc_fullprio_mask(GICv3CPUState *cs) +{ + /* + * Return a mask word which clears the unimplemented priority bits + * from a priority value for a physical interrupt. (Not to be confused + * with the group priority, whose mask depends on the value of BPR + * for the interrupt group.) + */ + return ~0U << (8 - cs->pribits); +} + +static inline int icc_min_bpr(GICv3CPUState *cs) +{ + /* The minimum BPR for the physical interface. */ + return 7 - cs->prebits; +} + +static inline int icc_min_bpr_ns(GICv3CPUState *cs) +{ + return icc_min_bpr(cs) + 1; +} + +static inline int icc_num_aprs(GICv3CPUState *cs) +{ + /* Return the number of APR registers (1, 2, or 4) */ + int aprmax =3D 1 << MAX(cs->prebits - 5, 0); + assert(aprmax <=3D ARRAY_SIZE(cs->icc_apr[0])); + return aprmax; +} + static int icc_highest_active_prio(GICv3CPUState *cs) { /* Calculate the current running priority based on the set bits @@ -794,14 +824,14 @@ static int icc_highest_active_prio(GICv3CPUState *cs) */ int i; =20 - for (i =3D 0; i < ARRAY_SIZE(cs->icc_apr[0]); i++) { + for (i =3D 0; i < icc_num_aprs(cs); i++) { uint32_t apr =3D cs->icc_apr[GICV3_G0][i] | cs->icc_apr[GICV3_G1][i] | cs->icc_apr[GICV3_G1NS][i]; =20 if (!apr) { continue; } - return (i * 32 + ctz32(apr)) << (GIC_MIN_BPR + 1); + return (i * 32 + ctz32(apr)) << (icc_min_bpr(cs) + 1); } /* No current active interrupts: return idle priority */ return 0xff; @@ -980,7 +1010,7 @@ static void icc_pmr_write(CPUARMState *env, const ARMC= PRegInfo *ri, =20 trace_gicv3_icc_pmr_write(gicv3_redist_affid(cs), value); =20 - value &=3D 0xff; + value &=3D icc_fullprio_mask(cs); =20 if (arm_feature(env, ARM_FEATURE_EL3) && !arm_is_secure(env) && (env->cp15.scr_el3 & SCR_FIQ)) { @@ -1004,7 +1034,7 @@ static void icc_activate_irq(GICv3CPUState *cs, int i= rq) */ uint32_t mask =3D icc_gprio_mask(cs, cs->hppi.grp); int prio =3D cs->hppi.prio & mask; - int aprbit =3D prio >> 1; + int aprbit =3D prio >> (8 - cs->prebits); int regno =3D aprbit / 32; int regbit =3D aprbit % 32; =20 @@ -1162,7 +1192,7 @@ static void icc_drop_prio(GICv3CPUState *cs, int grp) */ int i; =20 - for (i =3D 0; i < ARRAY_SIZE(cs->icc_apr[grp]); i++) { + for (i =3D 0; i < icc_num_aprs(cs); i++) { uint64_t *papr =3D &cs->icc_apr[grp][i]; =20 if (!*papr) { @@ -1590,7 +1620,7 @@ static void icc_bpr_write(CPUARMState *env, const ARM= CPRegInfo *ri, return; } =20 - minval =3D (grp =3D=3D GICV3_G1NS) ? GIC_MIN_BPR_NS : GIC_MIN_BPR; + minval =3D (grp =3D=3D GICV3_G1NS) ? icc_min_bpr_ns(cs) : icc_min_bpr(= cs); if (value < minval) { value =3D minval; } @@ -2171,19 +2201,19 @@ static void icc_reset(CPUARMState *env, const ARMCP= RegInfo *ri) =20 cs->icc_ctlr_el1[GICV3_S] =3D ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | - (7 << ICC_CTLR_EL1_PRIBITS_SHIFT); + ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); cs->icc_ctlr_el1[GICV3_NS] =3D ICC_CTLR_EL1_A3V | (1 << ICC_CTLR_EL1_IDBITS_SHIFT) | - (7 << ICC_CTLR_EL1_PRIBITS_SHIFT); + ((cs->pribits - 1) << ICC_CTLR_EL1_PRIBITS_SHIFT); cs->icc_pmr_el1 =3D 0; - cs->icc_bpr[GICV3_G0] =3D GIC_MIN_BPR; - cs->icc_bpr[GICV3_G1] =3D GIC_MIN_BPR; - cs->icc_bpr[GICV3_G1NS] =3D GIC_MIN_BPR_NS; + cs->icc_bpr[GICV3_G0] =3D icc_min_bpr(cs); + cs->icc_bpr[GICV3_G1] =3D icc_min_bpr(cs); + cs->icc_bpr[GICV3_G1NS] =3D icc_min_bpr_ns(cs); memset(cs->icc_apr, 0, sizeof(cs->icc_apr)); memset(cs->icc_igrpen, 0, sizeof(cs->icc_igrpen)); cs->icc_ctlr_el3 =3D ICC_CTLR_EL3_NDS | ICC_CTLR_EL3_A3V | (1 << ICC_CTLR_EL3_IDBITS_SHIFT) | - (7 << ICC_CTLR_EL3_PRIBITS_SHIFT); + ((cs->pribits - 1) << ICC_CTLR_EL3_PRIBITS_SHIFT); =20 memset(cs->ich_apr, 0, sizeof(cs->ich_apr)); cs->ich_hcr_el2 =3D 0; @@ -2238,27 +2268,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .readfn =3D icc_ap_read, .writefn =3D icc_ap_write, }, - { .name =3D "ICC_AP0R1_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 8, .opc2 =3D 5, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, - .readfn =3D icc_ap_read, - .writefn =3D icc_ap_write, - }, - { .name =3D "ICC_AP0R2_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 8, .opc2 =3D 6, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, - .readfn =3D icc_ap_read, - .writefn =3D icc_ap_write, - }, - { .name =3D "ICC_AP0R3_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 8, .opc2 =3D 7, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, - .readfn =3D icc_ap_read, - .writefn =3D icc_ap_write, - }, /* All the ICC_AP1R*_EL1 registers are banked */ { .name =3D "ICC_AP1R0_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 0, @@ -2267,27 +2276,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .readfn =3D icc_ap_read, .writefn =3D icc_ap_write, }, - { .name =3D "ICC_AP1R1_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 1, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, - .readfn =3D icc_ap_read, - .writefn =3D icc_ap_write, - }, - { .name =3D "ICC_AP1R2_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 2, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, - .readfn =3D icc_ap_read, - .writefn =3D icc_ap_write, - }, - { .name =3D "ICC_AP1R3_EL1", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 3, - .type =3D ARM_CP_IO | ARM_CP_NO_RAW, - .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, - .readfn =3D icc_ap_read, - .writefn =3D icc_ap_write, - }, { .name =3D "ICC_DIR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 11, .opc2 =3D 1, .type =3D ARM_CP_IO | ARM_CP_NO_RAW, @@ -2430,6 +2418,54 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { }, }; =20 +static const ARMCPRegInfo gicv3_cpuif_icc_apxr1_reginfo[] =3D { + { .name =3D "ICC_AP0R1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 8, .opc2 =3D 5, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, + .readfn =3D icc_ap_read, + .writefn =3D icc_ap_write, + }, + { .name =3D "ICC_AP1R1_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 1, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, + .readfn =3D icc_ap_read, + .writefn =3D icc_ap_write, + }, +}; + +static const ARMCPRegInfo gicv3_cpuif_icc_apxr23_reginfo[] =3D { + { .name =3D "ICC_AP0R2_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 8, .opc2 =3D 6, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, + .readfn =3D icc_ap_read, + .writefn =3D icc_ap_write, + }, + { .name =3D "ICC_AP0R3_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 8, .opc2 =3D 7, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D gicv3_fiq_access, + .readfn =3D icc_ap_read, + .writefn =3D icc_ap_write, + }, + { .name =3D "ICC_AP1R2_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 2, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, + .readfn =3D icc_ap_read, + .writefn =3D icc_ap_write, + }, + { .name =3D "ICC_AP1R3_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 9, .opc2 =3D 3, + .type =3D ARM_CP_IO | ARM_CP_NO_RAW, + .access =3D PL1_RW, .accessfn =3D gicv3_irq_access, + .readfn =3D icc_ap_read, + .writefn =3D icc_ap_write, + }, +}; + static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) { GICv3CPUState *cs =3D icc_cs_from_env(env); @@ -2763,6 +2799,44 @@ void gicv3_init_cpuif(GICv3State *s) * get back to the GICv3CPUState from the CPUARMState. */ define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); + + /* + * For the moment, retain the existing behaviour of 8 priority bit= s; + * in a following commit we will take this from the CPU state, + * as we do for the virtual priority bits. + */ + cs->pribits =3D 8; + /* + * The GICv3 has separate ID register fields for virtual priority + * and preemption bit values, but only a single ID register field + * for the physical priority bits. The preemption bit count is + * always the same as the priority bit count, except that 8 bits + * of priority means 7 preemption bits. We precalculate the + * preemption bits because it simplifies the code and makes the + * parallels between the virtual and physical bits of the GIC + * a bit clearer. + */ + cs->prebits =3D cs->pribits; + if (cs->prebits =3D=3D 8) { + cs->prebits--; + } + /* + * Check that CPU code defining pribits didn't violate + * architectural constraints our implementation relies on. + */ + g_assert(cs->pribits >=3D 4 && cs->pribits <=3D 8); + + /* + * gicv3_cpuif_reginfo[] defines ICC_AP*R0_EL1; add definitions + * for ICC_AP*R{1,2,3}_EL1 if the prebits value requires them. + */ + if (cs->prebits >=3D 6) { + define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr1_reginfo); + } + if (cs->prebits =3D=3D 7) { + define_arm_cp_regs(cpu, gicv3_cpuif_icc_apxr23_reginfo); + } + if (arm_feature(&cpu->env, ARM_FEATURE_EL2) && cpu->gic_num_lrs) { int j; --=20 2.25.1 From nobody Sun May 19 10:57:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651854362; cv=none; d=zohomail.com; s=zohoarc; b=izvX+VBFY1vqOhYWEKlfC2IRia3bFX59Z4CqAcYf/rzTX3Oao2MJ2Y6xhJHvNIXlJM7G3AX1t+TkV43Pdtr0RWGBMcmIXKT3IjG2wPmoT38rON0j2Z2fDnqRJfftWOjL0jGahLOFzm/yOF9e2v6B/sr7auIwfMf0S7SeQZzKJvE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651854362; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=tr8TV4hqUwZ65ANOZtVJWuhRalEYVu1kyymwRoj7iTA=; b=DANTNXyn6BfexGtuJZrBMHXEGYc7pnrmDloCvGHuksxUzKxthpuYDWHsEpgBjrLcnK9QmTxs3b1fOZtqQq+EXuIIP/DTZeLoB4FJbTWzIljbu46j6d0SjA+MJqMenrAQnc4WlS7O2VMtE7PMdFSyXqb9PJjp49U0rkQc04ZStNA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651854362731464.54438500875983; Fri, 6 May 2022 09:26:02 -0700 (PDT) Received: from localhost ([::1]:36376 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn0mH-0004GH-Hl for importer@patchew.org; Fri, 06 May 2022 12:26:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39232) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn0i3-0005OG-4H for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:39 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:38844) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn0i0-000569-N3 for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:38 -0400 Received: by mail-wr1-x433.google.com with SMTP id k2so10681352wrd.5 for ; Fri, 06 May 2022 09:21:36 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j2-20020a5d4482000000b0020c5253d926sm3782082wrq.114.2022.05.06.09.21.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 09:21:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=tr8TV4hqUwZ65ANOZtVJWuhRalEYVu1kyymwRoj7iTA=; b=DyAXxuYVisY/VQqpleSgDexuIZwVffAmbCaoC6aYTTAX+10mZAPaWQ4+d7/kSXb2N1 6cL1pz1lbmICYlUywmmh0JxgEtjGEzBObCXQJDQ57F6V7JANJVioLWMu/gNqrn6ce+cy ym269rD1k1e5Ne0ZOKzc7sZkdfsgjK+P/HgBcV++BjFYD+KfExEVUtxVw4xbIlICE9JL C/OZvpo2RGiyzCts+/ukyq9tjwPmRxRg7niK06TBksKY/IlCiHz+mW1SHLW5Uqh5TQVT ixlgnzP6KUkijECUW91kB3uRu1/MeYdxqCGEdAYdYk8NR+h+5n6/StxmR/3F2eJORAZl 40eg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=tr8TV4hqUwZ65ANOZtVJWuhRalEYVu1kyymwRoj7iTA=; b=NHz50XYp7KokHnErPrw498oXGpWrW2UIHciUcEpPx7lbXsQby2ecdxTFgDm1YMtxLJ 0ge2YkK4QQsv7+uX+jdOYWCJVq+tv14QNVI7xg2boj9keizN3deQkG3RzPzyB/pMcjmo bxiVGe5oakVBPnWNzGIpz+ZfiSoWoY3+Ij5kiXmK5TwkJ9XxRpixoFPJInX703FQcOft GocLqrrIJpamXhOHJ//+T6vK+26x9WrQVM9nDLQ0E3pTognOG+m4wq6VHAoQylL9Dk1w OPcdLKKW43WxCLPBetWa/l1Qs4VVj91ak3QqMbzS0AAHtEYD5xrZtFmy86uTuoa/D0wC a0Ig== X-Gm-Message-State: AOAM530i1DtjEvRfNu7w3bGBBJVxs1j+ZfioigB5yURsOofu+u64tryW VppIyehC2zY2faxzV9v+VR8Gbw== X-Google-Smtp-Source: ABdhPJxiy/znK5uA21Vny70mvYuZ+HeG15uF3MEAwGJ4aw018YMGyYi1UakO96xwgSODlAl7pxgZxg== X-Received: by 2002:a05:6000:2a2:b0:20c:999d:bdec with SMTP id l2-20020a05600002a200b0020c999dbdecmr3346136wry.36.1651854095396; Fri, 06 May 2022 09:21:35 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/5] hw/intc/arm_gicv3: Use correct number of priority bits for the CPU Date: Fri, 6 May 2022 17:21:28 +0100 Message-Id: <20220506162129.2896966-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506162129.2896966-1-peter.maydell@linaro.org> References: <20220506162129.2896966-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651854364877100001 Content-Type: text/plain; charset="utf-8" Make the GICv3 set its number of bits of physical priority from the implementation-specific value provided in the CPU state struct, in the same way we already do for virtual priority bits. Because this would be a migration compatibility break, we provide a property force-8-bit-prio which is enabled for 7.0 and earlier versioned board models to retain the legacy "always use 8 bits" behaviour. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- I have guessed at the right value for the A64FX, but if we can find the correct ICC_CTLR_EL1 value that would be better. --- include/hw/intc/arm_gicv3_common.h | 1 + target/arm/cpu.h | 1 + hw/core/machine.c | 4 +++- hw/intc/arm_gicv3_common.c | 5 +++++ hw/intc/arm_gicv3_cpuif.c | 14 ++++++++++---- target/arm/cpu64.c | 9 +++++++++ 6 files changed, 29 insertions(+), 5 deletions(-) diff --git a/include/hw/intc/arm_gicv3_common.h b/include/hw/intc/arm_gicv3= _common.h index 46677ec345c..ab5182a28a2 100644 --- a/include/hw/intc/arm_gicv3_common.h +++ b/include/hw/intc/arm_gicv3_common.h @@ -248,6 +248,7 @@ struct GICv3State { uint32_t revision; bool lpi_enable; bool security_extn; + bool force_8bit_prio; bool irq_reset_nonsecure; bool gicd_no_migration_shift_bug; =20 diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca01f909a86..f8873bdbb97 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -993,6 +993,7 @@ struct ArchCPU { int gic_num_lrs; /* number of list registers */ int gic_vpribits; /* number of virtual priority bits */ int gic_vprebits; /* number of virtual preemption bits */ + int gic_pribits; /* number of physical priority bits */ =20 /* Whether the cfgend input is high (i.e. this CPU should reset into * big-endian mode). This setting isn't used directly: instead it mod= ifies diff --git a/hw/core/machine.c b/hw/core/machine.c index cb9bbc844d2..db012376785 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -37,7 +37,9 @@ #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" =20 -GlobalProperty hw_compat_7_0[] =3D {}; +GlobalProperty hw_compat_7_0[] =3D { + { "arm-gicv3-common", "force-8-bit-prio", "on" }, +}; const size_t hw_compat_7_0_len =3D G_N_ELEMENTS(hw_compat_7_0); =20 GlobalProperty hw_compat_6_2[] =3D { diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 5634c6fc788..351843db4aa 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -563,6 +563,11 @@ static Property arm_gicv3_common_properties[] =3D { DEFINE_PROP_UINT32("revision", GICv3State, revision, 3), DEFINE_PROP_BOOL("has-lpi", GICv3State, lpi_enable, 0), DEFINE_PROP_BOOL("has-security-extensions", GICv3State, security_extn,= 0), + /* + * Compatibility property: force 8 bits of physical priority, even + * if the CPU being emulated should have fewer. + */ + DEFINE_PROP_BOOL("force-8-bit-prio", GICv3State, force_8bit_prio, 0), DEFINE_PROP_ARRAY("redist-region-count", GICv3State, nb_redist_regions, redist_region_count, qdev_prop_uint32, uint32_t), DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8499a49be39..e277a807bd5 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2801,11 +2801,17 @@ void gicv3_init_cpuif(GICv3State *s) define_arm_cp_regs(cpu, gicv3_cpuif_reginfo); =20 /* - * For the moment, retain the existing behaviour of 8 priority bit= s; - * in a following commit we will take this from the CPU state, - * as we do for the virtual priority bits. + * The CPU implementation specifies the number of supported + * bits of physical priority. For backwards compatibility + * of migration, we have a compat property that forces use + * of 8 priority bits regardless of what the CPU really has. */ - cs->pribits =3D 8; + if (s->force_8bit_prio) { + cs->pribits =3D 8; + } else { + cs->pribits =3D cpu->gic_pribits; + } + /* * The GICv3 has separate ID register fields for virtual priority * and preemption bit values, but only a single ID register field diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c841d55d0e9..490231b90f3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -143,6 +143,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -196,6 +197,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -247,6 +249,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + cpu->gic_pribits =3D 5; define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); } =20 @@ -961,6 +964,12 @@ static void aarch64_a64fx_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; + /* + * TODO: What does the real A64FX GICv3 provide ? + * This is a guess based on what other Arm CPUs do; to find the correct + * answer we need the value of the A64FX's ICC_CTLR_EL1 register. + */ + cpu->gic_pribits =3D 5; =20 /* Suppport of A64FX's vector length are 128,256 and 512bit only */ aarch64_add_sve_properties(obj); --=20 2.25.1 From nobody Sun May 19 10:57:16 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651854397; cv=none; d=zohomail.com; s=zohoarc; b=JEWwhgn9OvsUlmX1/q5qkrFMWafE1TaKV6jk2+IMHAOIvyVGs7Lb1ospMot+pyFTPaeVzQc3ADdEaLRYKK04rYVPxIR7K+Rz+4nk1g0ZIxRnxgMXg2NQzEIgAPfdBVyJReWtyBVTO3XZxgZ3KPGQwsCftD7tNklUyKvjfByS3mY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651854397; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rznGUlqhm1e5gkG+nuwND08zKHXTaunZHlwOXJp3GXs=; b=nBw/3xSphXy5SenTc8Ryj9tPSfXtGoPCzyETBe+O2UsMGlVTkNBQ71OwMEDuLYrWAjC4sB/Mm0tGGKg+kgl8XHvBw4VljyY3M+pPGIkcted5dQ0sGYLVcx5u+rB+Y7csYlb3OlTaYutQUrW3EnTqQ5xLEwy+0qIaULYR1TkuMTY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651854397982591.0460580305266; Fri, 6 May 2022 09:26:37 -0700 (PDT) Received: from localhost ([::1]:38106 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nn0mr-0005Oc-0R for importer@patchew.org; Fri, 06 May 2022 12:26:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39250) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nn0i4-0005PB-Ii for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:41 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:36499) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nn0i2-00056x-R7 for qemu-devel@nongnu.org; Fri, 06 May 2022 12:21:40 -0400 Received: by mail-wr1-x42d.google.com with SMTP id u3so10710938wrg.3 for ; Fri, 06 May 2022 09:21:37 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j2-20020a5d4482000000b0020c5253d926sm3782082wrq.114.2022.05.06.09.21.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 May 2022 09:21:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rznGUlqhm1e5gkG+nuwND08zKHXTaunZHlwOXJp3GXs=; b=FwrRa/TvxVORlHBkmC27VQUTCDLeyyslUHXesXwBr6jkQd1og5PR1BVvKTGLlipVJn aHd4g7shJbWXBKxZNGmV2PFaYA9rK3AYiurZPnT3AfQaZcwzi2PwM80b7JX6W8TJYYHH F1bLaDJ95pc38JeppYeggie45O2qfNkxDamxYTB5aLou04Xrd6rl65/ueaHDVdlEXFCP qIfWhe8bYAlU/dDBJc8usEBxm7XAQhdsobONUcefAUQrI6UWN3+tb53CC51hrpYvz0Wk Tfd3PA0QDX2WRqMc30iK6i+9z9QzgCkFmyg9bOx7lQPkENc0ls2lHm6JCrLAzlhDaBUf Okfw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rznGUlqhm1e5gkG+nuwND08zKHXTaunZHlwOXJp3GXs=; b=wDWJt/AdtzedNt0XbfHaXuNdnUqOJ9tiE4R3J3mxgf1SC6vGUR0bM0ivKjhJ69KxoU dOopYpOnesk+WJTg0Pm5eXlhPcUrSXbXwz/ZuEZirxKvtXOz3+L6rDARlogeC5KzW6ms b21pzq4MQgSXmXV65bsBGko7CDBrUQwQsrKTIihEq0fvcygB6/u1a4XeKW7uK5o/52Vv RD/fMJQxLFS9/odnspA2DZ+8ujS2JR+aFFNg340XQ0EIZon6bLyPmi1VjjPsUiIihO4W jxkDMhNVDqGdlH1gm7ditQ3rW+bR447aw9PBFA8dCrMZ6O7Wf6Odki6s9mEyg6n6IORr CDDQ== X-Gm-Message-State: AOAM531tNAgSXAsZOZIdpfM1v5naDS0H8hAdGtZ/kZkVjXwlX6XK8TFR oNVj/AO27H4dX38hUCXsCHIOmg== X-Google-Smtp-Source: ABdhPJw1sBuERyX8dXtRwZm7GRAVH8De81msT9/9R270YnTpUL49jAyI01+rR4tyc8yFxLq5byg8zA== X-Received: by 2002:adf:eb87:0:b0:20c:a5b5:6731 with SMTP id t7-20020adfeb87000000b0020ca5b56731mr3383751wrn.199.1651854096235; Fri, 06 May 2022 09:21:36 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 5/5] hw/intc/arm_gicv3: Provide ich_num_aprs() Date: Fri, 6 May 2022 17:21:29 +0100 Message-Id: <20220506162129.2896966-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220506162129.2896966-1-peter.maydell@linaro.org> References: <20220506162129.2896966-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651854398949100001 Content-Type: text/plain; charset="utf-8" We previously open-coded the expression for the number of virtual APR registers and the assertion that it was not going to cause us to overflow the cs->ich_apr[] array. Factor this out into a new ich_num_aprs() function, for consistency with the icc_num_aprs() function we just added for the physical APR handling. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- hw/intc/arm_gicv3_cpuif.c | 18 ++++++++++-------- 1 file changed, 10 insertions(+), 8 deletions(-) diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index e277a807bd5..5418ad9bbc5 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -49,6 +49,14 @@ static inline int icv_min_vbpr(GICv3CPUState *cs) return 7 - cs->vprebits; } =20 +static inline int ich_num_aprs(GICv3CPUState *cs) +{ + /* Return the number of virtual APR registers (1, 2, or 4) */ + int aprmax =3D 1 << (cs->vprebits - 5); + assert(aprmax <=3D ARRAY_SIZE(cs->ich_apr[0])); + return aprmax; +} + /* Simple accessor functions for LR fields */ static uint32_t ich_lr_vintid(uint64_t lr) { @@ -145,11 +153,8 @@ static int ich_highest_active_virt_prio(GICv3CPUState = *cs) * in the ICH Active Priority Registers. */ int i; - int aprmax =3D 1 << (cs->vprebits - 5); =20 - assert(aprmax <=3D ARRAY_SIZE(cs->ich_apr[0])); - - for (i =3D 0; i < aprmax; i++) { + for (i =3D 0; i < ich_num_aprs(cs); i++) { uint32_t apr =3D cs->ich_apr[GICV3_G0][i] | cs->ich_apr[GICV3_G1NS][i]; =20 @@ -1333,11 +1338,8 @@ static int icv_drop_prio(GICv3CPUState *cs) * 32 bits are actually relevant. */ int i; - int aprmax =3D 1 << (cs->vprebits - 5); =20 - assert(aprmax <=3D ARRAY_SIZE(cs->ich_apr[0])); - - for (i =3D 0; i < aprmax; i++) { + for (i =3D 0; i < ich_num_aprs(cs); i++) { uint64_t *papr0 =3D &cs->ich_apr[GICV3_G0][i]; uint64_t *papr1 =3D &cs->ich_apr[GICV3_G1NS][i]; int apr0count, apr1count; --=20 2.25.1