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([2607:fb90:5fe8:83ea:bbf4:c9ef:4f3:11c6]) by smtp.gmail.com with ESMTPSA id s36-20020a0568302aa400b0060603221259sm857273otu.41.2022.05.05.11.50.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:50:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=4YqOGbb38qjiPY2dXCdLJrEWMXvDZh6b/gyG/7bmWLA=; b=ilBdOtWmaaU//pKM7FFsegWSpvRNjwDLc4z7U6l23Xp4eTcQQb967RGtHgV3UlIfCY HxJpInnH+n/03o8SXKeG++uH3iJ5taqcVP7u2CeQifybtfDAjvz8Nk4875XSqLvv4FJ0 gbeb90wF/sUrb+rcr6va4fUDnXWrv3mhKjZSQcGvYamj6uoz6hrOarjhrMPeloM79vLJ jElxw0cazd4K5LZ7SljGLYhotpWBLyHNgzky7FP93tUAwDUajKcHxc438tmDvB7gBXwb lxcx4Mt/ByBRbRsYjb8WkcVXvbN1E8h5wq/qeda4buhghA7l+xKPG74RPMAA+SxI2LVg pYgA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=4YqOGbb38qjiPY2dXCdLJrEWMXvDZh6b/gyG/7bmWLA=; b=Q5ErUIVn2dFRFd93iejhZ647OhgTPv1QQNjm3bf4phcb3U3TFYyc43jHmNAOgQyZJQ B32j6M4TvXbcmsHCzyQi99q4a9lY4AG/+oMWVxsgRKMGlNtNtOz8eP3RY0pa43s3ZJHU Pyg1O1zl9U/XlqOvnEQsUkqxhktuRvxSM/ysYFwZenJ9iJe3hUCi1RkgXIlfhL1qMm9+ zwaH5qSvESQsBTgg4bYfsC3eMm4Xfbj1YWPYA0rXf1SLOUWBLjJpOwQ4vQIC2y2k5LWk 88LprIgu1xvyBJlJVd9VPxWfHk8PjUMgi1N5p3uuRj/0UDAia3c9WqI4cihkrakcdf0W cAnA== X-Gm-Message-State: AOAM5324/29n40B8mvVViVcMKx+mzMUBo3BDlJmcR40sHV1OqNfz9MEK AHu1M0lbANLKdYqXnzkdQ0fzc6K4902dlWSB X-Google-Smtp-Source: ABdhPJzjEavGJbfQZS4sCZ/UjiBj7ffmNiOeRDHjVZsMlsy/XiIpsGhiZyqYz7bzoSBAOZH+Nn5F6g== X-Received: by 2002:a05:6808:56b:b0:325:9f5e:3fd4 with SMTP id j11-20020a056808056b00b003259f5e3fd4mr3227705oig.199.1651776612848; Thu, 05 May 2022 11:50:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 03/24] target/arm: Merge zcr reginfo Date: Thu, 5 May 2022 13:49:45 -0500 Message-Id: <20220505185006.200555-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220505185006.200555-1-richard.henderson@linaro.org> References: <20220505185006.200555-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651778580781100001 Content-Type: text/plain; charset="utf-8" Drop zcr_no_el2_reginfo and merge the 3 registers into one array, now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped while registering. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 55 ++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index ea2788b3d5..72d05070f0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6122,35 +6122,22 @@ static void zcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static const ARMCPRegInfo zcr_el1_reginfo =3D { - .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_no_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore -}; - -static const ARMCPRegInfo zcr_el3_reginfo =3D { - .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write +static const ARMCPRegInfo zcr_reginfo[] =3D { + { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 void hw_watchpoint_update(ARMCPU *cpu, int n) @@ -8233,15 +8220,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_sve, cpu)) { - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); - if (arm_feature(env, ARM_FEATURE_EL2)) { - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); - } else { - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); - } + define_arm_cp_regs(cpu, zcr_reginfo); } =20 #ifdef TARGET_AARCH64 --=20 2.34.1