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([2607:fb90:5fe8:83ea:bbf4:c9ef:4f3:11c6]) by smtp.gmail.com with ESMTPSA id s36-20020a0568302aa400b0060603221259sm857273otu.41.2022.05.05.11.50.33 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GY2odDA192T0ClkUF75+bPEfdCFgpsNoLihYttz/3zY=; b=RuupAJxij1iUWDYoPju8S2pJjrLZ6lUUNzfm0xNTEUHt1bxfRU3/MTVwCxt4Jcf01X arIa8pwsnC3k9TlGbo7PwCSTUvqLTpC4yjj2X2f4E6erW5HWO9ez5qogDrRFa7jxeRwr 4gDWP2/kQ1kzDwq52Lu+/n6ocJrZbKB/gT9idufYJyChbEwDfbNVV+HgzD9MCHtfLD8j sbPGw5mBZxqCJqWwn16KQ9od3DvMX/9vOwYvwENT3XxvXKpQYp+VZCBh9kFU7oDmgEc1 Qw/qQ1dAhSaOn7dNKOPIOujt4KHXxsDJpnwKa8McaNdTiNdCBhKI26vAMDRj1U5gCj2s acjQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GY2odDA192T0ClkUF75+bPEfdCFgpsNoLihYttz/3zY=; b=pdcNWwTycMmwId+JiWkQx0XBG6pFFuaUEn/6rn1I1YaiMYW/q2C5RNIJmdOUC8hK3x gZfTt81aKjkhxjz/hKI9OfES5FSe43Mfr1g71APDmEnQvfC+kfxK4pye0JC2c5txUYTr aBd56rE9RD3j0WmOgT2cksj5+yofaz16MDUjm1y2wdvW4ZvM2xqeHeyvgyN0aKwv2Jc4 nfXn+DMt/ODhZqt2ujy9FTgGulFefAzc8sPQER3Jh1dLFSmEmH5em37LpgWiO2wnCJNn 3AkS2Pb8Ngq/q/Y76/RyVK0qcsMsLvWdacD5rgaYWPScwyC551J4WVxvjEzDG7bLxmUB mVDQ== X-Gm-Message-State: AOAM531OE/PmD4LtxjJ+dUmp44tHezZPhXxzV5SfBF1woBeFAwneEXuA c06z3mJKcJ+t1qX/TQi8PnBOtrMaxljwrnN9 X-Google-Smtp-Source: ABdhPJws0dm89mt6zQGbIfv3OMp2tavr4A8SjVe70fSIyJ5AxnwvI176ZH7yVxliKZoLD1/5aoomqg== X-Received: by 2002:aca:a945:0:b0:325:9428:ac02 with SMTP id s66-20020acaa945000000b003259428ac02mr3130507oie.268.1651776634933; Thu, 05 May 2022 11:50:34 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 18/24] target/arm: Enable FEAT_IESB for -cpu max Date: Thu, 5 May 2022 13:50:00 -0500 Message-Id: <20220505185006.200555-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220505185006.200555-1-richard.henderson@linaro.org> References: <20220505185006.200555-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651779385366100001 Content-Type: text/plain; charset="utf-8" This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8110408000..b200012d89 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -25,6 +25,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 35881c74b2..10410619f9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ --=20 2.34.1