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([2607:fb90:5fe8:83ea:bbf4:c9ef:4f3:11c6]) by smtp.gmail.com with ESMTPSA id s36-20020a0568302aa400b0060603221259sm857273otu.41.2022.05.05.11.50.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:50:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UA0u5zIb+IjVjwjFedkOJVeM7leXzM2MF4hE+Hu/fBc=; b=dp44kJCItyvzaIgdlYDpsN8be0sKQJNR6F7Bx6SwfWUiUFd7CUbxc20nOoIvLmbgsx Jq+Ie4fiEjXbt+EEYaKjJ28sgw8VNf0YL+WMjdjNZ86X8Bg1Le37DNW59PTh2SFl0763 iiNNpwfEIQ6mEDpA1Z0G/We/J3XwqwGBcCNV6fMQImZ4HwGaSoGoJSeartMY5UxTPlYF fIDSCVuoP1C4UxvHFEf7+s4rrUH/Tl8G/efqw4zpbjuZ4Xfp9KEfXbT8nLh5ELWkXJ/3 aWspqd+5hqqA93Tx2ZA5SjaGAa1Ee0y8yUr9zlOfH6/P18o+60gC9KRhJbRWCI3OoCIo jW3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UA0u5zIb+IjVjwjFedkOJVeM7leXzM2MF4hE+Hu/fBc=; b=x79FICYOvKLYvD5sUOyBpaHIGTgch+mTXvuhFUUPsnQE3GN4Ji6W+1OSphLZQ6reCe 3SGebIgNIdjGsEzri8+m3p/WqyCYJNrYjF5XZBYfgqeLnelTCRJQrLq84sbqGhFgZPHN bqivefrAH6aXQXjAZMWUEYmhqXrpn9NGEeJhhiF6a2LmVxLuvClgjak//aE8ANDx6D9L h+QD3jrsTQhYU9MvVchMHsepcjTL5kFGjpcX+cbqcYGNC87rERtD9ykOqqmFkD8XKGKD hhXngA/r9k4OKyodD584+7sw1/mGYQ4MovhZzyUcUJqfSsrX2Duwq5ChAdkkDIt4k5Uy v3jw== X-Gm-Message-State: AOAM532TptpKQ7XoyEgNEGmMe+hXLcF1y4UcDqn2ZJulsd24bdOhWaLy 4K66y/z03OhM9E/ycTxjmQMTpd9yY2oe6ViW X-Google-Smtp-Source: ABdhPJwctTeVVPT0boW2COFncwEbk93Ec786oOjJ6olox3CbIN76rw40ZxvJfWelSxmrqihzSEUMkw== X-Received: by 2002:a54:4d86:0:b0:324:ecc3:fd02 with SMTP id y6-20020a544d86000000b00324ecc3fd02mr3229632oix.243.1651776622942; Thu, 05 May 2022 11:50:22 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Cc: qemu-arm@nongnu.org, Peter Maydell Subject: [PATCH v5 10/24] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Thu, 5 May 2022 13:49:52 -0500 Message-Id: <20220505185006.200555-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220505185006.200555-1-richard.henderson@linaro.org> References: <20220505185006.200555-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::231; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x231.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651778296883100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 01176b2569..7995ff2712 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1801,11 +1801,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1836,12 +1838,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1