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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id n67-20020aca4046000000b00325cda1ff94sm917146oia.19.2022.05.05.11.51.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:51:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Chk0RINyrs3VC8UL+UPYQkDpM9x5xllD+vsKhxm4sfM=; b=e7au+DnA80YcxCewrvqIIhtYpxiwN6ib+SpfbB5IB02b/KozZ/YLLQxozDjy6dJ5Vn Se1qG9hYt4ZqSSZNh4HSi+/9RCe8GEIWzS3rMn9l2vuOxYMR2TVW2S+Vy0YmEmOishoa ps/1y9+l2h1VdqQfhjm7pwxFvTyZd2b9ueaHi11+CrzXNJiigfvjr4eDqljKUf2r75Zi Dv9MjuIrvC/H7SR5ypN6dXLSsvrHOTgFk7Un/hBfhZa5riZCv1rn9Ry2srNAlQ7OwyQW E8FQC5c3PEZABo3tB0+t/3spevY7JNbFowoKNm3DmbGx/kwNN4V6NZPX8lmkfxka4ytq uNrA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Chk0RINyrs3VC8UL+UPYQkDpM9x5xllD+vsKhxm4sfM=; b=EZSd5jTlAeaIn/tqbN7Xi7CdTxgYXymNfVk30CJyt9bMuz7tdpv6XPy3lFyhn+Xs8S uQaKQu/Xhh8u+KAiWucJHynE+JzNcS/D30XP7CB55XXJLm7gq+EwtR+UVncU6tATGFPS 0TrIsZNCejhmjKWZC9bEw0bcCFknd4MeoE+Tu/Xv1Cp7mxWeA8muUFUTeoYev8ZQWDJQ WdlaMRfc4Biz+TGf0S5+v9Pdss8RUSsFBFkrcPG8yFk1ha81pOjx12TLNk5O89WJV++R kuZ6uVlcm96PCfOyYNU2KhjKxUvLhtoLxadHwlJCcdr27Cjhq1fcHee7sYl1wvMFqapV xU5Q== X-Gm-Message-State: AOAM5322B4VTpiiwNx7KdrpirgeoFk1z0ZnYdZjjZ5ZRgl1l94znnsVd L27/h9Kma8xbbmXmeBzyhmBaWOXzMuY= X-Google-Smtp-Source: ABdhPJzVCMq6/DLstsnOIggEL49GYxd80kaeytsJAtaY00JF02ldYf+piuQNTEIILFPo+BrZWw1LIQ== X-Received: by 2002:a05:6870:f728:b0:ed:9d92:7ba3 with SMTP id ej40-20020a056870f72800b000ed9d927ba3mr2950371oab.177.1651776690528; Thu, 05 May 2022 11:51:30 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, richard.henderson@linaro.org, =?UTF-8?q?V=C3=ADctor=20Colombo?= Subject: [PULL 27/30] target/ppc: Remove msr_hv macro Date: Thu, 5 May 2022 15:49:35 -0300 Message-Id: <20220505184938.351866-28-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220505184938.351866-1-danielhb413@gmail.com> References: <20220505184938.351866-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2001:4860:4864:20::34; envelope-from=danielhb413@gmail.com; helo=mail-oa1-x34.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1651781096859100001 From: V=C3=ADctor Colombo msr_hv macro hides the usage of env->msr, which is a bad behavior. Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson Signed-off-by: V=C3=ADctor Colombo Reviewed-by: Richard Henderson Message-Id: <20220504210541.115256-20-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza --- target/ppc/cpu.h | 11 ++++++----- target/ppc/cpu_init.c | 6 ++++-- target/ppc/excp_helper.c | 8 ++++---- target/ppc/mem_helper.c | 4 ++-- target/ppc/misc_helper.c | 2 +- target/ppc/mmu-radix64.c | 6 +++--- 6 files changed, 20 insertions(+), 17 deletions(-) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 5ac7d7d68f..9f19b3c0a8 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -354,6 +354,12 @@ typedef enum { #define MSR_RI 1 /* Recoverable interrupt 1 = */ #define MSR_LE 0 /* Little-endian mode 1 hfla= gs */ =20 +#if defined(TARGET_PPC64) +FIELD(MSR, HV, MSR_HV, 1) +#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV) +#else +#define FIELD_EX64_HV(storage) 0 +#endif FIELD(MSR, TS, MSR_TS0, 2) FIELD(MSR, CM, MSR_CM, 1) FIELD(MSR, GS, MSR_GS, 1) @@ -489,11 +495,6 @@ FIELD(MSR, LE, MSR_LE, 1) #define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */ #define HFSCR_IC_MSGP 0xA =20 -#if defined(TARGET_PPC64) -#define msr_hv ((env->msr >> MSR_HV) & 1) -#else -#define msr_hv (0) -#endif #define msr_de ((env->msr >> MSR_DE) & 1) =20 #define DBCR0_ICMP (1 << 27) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 10e7c41bc9..d4c7813de5 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6305,7 +6305,8 @@ static bool cpu_has_work_POWER9(CPUState *cs) if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && (env->spr[SPR_LPCR] & LPCR_EEE)) { bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) { + if (!heic || !FIELD_EX64_HV(env->msr) || + FIELD_EX64(env->msr, MSR, PR)) { return true; } } @@ -6520,7 +6521,8 @@ static bool cpu_has_work_POWER10(CPUState *cs) if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && (env->spr[SPR_LPCR] & LPCR_EEE)) { bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) { + if (!heic || !FIELD_EX64_HV(env->msr) || + FIELD_EX64(env->msr, MSR, PR)) { return true; } } diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index aa201c63c6..cb752b184a 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1715,7 +1715,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) { /* LPCR will be clear when not supported so this will work */ bool hdice =3D !!(env->spr[SPR_LPCR] & LPCR_HDICE); - if ((async_deliver || msr_hv =3D=3D 0) && hdice) { + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) { /* HDEC clears on delivery */ env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_HDECR); powerpc_excp(cpu, POWERPC_EXCP_HDECR); @@ -1727,7 +1727,7 @@ static void ppc_hw_interrupt(CPUPPCState *env) if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) { /* LPCR will be clear when not supported so this will work */ bool hvice =3D !!(env->spr[SPR_LPCR] & LPCR_HVICE); - if ((async_deliver || msr_hv =3D=3D 0) && hvice) { + if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) { powerpc_excp(cpu, POWERPC_EXCP_HVIRT); return; } @@ -1738,9 +1738,9 @@ static void ppc_hw_interrupt(CPUPPCState *env) bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ - if ((async_deliver && !(heic && msr_hv && + if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) && !FIELD_EX64(env->msr, MSR, PR))) || - (env->has_hv_mode && msr_hv =3D=3D 0 && !lpes0)) { + (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) { if (books_vhyp_promotes_external_to_hvirt(cpu)) { powerpc_excp(cpu, POWERPC_EXCP_HVIRT); } else { diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 9af135e88e..d1163f316c 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -612,11 +612,11 @@ void helper_tbegin(CPUPPCState *env) env->spr[SPR_TEXASR] =3D (1ULL << TEXASR_FAILURE_PERSISTENT) | (1ULL << TEXASR_NESTING_OVERFLOW) | - (msr_hv << TEXASR_PRIVILEGE_HV) | + (FIELD_EX64_HV(env->msr) << TEXASR_PRIVILEGE_HV) | (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) | (1ULL << TEXASR_FAILURE_SUMMARY) | (1ULL << TEXASR_TFIAR_EXACT); - env->spr[SPR_TFIAR] =3D env->nip | (msr_hv << 1) | + env->spr[SPR_TFIAR] =3D env->nip | (FIELD_EX64_HV(env->msr) << 1) | FIELD_EX64(env->msr, MSR, PR); env->spr[SPR_TFHAR] =3D env->nip + 4; env->crf[0] =3D 0xB; /* 0b1010 =3D transaction failure */ diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 06aa716cab..b0a5e7ce76 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -73,7 +73,7 @@ void helper_hfscr_facility_check(CPUPPCState *env, uint32= _t bit, const char *caller, uint32_t cause) { #ifdef TARGET_PPC64 - if ((env->msr_mask & MSR_HVB) && !msr_hv && + if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) && !(env->spr[SPR_HFSCR] & (1UL << bit))= ) { raise_hv_fu_exception(env, bit, caller, cause, GETPC()); } diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index e88f51fd34..21ac958e48 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -37,7 +37,7 @@ static bool ppc_radix64_get_fully_qualified_addr(const CP= UPPCState *env, return false; } =20 - if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */ + if (FIELD_EX64(env->msr, MSR, HV)) { /* MSR[HV] -> Hypervisor/bare met= al */ switch (eaddr & R_EADDR_QUADRANT) { case R_EADDR_QUADRANT0: *lpid =3D 0; @@ -306,7 +306,7 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpi= d, ppc_v3_pate_t *pate) if (!(pate->dw0 & PATE0_HR)) { return false; } - if (lpid =3D=3D 0 && !msr_hv) { + if (lpid =3D=3D 0 && !FIELD_EX64(env->msr, MSR, HV)) { return false; } if ((pate->dw0 & PATE1_R_PRTS) < 5) { @@ -431,7 +431,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU = *cpu, *g_page_size =3D PRTBE_R_GET_RTS(prtbe0); base_addr =3D prtbe0 & PRTBE_R_RPDB; nls =3D prtbe0 & PRTBE_R_RPDS; - if (msr_hv || vhyp_flat_addressing(cpu)) { + if (FIELD_EX64(env->msr, MSR, HV) || vhyp_flat_addressing(cpu)) { /* * Can treat process table addresses as real addresses */ --=20 2.32.0