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[201.1.57.208]) by smtp.gmail.com with ESMTPSA id n67-20020aca4046000000b00325cda1ff94sm917146oia.19.2022.05.05.11.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hkvwi4o1Hq2eveuKw9kTx1VRbMCGplT1oknE4ER05us=; b=p/RwOhLnWJxgdeLt+rNY8B2cUKefVcAAzM+AEcdXZE921Aw4VY03OmZq6Bsek5nq4X a0l+uiCUVOUohhkbjZ8BWbO1lHYe63SNwTRpQZPXVKQiS1YH0U+qcBCixmNszuQaTYTV IWhia2D5ldrMkSu043gSWlfqfDIwbqh7Kg4LLBY4bfYUFxbXDrlXjHPk66vzSmUYKCX+ 3YXts2pFY/4t+SBIe05dkqzsZ1JBpAyJm1I8KqoIEA4qs9fBeN8++8pOOEk5xWnKbFce Cf/wtdEey1nqi8NH/s4L5tv+YmokcTfZ2Ko3aszJrqyIkVq9YZCTftGCBagpL/g0fLXQ y3BA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hkvwi4o1Hq2eveuKw9kTx1VRbMCGplT1oknE4ER05us=; b=70JPw424OESj//YEi9cPOZEs3TTxOJRw2rl57y8E5DepUbyNYvAJhKDVyc1A0N295M sfd8hM8LiSfiIUXP4rCM1iJkXDlBq0JVhD522Rt8EZKGQus90zEX+ZW/kugOknGLRzy9 pfkDB+KVeUbT6xsI/iuZMmcTNGWg8APVAjgca+M+M7RKSZgZ0D6Y1eUqhm9U9ebYfCdT uSSd/jtPjWVVmyf0xSn7ZgBPvFfnO3VJoodhTSdzcMj0xgBHPWJJDFsSYUqnhMAeW/4a SOLtRYATdrRv6MX3hg8xe0I0vKg03y3P8A1OgAbJgXt9cfqfLUcIBHkccPV5mt7v77Oo nitg== X-Gm-Message-State: AOAM5338Wbh0eol7VNHL4A8GgIVJmd3OhAMO1FPakAPKhEQfSSd3WwH2 MADYDiukiyc9xeQBT8i3CIDU9AmvNt8= X-Google-Smtp-Source: ABdhPJyvQKNGcIOBS2Ma5SwTIThDZnfq/HC020pMazx8AOTqN9ly3IY44/zZhetD9Hz+TazL7gKfJw== X-Received: by 2002:a05:6808:98f:b0:325:d44d:62d6 with SMTP id a15-20020a056808098f00b00325d44d62d6mr3110731oic.145.1651776640731; Thu, 05 May 2022 11:50:40 -0700 (PDT) From: Daniel Henrique Barboza To: qemu-devel@nongnu.org Cc: qemu-ppc@nongnu.org, danielhb413@gmail.com, peter.maydell@linaro.org, richard.henderson@linaro.org, =?UTF-8?q?V=C3=ADctor=20Colombo?= Subject: [PULL 11/30] target/ppc: Remove msr_pr macro Date: Thu, 5 May 2022 15:49:19 -0300 Message-Id: <20220505184938.351866-12-danielhb413@gmail.com> X-Mailer: git-send-email 2.32.0 In-Reply-To: <20220505184938.351866-1-danielhb413@gmail.com> References: <20220505184938.351866-1-danielhb413@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::22c; envelope-from=danielhb413@gmail.com; helo=mail-oi1-x22c.google.com X-Spam_score_int: -18 X-Spam_score: -1.9 X-Spam_bar: - X-Spam_report: (-1.9 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_ENVFROM_END_DIGIT=0.25, FREEMAIL_FROM=0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @gmail.com) X-ZM-MESSAGEID: 1651779813763100001 From: V=C3=ADctor Colombo msr_pr macro hides the usage of env->msr, which is a bad behavior Substitute it with FIELD_EX64 calls that explicitly use env->msr as a parameter. Suggested-by: Richard Henderson Signed-off-by: V=C3=ADctor Colombo Reviewed-by: Richard Henderson Message-Id: <20220504210541.115256-4-victor.colombo@eldorado.org.br> Signed-off-by: Daniel Henrique Barboza --- hw/ppc/pegasos2.c | 2 +- hw/ppc/spapr.c | 2 +- target/ppc/cpu.h | 4 +++- target/ppc/cpu_init.c | 4 ++-- target/ppc/excp_helper.c | 8 +++++--- target/ppc/mem_helper.c | 5 +++-- target/ppc/mmu-radix64.c | 5 +++-- target/ppc/mmu_common.c | 23 ++++++++++++----------- 8 files changed, 30 insertions(+), 23 deletions(-) diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 56bf203dfd..9411ca6b16 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -461,7 +461,7 @@ static void pegasos2_hypercall(PPCVirtualHypervisor *vh= yp, PowerPCCPU *cpu) /* The TCG path should also be holding the BQL at this point */ g_assert(qemu_mutex_iothread_locked()); =20 - if (msr_pr) { + if (FIELD_EX64(env->msr, MSR, PR)) { qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=3D1\n"= ); env->gpr[3] =3D H_PRIVILEGE; } else if (env->gpr[3] =3D=3D KVMPPC_H_RTAS) { diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 22569305d2..fe9937e811 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1269,7 +1269,7 @@ static void emulate_spapr_hypercall(PPCVirtualHypervi= sor *vhyp, =20 g_assert(!vhyp_cpu_in_nested(cpu)); =20 - if (msr_pr) { + if (FIELD_EX64(env->msr, MSR, PR)) { hcall_dprintf("Hypercall made with MSR[PR]=3D1\n"); env->gpr[3] =3D H_PRIVILEGE; } else { diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 112b456220..8f1dc4cb15 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -25,6 +25,7 @@ #include "exec/cpu-defs.h" #include "cpu-qom.h" #include "qom/object.h" +#include "hw/registerfields.h" =20 #define TCG_GUEST_DEFAULT_MO 0 =20 @@ -353,6 +354,8 @@ typedef enum { #define MSR_RI 1 /* Recoverable interrupt 1 = */ #define MSR_LE 0 /* Little-endian mode 1 hfla= gs */ =20 +FIELD(MSR, PR, MSR_PR, 1) + /* PMU bits */ #define MMCR0_FC PPC_BIT(32) /* Freeze Counters */ #define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */ @@ -474,7 +477,6 @@ typedef enum { #define msr_ce ((env->msr >> MSR_CE) & 1) #define msr_ile ((env->msr >> MSR_ILE) & 1) #define msr_ee ((env->msr >> MSR_EE) & 1) -#define msr_pr ((env->msr >> MSR_PR) & 1) #define msr_fp ((env->msr >> MSR_FP) & 1) #define msr_me ((env->msr >> MSR_ME) & 1) #define msr_fe0 ((env->msr >> MSR_FE0) & 1) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index d42e2ba8e0..ac16a64846 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -6303,7 +6303,7 @@ static bool cpu_has_work_POWER9(CPUState *cs) if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && (env->spr[SPR_LPCR] & LPCR_EEE)) { bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (heic =3D=3D 0 || !msr_hv || msr_pr) { + if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) { return true; } } @@ -6517,7 +6517,7 @@ static bool cpu_has_work_POWER10(CPUState *cs) if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) && (env->spr[SPR_LPCR] & LPCR_EEE)) { bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); - if (heic =3D=3D 0 || !msr_hv || msr_pr) { + if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) { return true; } } diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index d3e2cfcd71..7e8e34ef06 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1738,7 +1738,8 @@ static void ppc_hw_interrupt(CPUPPCState *env) bool lpes0 =3D !!(env->spr[SPR_LPCR] & LPCR_LPES0); bool heic =3D !!(env->spr[SPR_LPCR] & LPCR_HEIC); /* HEIC blocks delivery to the hypervisor */ - if ((async_deliver && !(heic && msr_hv && !msr_pr)) || + if ((async_deliver && !(heic && msr_hv && + !FIELD_EX64(env->msr, MSR, PR))) || (env->has_hv_mode && msr_hv =3D=3D 0 && !lpes0)) { if (books_vhyp_promotes_external_to_hvirt(cpu)) { powerpc_excp(cpu, POWERPC_EXCP_HVIRT); @@ -1818,7 +1819,8 @@ static void ppc_hw_interrupt(CPUPPCState *env) * EBB exception must be taken in problem state and * with BESCR_GE set. */ - if (msr_pr =3D=3D 1 && env->spr[SPR_BESCR] & BESCR_GE) { + if (FIELD_EX64(env->msr, MSR, PR) && + (env->spr[SPR_BESCR] & BESCR_GE)) { env->pending_interrupts &=3D ~(1 << PPC_INTERRUPT_EBB); =20 if (env->spr[SPR_BESCR] & BESCR_PMEO) { @@ -2094,7 +2096,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp) env->spr[SPR_BESCR] |=3D BESCR_EEO; } =20 - if (msr_pr =3D=3D 1) { + if (FIELD_EX64(env->msr, MSR, PR)) { powerpc_excp(cpu, ebb_excp); } else { env->pending_interrupts |=3D 1 << PPC_INTERRUPT_EBB; diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index c4ff8fd632..fba7f84b7a 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -613,10 +613,11 @@ void helper_tbegin(CPUPPCState *env) (1ULL << TEXASR_FAILURE_PERSISTENT) | (1ULL << TEXASR_NESTING_OVERFLOW) | (msr_hv << TEXASR_PRIVILEGE_HV) | - (msr_pr << TEXASR_PRIVILEGE_PR) | + (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) | (1ULL << TEXASR_FAILURE_SUMMARY) | (1ULL << TEXASR_TFIAR_EXACT); - env->spr[SPR_TFIAR] =3D env->nip | (msr_hv << 1) | msr_pr; + env->spr[SPR_TFIAR] =3D env->nip | (msr_hv << 1) | + FIELD_EX64(env->msr, MSR, PR); env->spr[SPR_TFHAR] =3D env->nip + 4; env->crf[0] =3D 0xB; /* 0b1010 =3D transaction failure */ } diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 5414fd63c1..e88f51fd34 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -191,12 +191,13 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, M= MUAccessType access_type, } =20 /* Determine permissions allowed by Encoded Access Authority */ - if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && msr_pr) { + if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && + FIELD_EX64(env->msr, MSR, PR)) { *prot =3D 0; } else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) || partition_scoped) { *prot =3D ppc_radix64_get_prot_eaa(pte); - } else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */ + } else { /* !MSR_PR && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */ *prot =3D ppc_radix64_get_prot_eaa(pte); *prot &=3D ppc_radix64_get_prot_amr(cpu); /* Least combined permis= sions */ } diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index e9c5b14c0f..6ef8b1c00d 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -273,8 +273,8 @@ static inline void bat_size_prot(CPUPPCState *env, targ= et_ulong *blp, bl =3D (*BATu & 0x00001FFC) << 15; valid =3D 0; prot =3D 0; - if (((msr_pr =3D=3D 0) && (*BATu & 0x00000002)) || - ((msr_pr !=3D 0) && (*BATu & 0x00000001))) { + if ((!FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000002)) || + (FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000001))) { valid =3D 1; pp =3D *BATl & 0x00000003; if (pp !=3D 0) { @@ -368,16 +368,17 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_= ctx_t *ctx, PowerPCCPU *cpu =3D env_archcpu(env); hwaddr hash; target_ulong vsid; - int ds, pr, target_page_bits; + int ds, target_page_bits; + bool pr; int ret; target_ulong sr, pgidx; =20 - pr =3D msr_pr; + pr =3D FIELD_EX64(env->msr, MSR, PR); ctx->eaddr =3D eaddr; =20 sr =3D env->sr[eaddr >> 28]; - ctx->key =3D (((sr & 0x20000000) && (pr !=3D 0)) || - ((sr & 0x40000000) && (pr =3D=3D 0))) ? 1 : 0; + ctx->key =3D (((sr & 0x20000000) && pr) || + ((sr & 0x40000000) && !pr)) ? 1 : 0; ds =3D sr & 0x80000000 ? 1 : 0; ctx->nx =3D sr & 0x10000000 ? 1 : 0; vsid =3D sr & 0x00FFFFFF; @@ -386,8 +387,8 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ct= x_t *ctx, "Check segment v=3D" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=3D" TARGET_FMT_lx " lr=3D" TARGET_FMT_lx " ir=3D%d dr=3D%d pr=3D%d %d t=3D%d\n", - eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)m= sr_ir, - (int)msr_dr, pr !=3D 0 ? 1 : 0, + eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, + (int)msr_ir, (int)msr_dr, pr ? 1 : 0, access_type =3D=3D MMU_DATA_STORE, type); pgidx =3D (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits; hash =3D vsid ^ pgidx; @@ -530,7 +531,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env= , mmu_ctx_t *ctx, =20 ret =3D -1; raddr =3D (hwaddr)-1ULL; - pr =3D msr_pr; + pr =3D FIELD_EX64(env->msr, MSR, PR); for (i =3D 0; i < env->nb_tlb; i++) { tlb =3D &env->tlb.tlbe[i]; if (ppcemb_tlb_check(env, tlb, &raddr, address, @@ -618,7 +619,7 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_= tlb_t *tlb, =20 found_tlb: =20 - if (msr_pr !=3D 0) { + if (FIELD_EX64(env->msr, MSR, PR)) { prot2 =3D tlb->prot & 0xF; } else { prot2 =3D (tlb->prot >> 4) & 0xF; @@ -768,7 +769,7 @@ static bool mmubooke206_get_as(CPUPPCState *env, return true; } else { *as_out =3D msr_ds; - *pr_out =3D msr_pr; + *pr_out =3D FIELD_EX64(env->msr, MSR, PR); return false; } } --=20 2.32.0