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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o35-20020a05600c512300b0039454a85a9asm2302121wms.30.2022.05.05.11.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BK37fHRVqnthuH26rW9Ll64hvEKI8MD8UM28AzmRwT8=; b=uJozRu9wwK26qd7XxlZ0LdjtatqxguT+TdkhMvjcTFb/DTMfuz43qRAJXkMYpgZIw1 LKl/XAxGESPvsUkma/fhnpJFT6vHuA/wYR0HCj353wmU61ZhULULDrRIhxhJsiqx+x7l hF6n/O9Tgv9AjmH8gQIGOKyA03myeD4j4CF047xjKPPc3j91wMgtvUBnndQ8Lur6pddw sA1zmQU3SsatS0XyvWfzmRC2JmJFfWCGDkiB7Gyo52RODXsucejRp4Ll3EkXAGL7RGkZ ru7VwTFjBtNluCDAicUSoKAi+TVJzyFKorWw1+5snw0XfSUADbjUdfAJiKVhrHgdx7WD PQCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BK37fHRVqnthuH26rW9Ll64hvEKI8MD8UM28AzmRwT8=; b=rnGoPKtRbY5f5DD5XA43u6ii4tFFeKOXE7m78T7eowXwdbNWYCxtrT/v4pTnmqGoXY k7XONHgmu7ZIfL/pjFecL44aRqGx9+3YoM86QFxSaAu8HVRoF+TMeVG3Lv3pGW1ma7Pn YRnzTDOGeR/txgaADPiOz1sgZlW+MMntIEjgC610ubLlCieRoXw9YgseNx4OPUEazzwP IAPmJCh3GBd4wB5BVtCbstl83pvwjlncIortWsJk1p5Tn1+f+oqjHrYZ1CYJ9p5zdgMw qEtI9KMiqyVk637DakxpvnCzODWT3qSM48RJ7C88M79V6Q3V2rDfyF6ZKZQzOcS5kqkY /5cw== X-Gm-Message-State: AOAM531HtFdEl7vUz2TSPL8uoLficOXKeBvAwGbmUlVJy8vmWVcS8lcx iL1FuXEbTLEyNp3mKbfP/PTI8ae1hfSg/A== X-Google-Smtp-Source: ABdhPJwUEk4DFKkWJVH3cAXjxc2zXbG28rrlwzFpkF8vmAuzfIzGWTBV3yuUpDgP+AZ1ebSFd8uKOQ== X-Received: by 2002:adf:f0c6:0:b0:20a:d31b:6 with SMTP id x6-20020adff0c6000000b0020ad31b0006mr22168714wro.162.1651775995094; Thu, 05 May 2022 11:39:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/4] target/arm: Implement FEAT_S2FWB Date: Thu, 5 May 2022 19:39:49 +0100 Message-Id: <20220505183950.2781801-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505183950.2781801-1-peter.maydell@linaro.org> References: <20220505183950.2781801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651777196137100001 Content-Type: text/plain; charset="utf-8" Implement the handling of FEAT_S2FWB; the meat of this is in the new combined_attrs_fwb() function which combines S1 and S2 attributes when HCR_EL2.FWB is set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 86 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index db8ff044497..dff0f634c38 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4289,6 +4289,11 @@ static inline bool isar_feature_aa64_st(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; } =20 +static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2828f0dacf3..fb8d2bf5c9d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5290,6 +5290,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_fwb, cpu)) { + valid_mask |=3D HCR_FWB; + } } =20 /* Clear RES0 bits. */ @@ -5301,8 +5304,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) * HCR_PTW forbids certain page-table setups * HCR_DC disables stage1 and enables stage2 translation * HCR_DCT enables tagging on (disabled) stage1 translation + * HCR_FWB changes the interpretation of stage2 descriptor bits */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT= )) { + if ((env->cp15.hcr_el2 ^ value) & + (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { tlb_flush(CPU(cpu)); } env->cp15.hcr_el2 =3D value; @@ -10685,9 +10690,15 @@ static bool ptw_attrs_are_device(CPUARMState *env,= ARMCacheAttrs cacheattrs) * attributes are therefore only Device if stage 2 specifies Device. * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] are 0b= 00, * ie when cacheattrs.attrs bits [3:2] are 0b00. + * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0, ie + * when cacheattrs.attrs bit [2] is 0. */ assert(cacheattrs.is_s2_format); - return (cacheattrs.attrs & 0xc) =3D=3D 0; + if (arm_hcr_el2_eff(env) & HCR_FWB) { + return (cacheattrs.attrs & 0x4) =3D=3D 0; + } else { + return (cacheattrs.attrs & 0xc) =3D=3D 0; + } } =20 /* Translate a S1 pagetable walk through S2 if needed. */ @@ -12572,6 +12583,69 @@ static uint8_t combined_attrs_nofwb(CPUARMState *e= nv, return ret_attrs; } =20 +static uint8_t force_cacheattr_nibble_wb(uint8_t attr) +{ + /* + * Given the 4 bits specifying the outer or inner cacheability + * in MAIR format, return a value specifying Normal Write-Back, + * with the allocation and transient hints taken from the input + * if the input specified some kind of cacheable attribute. + */ + if (attr =3D=3D 0 || attr =3D=3D 4) { + /* + * 0 =3D=3D an UNPREDICTABLE encoding + * 4 =3D=3D Non-cacheable + * Either way, force Write-Back RW allocate non-transient + */ + return 0xf; + } + /* Change WriteThrough to WriteBack, keep allocation and transient hin= ts */ + return attr | 4; +} + +/* + * Combine the memory type and cacheability attributes of + * s1 and s2 for the HCR_EL2.FWB =3D=3D 1 case, returning the + * combined attributes in MAIR_EL1 format. + */ +static uint8_t combined_attrs_fwb(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + switch (s2.attrs) { + case 7: + /* Use stage 1 attributes */ + return s1.attrs; + case 6: + /* + * Force Normal Write-Back. Note that if S1 is Normal cacheable + * then we take the allocation hints from it; otherwise it is + * RW allocate, non-transient. + */ + if ((s1.attrs & 0xf0) =3D=3D 0) { + /* S1 is Device */ + return 0xff; + } + /* Need to check the Inner and Outer nibbles separately */ + return force_cacheattr_nibble_wb(s1.attrs & 0xf) | + force_cacheattr_nibble_wb(s1.attrs >> 4) << 4; + case 5: + /* If S1 attrs are Device, use them; otherwise Normal Non-cacheabl= e */ + if ((s1.attrs & 0xf0) =3D=3D 0) { + return s1.attrs; + } + return 0x44; + case 0 ... 3: + /* Force Device, of subtype specified by S2 */ + return s2.attrs << 2; + default: + /* + * RESERVED values (including RES0 descriptor bit [5] being nonzer= o); + * arbitrarily force Device. + */ + return 0; + } +} + /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 * and CombineS1S2Desc() * @@ -12606,7 +12680,11 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMStat= e *env, } =20 /* Combine memory type and cacheability attributes */ - ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + if (arm_hcr_el2_eff(env) & HCR_FWB) { + ret.attrs =3D combined_attrs_fwb(env, s1, s2); + } else { + ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + } =20 /* * Any location for which the resultant memory type is any --=20 2.25.1