From nobody Mon Feb 9 10:52:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651776938; cv=none; d=zohomail.com; s=zohoarc; b=FLgs7/hyNXzY8ANKv7wG2+ZBR+8HMKV4qxp6yJQucsckpw0+j1WQ1nB//6GjXgcFU0Ol3rBuFS4mq4fEhwdy3shflDfPaGQGGI2e8BKpL6ylOUWNuOqCApHsV7mNgEV2ZFTSeN+jLJZCa1wmftB6iXZ4ngNJTb/p5X7X0kQTgeU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651776938; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zKpJXBcRLWde91wk5xHMHBvq9z9D+hxg14bTZbWAWx8=; b=AV+SHQzIpolPopTAU8a5A3ykW+e/w0f6995SbfDmigJ7zznQuoDzT+JlQp+wkbC7S5K6VzI5ijKEhxsoEDCWC46y2uVuCHrpLIJ5SebUOHWaZ5LjgoKyPpwfQwHMOKk3hLVBdG19uXd4FKvzl6WV5k0C6ke5f2xcQ1NR7kIr0BA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651776938751278.4073705355761; Thu, 5 May 2022 11:55:38 -0700 (PDT) Received: from localhost ([::1]:34652 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmgdV-0001qQ-Gx for importer@patchew.org; Thu, 05 May 2022 14:55:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43832) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmgOM-0006ws-Va for qemu-devel@nongnu.org; Thu, 05 May 2022 14:40:00 -0400 Received: from mail-wr1-x42d.google.com ([2a00:1450:4864:20::42d]:34472) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmgOI-0002AI-Tl for qemu-devel@nongnu.org; Thu, 05 May 2022 14:39:57 -0400 Received: by mail-wr1-x42d.google.com with SMTP id q23so7233522wra.1 for ; Thu, 05 May 2022 11:39:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o35-20020a05600c512300b0039454a85a9asm2302121wms.30.2022.05.05.11.39.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:39:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zKpJXBcRLWde91wk5xHMHBvq9z9D+hxg14bTZbWAWx8=; b=KOU8kxvcgOAHgInguxp5HPffsCaOkcLtQgzEwn7tEazl3AwhEfFM//HPx15zUj3Hir L8nDMnWKfJts7hELT0haXx3FDiNRz6GeqR2Trxmyf0iVjx11zAm8bJtgpxk+cfbW1pjd vFmFKRnRJTPuxsfoX4BqskRekggdXsILvXSFh2lI5UfiwJ2NOOarXvVlvKCjSSI+vcsX GVpACMCgGQJjCS2a7HfF5akFqYDaxkdIFo3BNvCgKOrBDTmjaihu4T/KeCOpcmYBMWVJ kyYcAseSgp7lcWIZtX8FaQn+TDgs7o7FEEnQOiA+417oDIL6ro8B3W5ylh/vi7P8tjiR tsNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zKpJXBcRLWde91wk5xHMHBvq9z9D+hxg14bTZbWAWx8=; b=H364Oxd+XryAlnkT3xhWp6szHhch0jemT8GFLamlcjvFGptDJO2F1qnS3oDt5F33SG ok2kyD9c+vpUTpfjIfA8AOGGWO8EteAsg5b1m/0/TqqjdD01zOApLnPV8+mt4p5ReE6X 898HnzQ8t3GGi7yeH7o0hrcaelD1AVeXD5KI+HEkClMRKSDMnurImsw0G3t5WQPTt4qO i4YlrZn+hRGVOBmbx8F39BATJYrxALlyTDdKr2McyizuR+L9fOz3TE5t20jR+S7RPWPP dwD5YnRYwcTQS2ISWOqo804C8PdUpr5MyU2uja4uvdZ3opcUe53EbObppPQIcPC45t+U hunA== X-Gm-Message-State: AOAM531slYrESpTaRswLBYwrjPJI53SZzlonM6J1VjYI2DzBuJjVsxGf SkuAST3EUciQvWMSWGHoQaDq4A== X-Google-Smtp-Source: ABdhPJwOOlB7V2e3xDJHSlJrjyT1zu4/RK1LpBvQ+JixsxiHMbRfdKC4hA18Qa0Kis/rrkDtpjFVeg== X-Received: by 2002:a5d:6102:0:b0:20a:db89:724f with SMTP id v2-20020a5d6102000000b0020adb89724fmr21580282wrt.59.1651775993113; Thu, 05 May 2022 11:39:53 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 1/4] target/arm: Postpone interpretation of stage 2 descriptor attribute bits Date: Thu, 5 May 2022 19:39:47 +0100 Message-Id: <20220505183950.2781801-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505183950.2781801-1-peter.maydell@linaro.org> References: <20220505183950.2781801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42d; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651776940918100001 Content-Type: text/plain; charset="utf-8" In the original Arm v8 two-stage translation, both stage 1 and stage 2 specify memory attributes (memory type, cacheability, shareability); these are then combined to produce the overall memory attributes for the whole stage 1+2 access. In QEMU we implement this by having get_phys_addr() fill in an ARMCacheAttrs struct, and we convert both the stage 1 and stage 2 attribute bit formats to the same encoding (an 8-bit attribute value matching the MAIR_EL1 fields, plus a 2-bit shareability value). The new FEAT_S2FWB feature allows the guest to enable a different interpretation of the attribute bits in the stage 2 descriptors. These bits can now be used to control details of how the stage 1 and 2 attributes should be combined (for instance they can say "always use the stage 1 attributes" or "ignore the stage 1 attributes and always be Device memory"). This means we need to pass the raw bit information for stage 2 down to the function which combines the stage 1 and stage 2 information. Add a field to ARMCacheAttrs that indicates whether the attrs field should be interpreted as MAIR format, or as the raw stage 2 attribute bits from the descriptor, and store the appropriate values when filling in cacheattrs. We only need to interpret the attrs field in a few places: * in do_ats_write(), where we know to expect a MAIR value (there is no ATS instruction to do a stage-2-only walk) * in S1_ptw_translate(), where we want to know whether the combined S1 + S2 attributes indicate Device memory that should provoke a fault * in combine_cacheattrs(), which does the S1 + S2 combining Update those places accordingly. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/internals.h | 7 ++++++- target/arm/helper.c | 42 ++++++++++++++++++++++++++++++++++++------ 2 files changed, 42 insertions(+), 7 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 255833479d4..b9dd093b5fb 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1141,8 +1141,13 @@ bool pmsav8_mpu_lookup(CPUARMState *env, uint32_t ad= dress, =20 /* Cacheability and shareability attributes for a memory access */ typedef struct ARMCacheAttrs { - unsigned int attrs:8; /* as in the MAIR register encoding */ + /* + * If is_s2_format is true, attrs is the S2 descriptor bits [5:2] + * Otherwise, attrs is the same as the MAIR_EL1 8-bit format + */ + unsigned int attrs:8; unsigned int shareability:2; /* as in the SH field of the VMSAv8-64 PT= Es */ + bool is_s2_format:1; } ARMCacheAttrs; =20 bool get_phys_addr(CPUARMState *env, target_ulong address, diff --git a/target/arm/helper.c b/target/arm/helper.c index 5a244c3ed93..5839acc343b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -3189,6 +3189,12 @@ static uint64_t do_ats_write(CPUARMState *env, uint6= 4_t value, ret =3D get_phys_addr(env, value, access_type, mmu_idx, &phys_addr, &a= ttrs, &prot, &page_size, &fi, &cacheattrs); =20 + /* + * ATS operations only do S1 or S1+S2 translations, so we never + * have to deal with the ARMCacheAttrs format for S2 only. + */ + assert(!cacheattrs.is_s2_format); + if (ret) { /* * Some kinds of translation fault must cause exceptions rather @@ -10671,6 +10677,19 @@ static bool get_level1_table_address(CPUARMState *= env, ARMMMUIdx mmu_idx, return true; } =20 +static bool ptw_attrs_are_device(CPUARMState *env, ARMCacheAttrs cacheattr= s) +{ + /* + * For an S1 page table walk, the stage 1 attributes are always + * some form of "this is Normal memory". The combined S1+S2 + * attributes are therefore only Device if stage 2 specifies Device. + * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] are 0b= 00, + * ie when cacheattrs.attrs bits [3:2] are 0b00. + */ + assert(cacheattrs.is_s2_format); + return (cacheattrs.attrs & 0xc) =3D=3D 0; +} + /* Translate a S1 pagetable walk through S2 if needed. */ static hwaddr S1_ptw_translate(CPUARMState *env, ARMMMUIdx mmu_idx, hwaddr addr, bool *is_secure, @@ -10699,7 +10718,7 @@ static hwaddr S1_ptw_translate(CPUARMState *env, AR= MMMUIdx mmu_idx, return ~0; } if ((arm_hcr_el2_eff(env) & HCR_PTW) && - (cacheattrs.attrs & 0xf0) =3D=3D 0) { + ptw_attrs_are_device(env, cacheattrs)) { /* * PTW set and S1 walk touched S2 Device memory: * generate Permission fault. @@ -11771,12 +11790,14 @@ static bool get_phys_addr_lpae(CPUARMState *env, = uint64_t address, } =20 if (mmu_idx =3D=3D ARMMMUIdx_Stage2 || mmu_idx =3D=3D ARMMMUIdx_Stage2= _S) { - cacheattrs->attrs =3D convert_stage2_attrs(env, extract32(attrs, 0= , 4)); + cacheattrs->is_s2_format =3D true; + cacheattrs->attrs =3D extract32(attrs, 0, 4); } else { /* Index into MAIR registers for cache attributes */ uint8_t attrindx =3D extract32(attrs, 0, 3); uint64_t mair =3D env->cp15.mair_el[regime_el(env, mmu_idx)]; assert(attrindx <=3D 7); + cacheattrs->is_s2_format =3D false; cacheattrs->attrs =3D extract64(mair, attrindx * 8, 8); } =20 @@ -12514,14 +12535,22 @@ static uint8_t combine_cacheattr_nibble(uint8_t s= 1, uint8_t s2) /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 * and CombineS1S2Desc() * + * @env: CPUARMState * @s1: Attributes from stage 1 walk * @s2: Attributes from stage 2 walk */ -static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2) +static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) { uint8_t s1lo, s2lo, s1hi, s2hi; ARMCacheAttrs ret; bool tagged =3D false; + uint8_t s2_mair_attrs; + + assert(s2.is_s2_format && !s1.is_s2_format); + ret.is_s2_format =3D false; + + s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); =20 if (s1.attrs =3D=3D 0xf0) { tagged =3D true; @@ -12529,9 +12558,9 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAtt= rs s1, ARMCacheAttrs s2) } =20 s1lo =3D extract32(s1.attrs, 0, 4); - s2lo =3D extract32(s2.attrs, 0, 4); + s2lo =3D extract32(s2_mair_attrs, 0, 4); s1hi =3D extract32(s1.attrs, 4, 4); - s2hi =3D extract32(s2.attrs, 4, 4); + s2hi =3D extract32(s2_mair_attrs, 4, 4); =20 /* Combine shareability attributes (table D4-43) */ if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { @@ -12685,7 +12714,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, } cacheattrs->shareability =3D 0; } - *cacheattrs =3D combine_cacheattrs(*cacheattrs, cacheattrs2); + *cacheattrs =3D combine_cacheattrs(env, *cacheattrs, cacheattr= s2); =20 /* Check if IPA translates to secure or non-secure PA space. */ if (arm_is_secure_below_el3(env)) { @@ -12803,6 +12832,7 @@ bool get_phys_addr(CPUARMState *env, target_ulong a= ddress, /* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */ hcr =3D arm_hcr_el2_eff(env); cacheattrs->shareability =3D 0; + cacheattrs->is_s2_format =3D false; if (hcr & HCR_DC) { if (hcr & HCR_DCT) { memattr =3D 0xf0; /* Tagged, Normal, WB, RWA */ --=20 2.25.1 From nobody Mon Feb 9 10:52:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651776753; cv=none; d=zohomail.com; s=zohoarc; b=IGLnbTRHhtEba+0XTwBteNJoN7jL5vNWAAhd+ANws6/2ZElkb7rqPxFEmZTy3/FqxSQeZSamIJsmLBo6PqdaOUmiAeXYD1TLkmMCXtMa2c8x0p56Avm/zkp5jFK+RKYwUyihs4rfzkRjN8CZ/geUREanj/RUmrgA0jNZMebYdLw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651776753; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o35-20020a05600c512300b0039454a85a9asm2302121wms.30.2022.05.05.11.39.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:39:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=uu7/TC5fWHfFvtIm4oJ7noZYbZtTrG6x0h1sDOIjlLo=; b=qI35xtAWKc5GgQS46g9oBirKR2BUffy1laCxXdrQ9z7+KHQxAe4g+jLgK9xNkDW2PD 6ca0EUINC31lKMR0o16mfhCsrn/T3NUqVPOOKmfDR48WkjdpSFFUD/C3OVnaAbB3YJ5k wF2x6XFjwohb6IY0iDfaZahBUjZdfDG6vmUzq1G68UpITPMch+H3AzAzjXs17hhWzRo9 fyuO7bC+6PCiTt72piC8QCujSRyGDAWwi3GQDRUbFb9CYbQhSdAVSL40AX6EIK4a8SGa djUP4mL/UOKTrF2pA1t0/ei3t1C9G79ZD1wsK90wKogIF76zKaS6z8amTx0rq60BNOCQ FJGg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=uu7/TC5fWHfFvtIm4oJ7noZYbZtTrG6x0h1sDOIjlLo=; b=NNMh3M7fkTtUR1VZK3XsFpHL2fUK5b/a/QJR18LTmUpWhEf1ojWNfUAYWjYpDEXshk WiFZVO5D0Afv+0fikqvlLqeMh35DNaDA5JCuF091JcDI0YR+JTMIHp49yAij8UhG6AOp huA49cjkKtBbsRwABE+NXcmWIL2W5LEMUSm8GcNoVkqFiy7lZCbOJmjJ+b5Rwr+zmQQT rhQIV4JYcFUm6OaLjLJAkPDIp9I3kjQP4unNefC+qm0+4V34RpLzi3a1r8QJAqOUTWNn 0LJnsw399MKrwORDXQ7a2GTM8Yq9FEeM6LxBhOA0nLIdiJrKm9hhPF8k8vm7y2wZu4/m 3LCQ== X-Gm-Message-State: AOAM532fKz4QG2yGY/Q3zIcW/UkRKgZBO1TzkE3ZWcQ5Pb8X9nnPK5ep 6aDLQN8ZbtBKP9Oo6aX83wHtkQ== X-Google-Smtp-Source: ABdhPJzR9BylEDwVQUZDHymXrmVn68FLaj5Dj8S0wikBOtfKguul1Q8638+lzAGDeaqAjN8GGDwD0A== X-Received: by 2002:a05:600c:2550:b0:393:fd17:a8d with SMTP id e16-20020a05600c255000b00393fd170a8dmr6301912wma.203.1651775994191; Thu, 05 May 2022 11:39:54 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 2/4] target/arm: Factor out FWB=0 specific part of combine_cacheattrs() Date: Thu, 5 May 2022 19:39:48 +0100 Message-Id: <20220505183950.2781801-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505183950.2781801-1-peter.maydell@linaro.org> References: <20220505183950.2781801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651776755540100001 Content-Type: text/plain; charset="utf-8" Factor out the part of combine_cacheattrs() that is specific to handling HCR_EL2.FWB =3D=3D 0. This is the part where we combine the memory type and cacheability attributes. The "force Outer Shareable for Device or Normal Inner-NC Outer-NC" logic remains in combine_cacheattrs() because it holds regardless (this is the equivalent of the pseudocode EffectiveShareability() function). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/helper.c | 88 +++++++++++++++++++++++++-------------------- 1 file changed, 50 insertions(+), 38 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 5839acc343b..2828f0dacf3 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -12532,6 +12532,46 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1= , uint8_t s2) } } =20 +/* + * Combine the memory type and cacheability attributes of + * s1 and s2 for the HCR_EL2.FWB =3D=3D 0 case, returning the + * combined attributes in MAIR_EL1 format. + */ +static uint8_t combined_attrs_nofwb(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + uint8_t s1lo, s2lo, s1hi, s2hi, s2_mair_attrs, ret_attrs; + + s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); + + s1lo =3D extract32(s1.attrs, 0, 4); + s2lo =3D extract32(s2_mair_attrs, 0, 4); + s1hi =3D extract32(s1.attrs, 4, 4); + s2hi =3D extract32(s2_mair_attrs, 4, 4); + + /* Combine memory type and cacheability attributes */ + if (s1hi =3D=3D 0 || s2hi =3D=3D 0) { + /* Device has precedence over normal */ + if (s1lo =3D=3D 0 || s2lo =3D=3D 0) { + /* nGnRnE has precedence over anything */ + ret_attrs =3D 0; + } else if (s1lo =3D=3D 4 || s2lo =3D=3D 4) { + /* non-Reordering has precedence over Reordering */ + ret_attrs =3D 4; /* nGnRE */ + } else if (s1lo =3D=3D 8 || s2lo =3D=3D 8) { + /* non-Gathering has precedence over Gathering */ + ret_attrs =3D 8; /* nGRE */ + } else { + ret_attrs =3D 0xc; /* GRE */ + } + } else { /* Normal memory */ + /* Outer/inner cacheability combine independently */ + ret_attrs =3D combine_cacheattr_nibble(s1hi, s2hi) << 4 + | combine_cacheattr_nibble(s1lo, s2lo); + } + return ret_attrs; +} + /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 * and CombineS1S2Desc() * @@ -12542,26 +12582,17 @@ static uint8_t combine_cacheattr_nibble(uint8_t s= 1, uint8_t s2) static ARMCacheAttrs combine_cacheattrs(CPUARMState *env, ARMCacheAttrs s1, ARMCacheAttrs s2) { - uint8_t s1lo, s2lo, s1hi, s2hi; ARMCacheAttrs ret; bool tagged =3D false; - uint8_t s2_mair_attrs; =20 assert(s2.is_s2_format && !s1.is_s2_format); ret.is_s2_format =3D false; =20 - s2_mair_attrs =3D convert_stage2_attrs(env, s2.attrs); - if (s1.attrs =3D=3D 0xf0) { tagged =3D true; s1.attrs =3D 0xff; } =20 - s1lo =3D extract32(s1.attrs, 0, 4); - s2lo =3D extract32(s2_mair_attrs, 0, 4); - s1hi =3D extract32(s1.attrs, 4, 4); - s2hi =3D extract32(s2_mair_attrs, 4, 4); - /* Combine shareability attributes (table D4-43) */ if (s1.shareability =3D=3D 2 || s2.shareability =3D=3D 2) { /* if either are outer-shareable, the result is outer-shareable */ @@ -12575,37 +12606,18 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMSta= te *env, } =20 /* Combine memory type and cacheability attributes */ - if (s1hi =3D=3D 0 || s2hi =3D=3D 0) { - /* Device has precedence over normal */ - if (s1lo =3D=3D 0 || s2lo =3D=3D 0) { - /* nGnRnE has precedence over anything */ - ret.attrs =3D 0; - } else if (s1lo =3D=3D 4 || s2lo =3D=3D 4) { - /* non-Reordering has precedence over Reordering */ - ret.attrs =3D 4; /* nGnRE */ - } else if (s1lo =3D=3D 8 || s2lo =3D=3D 8) { - /* non-Gathering has precedence over Gathering */ - ret.attrs =3D 8; /* nGRE */ - } else { - ret.attrs =3D 0xc; /* GRE */ - } + ret.attrs =3D combined_attrs_nofwb(env, s1, s2); =20 - /* Any location for which the resultant memory type is any - * type of Device memory is always treated as Outer Shareable. - */ + /* + * Any location for which the resultant memory type is any + * type of Device memory is always treated as Outer Shareable. + * Any location for which the resultant memory type is Normal + * Inner Non-cacheable, Outer Non-cacheable is always treated + * as Outer Shareable. + * TODO: FEAT_XS adds another value (0x40) also meaning iNCoNC + */ + if ((ret.attrs & 0xf0) =3D=3D 0 || ret.attrs =3D=3D 0x44) { ret.shareability =3D 2; - } else { /* Normal memory */ - /* Outer/inner cacheability combine independently */ - ret.attrs =3D combine_cacheattr_nibble(s1hi, s2hi) << 4 - | combine_cacheattr_nibble(s1lo, s2lo); - - if (ret.attrs =3D=3D 0x44) { - /* Any location for which the resultant memory type is Normal - * Inner Non-cacheable, Outer Non-cacheable is always treated - * as Outer Shareable. - */ - ret.shareability =3D 2; - } } =20 /* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */ --=20 2.25.1 From nobody Mon Feb 9 10:52:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651777195; cv=none; d=zohomail.com; s=zohoarc; b=dvcg7wAdBJymj3l0vpUh3E/y7jfy2D0d7UwjdzZmHlr0u1U9T2VyGrs+1OPMc4RWhBfqREWT1Q6shZW8WoKK3nEQJ+4GiCOGGdscr4FRC7Ufgn0Hwt2+kgI3VlwQa88BkNlnRCFSqJ1g8AvcI1bfAAslnWFaT/0pXWW9qDLr9Pg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651777195; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=BK37fHRVqnthuH26rW9Ll64hvEKI8MD8UM28AzmRwT8=; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o35-20020a05600c512300b0039454a85a9asm2302121wms.30.2022.05.05.11.39.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:39:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=BK37fHRVqnthuH26rW9Ll64hvEKI8MD8UM28AzmRwT8=; b=uJozRu9wwK26qd7XxlZ0LdjtatqxguT+TdkhMvjcTFb/DTMfuz43qRAJXkMYpgZIw1 LKl/XAxGESPvsUkma/fhnpJFT6vHuA/wYR0HCj353wmU61ZhULULDrRIhxhJsiqx+x7l hF6n/O9Tgv9AjmH8gQIGOKyA03myeD4j4CF047xjKPPc3j91wMgtvUBnndQ8Lur6pddw sA1zmQU3SsatS0XyvWfzmRC2JmJFfWCGDkiB7Gyo52RODXsucejRp4Ll3EkXAGL7RGkZ ru7VwTFjBtNluCDAicUSoKAi+TVJzyFKorWw1+5snw0XfSUADbjUdfAJiKVhrHgdx7WD PQCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=BK37fHRVqnthuH26rW9Ll64hvEKI8MD8UM28AzmRwT8=; b=rnGoPKtRbY5f5DD5XA43u6ii4tFFeKOXE7m78T7eowXwdbNWYCxtrT/v4pTnmqGoXY k7XONHgmu7ZIfL/pjFecL44aRqGx9+3YoM86QFxSaAu8HVRoF+TMeVG3Lv3pGW1ma7Pn YRnzTDOGeR/txgaADPiOz1sgZlW+MMntIEjgC610ubLlCieRoXw9YgseNx4OPUEazzwP IAPmJCh3GBd4wB5BVtCbstl83pvwjlncIortWsJk1p5Tn1+f+oqjHrYZ1CYJ9p5zdgMw qEtI9KMiqyVk637DakxpvnCzODWT3qSM48RJ7C88M79V6Q3V2rDfyF6ZKZQzOcS5kqkY /5cw== X-Gm-Message-State: AOAM531HtFdEl7vUz2TSPL8uoLficOXKeBvAwGbmUlVJy8vmWVcS8lcx iL1FuXEbTLEyNp3mKbfP/PTI8ae1hfSg/A== X-Google-Smtp-Source: ABdhPJwUEk4DFKkWJVH3cAXjxc2zXbG28rrlwzFpkF8vmAuzfIzGWTBV3yuUpDgP+AZ1ebSFd8uKOQ== X-Received: by 2002:adf:f0c6:0:b0:20a:d31b:6 with SMTP id x6-20020adff0c6000000b0020ad31b0006mr22168714wro.162.1651775995094; Thu, 05 May 2022 11:39:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 3/4] target/arm: Implement FEAT_S2FWB Date: Thu, 5 May 2022 19:39:49 +0100 Message-Id: <20220505183950.2781801-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505183950.2781801-1-peter.maydell@linaro.org> References: <20220505183950.2781801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651777196137100001 Content-Type: text/plain; charset="utf-8" Implement the handling of FEAT_S2FWB; the meat of this is in the new combined_attrs_fwb() function which combines S1 and S2 attributes when HCR_EL2.FWB is set. Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 86 insertions(+), 3 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index db8ff044497..dff0f634c38 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -4289,6 +4289,11 @@ static inline bool isar_feature_aa64_st(const ARMISA= Registers *id) return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, ST) !=3D 0; } =20 +static inline bool isar_feature_aa64_fwb(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64mmfr2, ID_AA64MMFR2, FWB) !=3D 0; +} + static inline bool isar_feature_aa64_bti(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, BT) !=3D 0; diff --git a/target/arm/helper.c b/target/arm/helper.c index 2828f0dacf3..fb8d2bf5c9d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5290,6 +5290,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_fwb, cpu)) { + valid_mask |=3D HCR_FWB; + } } =20 /* Clear RES0 bits. */ @@ -5301,8 +5304,10 @@ static void do_hcr_write(CPUARMState *env, uint64_t = value, uint64_t valid_mask) * HCR_PTW forbids certain page-table setups * HCR_DC disables stage1 and enables stage2 translation * HCR_DCT enables tagging on (disabled) stage1 translation + * HCR_FWB changes the interpretation of stage2 descriptor bits */ - if ((env->cp15.hcr_el2 ^ value) & (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT= )) { + if ((env->cp15.hcr_el2 ^ value) & + (HCR_VM | HCR_PTW | HCR_DC | HCR_DCT | HCR_FWB)) { tlb_flush(CPU(cpu)); } env->cp15.hcr_el2 =3D value; @@ -10685,9 +10690,15 @@ static bool ptw_attrs_are_device(CPUARMState *env,= ARMCacheAttrs cacheattrs) * attributes are therefore only Device if stage 2 specifies Device. * With HCR_EL2.FWB =3D=3D 0 this is when descriptor bits [5:4] are 0b= 00, * ie when cacheattrs.attrs bits [3:2] are 0b00. + * With HCR_EL2.FWB =3D=3D 1 this is when descriptor bit [4] is 0, ie + * when cacheattrs.attrs bit [2] is 0. */ assert(cacheattrs.is_s2_format); - return (cacheattrs.attrs & 0xc) =3D=3D 0; + if (arm_hcr_el2_eff(env) & HCR_FWB) { + return (cacheattrs.attrs & 0x4) =3D=3D 0; + } else { + return (cacheattrs.attrs & 0xc) =3D=3D 0; + } } =20 /* Translate a S1 pagetable walk through S2 if needed. */ @@ -12572,6 +12583,69 @@ static uint8_t combined_attrs_nofwb(CPUARMState *e= nv, return ret_attrs; } =20 +static uint8_t force_cacheattr_nibble_wb(uint8_t attr) +{ + /* + * Given the 4 bits specifying the outer or inner cacheability + * in MAIR format, return a value specifying Normal Write-Back, + * with the allocation and transient hints taken from the input + * if the input specified some kind of cacheable attribute. + */ + if (attr =3D=3D 0 || attr =3D=3D 4) { + /* + * 0 =3D=3D an UNPREDICTABLE encoding + * 4 =3D=3D Non-cacheable + * Either way, force Write-Back RW allocate non-transient + */ + return 0xf; + } + /* Change WriteThrough to WriteBack, keep allocation and transient hin= ts */ + return attr | 4; +} + +/* + * Combine the memory type and cacheability attributes of + * s1 and s2 for the HCR_EL2.FWB =3D=3D 1 case, returning the + * combined attributes in MAIR_EL1 format. + */ +static uint8_t combined_attrs_fwb(CPUARMState *env, + ARMCacheAttrs s1, ARMCacheAttrs s2) +{ + switch (s2.attrs) { + case 7: + /* Use stage 1 attributes */ + return s1.attrs; + case 6: + /* + * Force Normal Write-Back. Note that if S1 is Normal cacheable + * then we take the allocation hints from it; otherwise it is + * RW allocate, non-transient. + */ + if ((s1.attrs & 0xf0) =3D=3D 0) { + /* S1 is Device */ + return 0xff; + } + /* Need to check the Inner and Outer nibbles separately */ + return force_cacheattr_nibble_wb(s1.attrs & 0xf) | + force_cacheattr_nibble_wb(s1.attrs >> 4) << 4; + case 5: + /* If S1 attrs are Device, use them; otherwise Normal Non-cacheabl= e */ + if ((s1.attrs & 0xf0) =3D=3D 0) { + return s1.attrs; + } + return 0x44; + case 0 ... 3: + /* Force Device, of subtype specified by S2 */ + return s2.attrs << 2; + default: + /* + * RESERVED values (including RES0 descriptor bit [5] being nonzer= o); + * arbitrarily force Device. + */ + return 0; + } +} + /* Combine S1 and S2 cacheability/shareability attributes, per D4.5.4 * and CombineS1S2Desc() * @@ -12606,7 +12680,11 @@ static ARMCacheAttrs combine_cacheattrs(CPUARMStat= e *env, } =20 /* Combine memory type and cacheability attributes */ - ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + if (arm_hcr_el2_eff(env) & HCR_FWB) { + ret.attrs =3D combined_attrs_fwb(env, s1, s2); + } else { + ret.attrs =3D combined_attrs_nofwb(env, s1, s2); + } =20 /* * Any location for which the resultant memory type is any --=20 2.25.1 From nobody Mon Feb 9 10:52:41 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651776279; cv=none; d=zohomail.com; s=zohoarc; b=JnNxpDktdlPyqCDvTkCt5J14G2363fB8wp5Im2DthcL2cyZKa3na3n7MamM9aeSNSMHa7mcOUOg2ovsdIq7IVaaj+JfKFT3ZVi6/M0Sa1U7QOCApxd4+QIRzer664P432GnIBKVQ2CpGfm3wAkNtwNM2wixjfmik3aHhbJizEz0= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651776279; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=ZrbOgyRHel1WsxZxJsJlMGVG2H1MqvD6A/WHr3xS78s=; b=J0SRJlXcKZ2QUWUrPA0CxNBJPw2EyMF9TusLfUfXZPtgDTgrF8+KtmoY+ONT06/1pWXvDRKvSlyyL9mm4FsCjANt4IppoMdYhWUGlKWJ8IihBDvOOyNrCNaY+yOcrxsTleyBWYzj1BARgsNKLEYI79soS17YP+d3MEZ30XhSLVo= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651776279868611.6981500655189; Thu, 5 May 2022 11:44:39 -0700 (PDT) Received: from localhost ([::1]:38998 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmgSs-0001bq-E6 for importer@patchew.org; Thu, 05 May 2022 14:44:38 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43878) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmgOO-0006xj-RQ for qemu-devel@nongnu.org; Thu, 05 May 2022 14:40:04 -0400 Received: from mail-wm1-x333.google.com ([2a00:1450:4864:20::333]:42605) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmgOM-0002Ar-JW for qemu-devel@nongnu.org; Thu, 05 May 2022 14:39:59 -0400 Received: by mail-wm1-x333.google.com with SMTP id n126-20020a1c2784000000b0038e8af3e788so3148651wmn.1 for ; Thu, 05 May 2022 11:39:56 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id o35-20020a05600c512300b0039454a85a9asm2302121wms.30.2022.05.05.11.39.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 11:39:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ZrbOgyRHel1WsxZxJsJlMGVG2H1MqvD6A/WHr3xS78s=; b=TWEI4nTaN5hI01MIGwiFetwiVQ7upWwssaLsscSkrX71I7jJ++xd5NTetcl8stTZOZ ptje5NLs+rG1i0ZhZoWyuvQSeKbBrqKtlpRx+xxx0WIN7Z8ZtX3Vs/8MO7Jbo5UwxC4r 029OgDPSiaIVRI9QJhIHH9ZQCMKVcYSptzms1vyJM0Bi5R8UdaLzpEQ2xvEiaPyak0WS M0VTlNsYeQwFKj5YKDjDW5TGnfQC/MGcA9zsMHc8PEDzRZJlM3joeDDXspkA00qFTAj7 naCNe1y7LOcjmfcmfDRAQRrs21xP2SFcSHQekD2gzO4iqHD0jb8jORI55hgy7KMK5lT0 1kzA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ZrbOgyRHel1WsxZxJsJlMGVG2H1MqvD6A/WHr3xS78s=; b=TgvEICrcfAXOcL2wH9/qrLxw/xdD5fG14cW7w8yF0NVkSW8IoY7kt8fcf/2Ke5UnqO g+Mj+qNFHCIQo11Jfspj/oY49FhhMq2g35bP1JIJB2S+Ct3AVhnPisJR+6+vCplbmP2i RX32DB6FqdzIbrEuHntAJF7MDC4/QrqB/B9YEjd6wBhM+mvqc15cYyUS2les5zicCP6/ zk0Z0+SCn5L87g3Jckn9fdP9tDT94Juv1yX7p8m7u0Y58Ol91OopR5Mbt+roUGzklxCb gYMNaC4uDYgvc/JAGKvn88CQ2JqOhurQgTsurIFB37FwyNfA+QcJU0xL+2bKIlxlenbV q2eQ== X-Gm-Message-State: AOAM530eRgKt53yNqzhwxc1tKKTk8PlaQLihmg08W4i5LeNfHfPoDm3U uWfoNLq0iGtSPiiKOpRc2ssC3A== X-Google-Smtp-Source: ABdhPJxrAYHDTD71Jc3T7XhEeItpGJgpKP1K6mwtoMtEAPiC0dXIdSm4GcdX2hyzPpTBfqq3vh1IAg== X-Received: by 2002:a05:600c:3391:b0:393:fbba:3789 with SMTP id o17-20020a05600c339100b00393fbba3789mr6320440wmp.206.1651775995887; Thu, 05 May 2022 11:39:55 -0700 (PDT) From: Peter Maydell To: qemu-arm@nongnu.org, qemu-devel@nongnu.org Subject: [PATCH 4/4] target/arm: Enable FEAT_S2FWB for -cpu max Date: Thu, 5 May 2022 19:39:50 +0100 Message-Id: <20220505183950.2781801-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505183950.2781801-1-peter.maydell@linaro.org> References: <20220505183950.2781801-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::333; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x333.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651776280664100001 Content-Type: text/plain; charset="utf-8" Enable the FEAT_S2FWB for -cpu max. Since FEAT_S2FWB requires that CLIDR_EL1.{LoUU,LoUIS} are zero, we explicitly squash these (the inherited CLIDR_EL1 value from the Cortex-A57 has them as 1). Signed-off-by: Peter Maydell Reviewed-by: Richard Henderson --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 10 ++++++++++ 2 files changed, 11 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index c3bd0676a87..122306a99f1 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -42,6 +42,7 @@ the following architecture extensions: - FEAT_PMUv3p4 (PMU Extensions v3.4) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) +- FEAT_S2FWB (Stage 2 forced Write-Back) - FEAT_SB (Speculation Barrier) - FEAT_SEL2 (Secure EL2) - FEAT_SHA1 (SHA1 instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2974cbc0d35..ed2831f1f38 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -769,6 +769,15 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, MIDR_EL1, REVISION, 0); cpu->midr =3D t; =20 + /* + * We're going to set FEAT_S2FWB, which mandates that CLIDR_EL1.{LoUU,= LoUIS} + * are zero. + */ + u =3D cpu->clidr; + u =3D FIELD_DP32(u, CLIDR_EL1, LOUIS, 0); + u =3D FIELD_DP32(u, CLIDR_EL1, LOUU, 0); + cpu->clidr =3D u; + t =3D cpu->isar.id_aa64isar0; t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); @@ -841,6 +850,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, FWB, 1); /* FEAT_S2FWB */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; --=20 2.25.1