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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 08/23] target/arm: Change cpreg access permissions to enum
Date: Thu, 5 May 2022 10:11:32 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Create a typedef as well, and use it in ARMCPRegInfo.
This won't be perfect for debugging, but it'll nicely
display the most common cases.
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-8-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 44 +++++++++++++++++++++++---------------------
target/arm/helper.c | 2 +-
2 files changed, 24 insertions(+), 22 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index ff3817decbd..858c5da57d8 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -154,31 +154,33 @@ enum {
* described with these bits, then use a laxer set of restrictions, and
* do the more restrictive/complex check inside a helper function.
*/
-#define PL3_R 0x80
-#define PL3_W 0x40
-#define PL2_R (0x20 | PL3_R)
-#define PL2_W (0x10 | PL3_W)
-#define PL1_R (0x08 | PL2_R)
-#define PL1_W (0x04 | PL2_W)
-#define PL0_R (0x02 | PL1_R)
-#define PL0_W (0x01 | PL1_W)
+typedef enum {
+ PL3_R =3D 0x80,
+ PL3_W =3D 0x40,
+ PL2_R =3D 0x20 | PL3_R,
+ PL2_W =3D 0x10 | PL3_W,
+ PL1_R =3D 0x08 | PL2_R,
+ PL1_W =3D 0x04 | PL2_W,
+ PL0_R =3D 0x02 | PL1_R,
+ PL0_W =3D 0x01 | PL1_W,
=20
-/*
- * For user-mode some registers are accessible to EL0 via a kernel
- * trap-and-emulate ABI. In this case we define the read permissions
- * as actually being PL0_R. However some bits of any given register
- * may still be masked.
- */
+ /*
+ * For user-mode some registers are accessible to EL0 via a kernel
+ * trap-and-emulate ABI. In this case we define the read permissions
+ * as actually being PL0_R. However some bits of any given register
+ * may still be masked.
+ */
#ifdef CONFIG_USER_ONLY
-#define PL0U_R PL0_R
+ PL0U_R =3D PL0_R,
#else
-#define PL0U_R PL1_R
+ PL0U_R =3D PL1_R,
#endif
=20
-#define PL3_RW (PL3_R | PL3_W)
-#define PL2_RW (PL2_R | PL2_W)
-#define PL1_RW (PL1_R | PL1_W)
-#define PL0_RW (PL0_R | PL0_W)
+ PL3_RW =3D PL3_R | PL3_W,
+ PL2_RW =3D PL2_R | PL2_W,
+ PL1_RW =3D PL1_R | PL1_W,
+ PL0_RW =3D PL0_R | PL0_W,
+} CPAccessRights;
=20
typedef enum CPAccessResult {
/* Access is permitted */
@@ -262,7 +264,7 @@ struct ARMCPRegInfo {
/* Register type: ARM_CP_* bits/values */
int type;
/* Access rights: PL*_[RW] */
- int access;
+ CPAccessRights access;
/* Security state: ARM_CP_SECSTATE_* bits/values */
int secure;
/*
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 06f8864c778..a19e04bb0bf 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8711,7 +8711,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* to encompass the generic architectural permission check.
*/
if (r->state !=3D ARM_CP_STATE_AA32) {
- int mask =3D 0;
+ CPAccessRights mask;
switch (r->opc1) {
case 0:
/* min_EL EL1, but some accessible to EL0 via kernel ABI */
--=20
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