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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 23/23] target/arm: read access to performance counters from EL0
Date: Thu, 5 May 2022 10:11:47 +0100
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From: Alex Zuepke <alex.zuepke@tum.de>
The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access
to both PMXEVCNTR_EL0 and PMEVCNTR<n>_EL0 registers, however,
we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR<n>_EL0 as well.
Signed-off-by: Alex Zuepke <alex.zuepke@tum.de>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220428132717.84190-1-alex.zuepke@tum.de
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 14ea5caad94..b4daf4f0761 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -6639,10 +6639,10 @@ static void define_pmu_regs(ARMCPU *cpu)
.crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7,
.access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS,
.readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn,
- .accessfn =3D pmreg_access },
+ .accessfn =3D pmreg_access_xevcntr },
{ .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64,
.opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i =
>> 3)),
- .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc=
ess,
+ .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc=
ess_xevcntr,
.type =3D ARM_CP_IO,
.readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn,
.raw_readfn =3D pmevcntr_rawread,
--=20
2.25.1