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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 14/23] target/arm: Hoist computation of key in
add_cpreg_to_hashtable
Date: Thu, 5 May 2022 10:11:38 +0100
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From: Richard Henderson <richard.henderson@linaro.org>
Move the computation of key to the top of the function.
Hoist the resolution of cp as well, as an input to the
computation of key.
This will be required by a subsequent patch.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-id: 20220501055028.646596-14-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/helper.c | 49 +++++++++++++++++++++++++--------------------
1 file changed, 27 insertions(+), 22 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index d92fd23445b..cbc873e3e60 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8509,8 +8509,34 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons=
t ARMCPRegInfo *r,
ARMCPRegInfo *r2;
int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0;
int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0;
+ int cp =3D r->cp;
size_t name_len;
=20
+ switch (state) {
+ case ARM_CP_STATE_AA32:
+ /* We assume it is a cp15 register if the .cp field is left unset.=
*/
+ if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) {
+ cp =3D 15;
+ }
+ key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2);
+ break;
+ case ARM_CP_STATE_AA64:
+ /*
+ * To allow abbreviation of ARMCPRegInfo definitions, we treat
+ * cp =3D=3D 0 as equivalent to the value for "standard guest-visi=
ble
+ * sysreg". STATE_BOTH definitions are also always "standard sysr=
eg"
+ * in their AArch64 view (the .cp value may be non-zero for the
+ * benefit of the AArch32 view).
+ */
+ if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) {
+ cp =3D CP_REG_ARM64_SYSREG_CP;
+ }
+ key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2);
+ break;
+ default:
+ g_assert_not_reached();
+ }
+
/* Combine cpreg and name into one allocation. */
name_len =3D strlen(name) + 1;
r2 =3D g_malloc(sizeof(*r2) + name_len);
@@ -8554,12 +8580,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons=
t ARMCPRegInfo *r,
}
=20
if (r->state =3D=3D ARM_CP_STATE_BOTH) {
- /* We assume it is a cp15 register if the .cp field is left un=
set.
- */
- if (r2->cp =3D=3D 0) {
- r2->cp =3D 15;
- }
-
#if HOST_BIG_ENDIAN
if (r2->fieldoffset) {
r2->fieldoffset +=3D sizeof(uint32_t);
@@ -8567,22 +8587,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons=
t ARMCPRegInfo *r,
#endif
}
}
- if (state =3D=3D ARM_CP_STATE_AA64) {
- /* To allow abbreviation of ARMCPRegInfo
- * definitions, we treat cp =3D=3D 0 as equivalent to
- * the value for "standard guest-visible sysreg".
- * STATE_BOTH definitions are also always "standard
- * sysreg" in their AArch64 view (the .cp value may
- * be non-zero for the benefit of the AArch32 view).
- */
- if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) {
- r2->cp =3D CP_REG_ARM64_SYSREG_CP;
- }
- key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
- r2->opc0, opc1, opc2);
- } else {
- key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2);
- }
if (opaque) {
r2->opaque =3D opaque;
}
@@ -8593,6 +8597,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const=
ARMCPRegInfo *r,
/* Make sure reginfo passed to helpers for wildcarded regs
* has the correct crm/opc1/opc2 for this reg, not CP_ANY:
*/
+ r2->cp =3D cp;
r2->crm =3D crm;
r2->opc1 =3D opc1;
r2->opc2 =3D opc2;
--=20
2.25.1