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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 09/23] target/arm: Name CPState type
Date: Thu, 5 May 2022 10:11:33 +0100
Message-Id: <20220505091147.2657652-10-peter.maydell@linaro.org>
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From: Richard Henderson <richard.henderson@linaro.org>
Give this enum a name and use in ARMCPRegInfo,
add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque.
Reviewed-by: Alex Benn=C3=A9e <alex.bennee@linaro.org>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220501055028.646596-9-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs.h | 6 +++---
target/arm/helper.c | 6 ++++--
2 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h
index 858c5da57d8..4179a8cdd5a 100644
--- a/target/arm/cpregs.h
+++ b/target/arm/cpregs.h
@@ -114,11 +114,11 @@ enum {
* Note that we rely on the values of these enums as we iterate through
* the various states in some places.
*/
-enum {
+typedef enum {
ARM_CP_STATE_AA32 =3D 0,
ARM_CP_STATE_AA64 =3D 1,
ARM_CP_STATE_BOTH =3D 2,
-};
+} CPState;
=20
/*
* ARM CP register secure state flags. These flags identify security state
@@ -260,7 +260,7 @@ struct ARMCPRegInfo {
uint8_t opc1;
uint8_t opc2;
/* Execution state in which this register is visible: ARM_CP_STATE_* */
- int state;
+ CPState state;
/* Register type: ARM_CP_* bits/values */
int type;
/* Access rights: PL*_[RW] */
diff --git a/target/arm/helper.c b/target/arm/helper.c
index a19e04bb0bf..d560a6a6a92 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -8502,7 +8502,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro=
r **errp)
}
=20
static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
- void *opaque, int state, int secstate,
+ void *opaque, CPState state, int secsta=
te,
int crm, int opc1, int opc2,
const char *name)
{
@@ -8662,13 +8662,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
* bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
* the register, if any.
*/
- int crm, opc1, opc2, state;
+ int crm, opc1, opc2;
int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm;
int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm;
int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1;
int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1;
int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2;
int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2;
+ CPState state;
+
/* 64 bit registers have only CRm and Opc1 fields */
assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
/* op0 only exists in the AArch64 encodings */
--=20
2.25.1