From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651742255; cv=none; d=zohomail.com; s=zohoarc; b=A+SSGLCyEHZoiVybv80QmHEXdbRedlcm1P/MLAVFex6tUiTxNEYrnaK00zNRDgM52MjCD2cDwZtJ7SeBghMOCGjSNtN0UUyORaDi4oujuS6Z9o7SipcAphTunJDnlvyzkY/toiYIhD9V0WoACuAAZUK7wsEPAkTmkOUsaBhS1Yg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651742255; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qfuC15wVhgbtf/sFl4PEa+tcmWHsuyafqPjoww1w/hI=; b=ZUy6z3wwGRfgoDyJXMJGI51lmXu7IV1EAiHFK6msnNzut/Sk+m3OCTCGqE76d4nvfY1pGvumheqtl1kfq7c3SmSgaY79jfMnjgCTYZeRn7UP0msONlReQkIXVsc00S+js6bptv/y5/4bhAKBYU6Lnzb3Ww6xrNhEbe5bT9Z62gI= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651742255592770.7290245513506; Thu, 5 May 2022 02:17:35 -0700 (PDT) Received: from localhost ([::1]:33740 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmXc2-0003BU-Vo for importer@patchew.org; Thu, 05 May 2022 05:17:32 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38440) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWc-0004nD-U5 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:11:54 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:44699) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWa-00039c-7Z for qemu-devel@nongnu.org; Thu, 05 May 2022 05:11:54 -0400 Received: by mail-wr1-x42c.google.com with SMTP id b19so5210540wrh.11 for ; Thu, 05 May 2022 02:11:51 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.49 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=qfuC15wVhgbtf/sFl4PEa+tcmWHsuyafqPjoww1w/hI=; b=dVV/E+RuyBmbbozQCgqG39EvJV5ONedx5ZNcjcYqt1bu6pEXRzWzwcb5iAZin8KuNz zGTyj8GjHdzQ9z39ESlBP7QGKZe/D93O7aZokGkE7BfRdYAEu32RDnVpCg9aZDqFI9cM Ww4/+Y1DqXvrfBQZz+4CAX3iD4tGYg6zCLQp4SPWNJ+znFMj6wsBIRdxTYDa/8pm3001 94pD3T37VtL7tph0mcPs5RZMBkE/Fm1ZpEzc0ShC2v/tNMXaiqNKaak8/bV7rrzepQqP 54qYbud/cf6uVUaCjWOfd5fzfBNJnO5Sh9wLCz+36hlrPJmaehVjtv8xWEBbgqaqRFnX 7K3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qfuC15wVhgbtf/sFl4PEa+tcmWHsuyafqPjoww1w/hI=; b=t0iD/yGMDd0i3KNVex36oGNSAQfbKdZc19bJOAW5otZhJ+sIpHZTn2ig3d+xTGjrpD w7CtopteDS8uxA4151zx+GAZqsowDKHAkFccN+MKDY/MEm3VNo3lJllifB4c1HgqFRv9 JSbL8h11EvKTrTBOjqSRmuXdjwbt6ySBmuQqtRH86dDcaX0lQRVx+sbfntCW4mWhiQv9 wXjyVZYkK9p0ggoeLHBq3rxoPEJte6QlHKMtAmUYXpJezO3w/OgO/ZYc4z+YAMEaGp9N uRrILrEc+sZV85xVOPOonLSyoARUFyvwNQlSQ9PCdmrVh/mTyWwhiggA0ZLBgZdGqrSk 57bA== X-Gm-Message-State: AOAM5338WNSwugxp6bKPVSPt3uOPCsUrNkhiiadf+ZWsZ76C4Onshp9f yiCpHLESQI+XPWPDfQn0EtLrBA64Fewf7w== X-Google-Smtp-Source: ABdhPJy0aoHLOgEIOrxcA4PcgTcjuOCXvGEZlwQJepRL9b7ejgUDAgMhV7Mokxrad7UcilzghaQNbA== X-Received: by 2002:a5d:4ac2:0:b0:20c:7844:fb79 with SMTP id y2-20020a5d4ac2000000b0020c7844fb79mr8647245wrs.33.1651741910669; Thu, 05 May 2022 02:11:50 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 01/23] target/arm: Enable SCTLR_EL1.BT0 for aarch64-linux-user Date: Thu, 5 May 2022 10:11:25 +0100 Message-Id: <20220505091147.2657652-2-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651742257027100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson This controls whether the PACI{A,B}SP instructions trap with BTYPE=3D3 (indirect branch from register other than x16/x17). The linux kernel sets this in bti_enable(). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/998 Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220427042312.294300-1-richard.henderson@linaro.org [PMM: remove stray change to makefile comment] Signed-off-by: Peter Maydell --- target/arm/cpu.c | 2 ++ tests/tcg/aarch64/bti-3.c | 42 +++++++++++++++++++++++++++++++ tests/tcg/aarch64/Makefile.target | 6 ++--- 3 files changed, 47 insertions(+), 3 deletions(-) create mode 100644 tests/tcg/aarch64/bti-3.c diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e46a766d770..2b81b18351a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -197,6 +197,8 @@ static void arm_cpu_reset(DeviceState *dev) /* Enable all PAC keys. */ env->cp15.sctlr_el[1] |=3D (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB); + /* Trap on btype=3D3 for PACIxSP. */ + env->cp15.sctlr_el[1] |=3D SCTLR_BT0; /* and to the FP/Neon instructions */ env->cp15.cpacr_el1 =3D deposit64(env->cp15.cpacr_el1, 20, 2, 3); /* and to the SVE instructions */ diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c new file mode 100644 index 00000000000..a852856d9a6 --- /dev/null +++ b/tests/tcg/aarch64/bti-3.c @@ -0,0 +1,42 @@ +/* + * BTI vs PACIASP + */ + +#include "bti-crt.inc.c" + +static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) +{ + uc->uc_mcontext.pc +=3D 8; + uc->uc_mcontext.pstate =3D 1; +} + +#define BTYPE_1() \ + asm("mov %0,#1; adr x16, 1f; br x16; 1: hint #25; mov %0,#0" \ + : "=3Dr"(skipped) : : "x16", "x30") + +#define BTYPE_2() \ + asm("mov %0,#1; adr x16, 1f; blr x16; 1: hint #25; mov %0,#0" \ + : "=3Dr"(skipped) : : "x16", "x30") + +#define BTYPE_3() \ + asm("mov %0,#1; adr x15, 1f; br x15; 1: hint #25; mov %0,#0" \ + : "=3Dr"(skipped) : : "x15", "x30") + +#define TEST(WHICH, EXPECT) \ + do { WHICH(); fail +=3D skipped ^ EXPECT; } while (0) + +int main() +{ + int fail =3D 0; + int skipped; + + /* Signal-like with SA_SIGINFO. */ + signal_info(SIGILL, skip2_sigill); + + /* With SCTLR_EL1.BT0 set, PACIASP is not compatible with type=3D3. */ + TEST(BTYPE_1, 0); + TEST(BTYPE_2, 0); + TEST(BTYPE_3, 1); + + return fail; +} diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile= .target index 6ad0ad49f98..d6a74d24dc0 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -28,9 +28,9 @@ endif # BTI Tests # bti-1 tests the elf notes, so we require special compiler support. ifneq ($(CROSS_CC_HAS_ARMV8_BTI),) -AARCH64_TESTS +=3D bti-1 -bti-1: CFLAGS +=3D -mbranch-protection=3Dstandard -bti-1: LDFLAGS +=3D -nostdlib +AARCH64_TESTS +=3D bti-1 bti-3 +bti-1 bti-3: CFLAGS +=3D -mbranch-protection=3Dstandard +bti-1 bti-3: LDFLAGS +=3D -nostdlib endif # bti-2 tests PROT_BTI, so no special compiler support required. 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.50 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=+7kIMctbvkf3Y5fE9yh7QgOjRPJgfV8X9/UfVbLmNnY=; b=VKiJL6H653QgYWTYFG0xS6f1ZbqAxk3mxiYgEzcfkpnOop1Ft5DHN2ef0dNN6U6xWb 5Hv+uhR1SfnxCYIMQAsGiM6zDYknXaFlJSBZQ3SxCwJ8QJiyFVn7qSbYXKNqVHL9Wc4e dWr7AoZuWVuQTTgUu3wrPC4B2SxTx8tnLouM6B847vDGbzDOhlLZ/uYOeF0MmnYtP9YL Z3zXAn0UcWJSl377uP921jmqwX3uLoFG1Ozd2zcraWdZgSGMxOruAsuOI7SbMqzQIh/u 2YjFjxFY703hmdztlksJmU2Rt34jfr5TF301WqiZUheYlQiMa4AG7kOjH63owE9OVEN5 0Q/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=+7kIMctbvkf3Y5fE9yh7QgOjRPJgfV8X9/UfVbLmNnY=; b=R7Frk9LNHU5y9FtQcof7mLzqkLaQw/Ho3sksueffBYw7d2tfrMCX4i9XmJNNU607H8 I5jJnkBvNrBqPXV0WBVgbI1f+/aF14cTlnDqyW3lSfwjaAuiYUkkyR/Gpc/nA/iMwpaj oWvOlC1BNv5I/uNpbFaAqyjcP7Diz9zUBytJHWBIn8jBKbyIKFkjU8Dg+2rY4nuuufZH 0EJPwilfy/f3sAmQJXDSBwe0a8v0X4Jj0d9yYTXi4iNNYZhaxh5KkLiJx528lj1ZVMdk 5zVCCW+9hoce8DPuXWpTy8UYehzWdZX/D3aWdpYwC4dhtQKagEriGpQQ+nsn0LZ/Nn4v YIvw== X-Gm-Message-State: AOAM530HtO9n/OsepR7EU59k/MkG2jL+hTQoFtCnku12osxFfYlbF//Y fgmnNN1aSTNQ1ycgKSn38IHytMafv3Bpzw== X-Google-Smtp-Source: ABdhPJy0Vmx9jPhmoQNZK7prVKWzR6SumUk1r3N5E0dIupTVcfTAr/nY0RiCRTkNfX0o6Q46gj5P/A== X-Received: by 2002:adf:d1e7:0:b0:20c:61a7:de2a with SMTP id g7-20020adfd1e7000000b0020c61a7de2amr14895859wrd.332.1651741912568; Thu, 05 May 2022 02:11:52 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 02/23] target/arm: Split out cpregs.h Date: Thu, 5 May 2022 10:11:26 +0100 Message-Id: <20220505091147.2657652-3-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651744539523100001 From: Richard Henderson Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-2-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 413 +++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 368 --------------------------------- hw/arm/pxa2xx.c | 1 + hw/arm/pxa2xx_pic.c | 1 + hw/intc/arm_gicv3_cpuif.c | 1 + hw/intc/arm_gicv3_kvm.c | 2 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/gdbstub.c | 3 +- target/arm/helper.c | 1 + target/arm/op_helper.c | 1 + target/arm/translate-a64.c | 4 +- target/arm/translate.c | 3 +- 14 files changed, 427 insertions(+), 374 deletions(-) create mode 100644 target/arm/cpregs.h diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h new file mode 100644 index 00000000000..8064c0763e2 --- /dev/null +++ b/target/arm/cpregs.h @@ -0,0 +1,413 @@ +/* + * QEMU ARM CP Register access and descriptions + * + * Copyright (c) 2022 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef TARGET_ARM_CPREGS_H +#define TARGET_ARM_CPREGS_H + +/* + * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a + * special-behaviour cp reg and bits [11..8] indicate what behaviour + * it has. Otherwise it is a simple cp reg, where CONST indicates that + * TCG can assume the value to be constant (ie load at translate time) + * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END + * indicates that the TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). OVERRIDE permits + * a register definition to override a previous definition for the + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the + * old must have the OVERRIDE bit set. + * ALIAS indicates that this register is an alias view of some underlying + * state which is also visible via another register, and that the other + * register is handling migration and reset; registers marked ALIAS will n= ot be + * migrated but may have their state set by syncing of register state from= KVM. + * NO_RAW indicates that this register has no underlying state and does not + * support raw access for state saving/loading; it will not be used for ei= ther + * migration or KVM state synchronization. (Typically this is for "registe= rs" + * which are actually used as instructions for cache maintenance and so on= .) + * IO indicates that this register does I/O and therefore its accesses + * need to be marked with gen_io_start() and also end the TB. In particula= r, + * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the ho= ok + * so that it is safe for the hook to call raise_exception(). + * NEWEL is for writes to registers that might change the exception + * level - typically on older ARM chips. For those cases we need to + * re-read the new el when recomputing the translation flags. + */ +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA +#define ARM_CP_FPU 0x1000 +#define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 +#define ARM_CP_NEWEL 0x10000 +/* Used only as a terminator for ARMCPRegInfo lists */ +#define ARM_CP_SENTINEL 0xfffff +/* Mask of only the flag bits in a type field */ +#define ARM_CP_FLAG_MASK 0x1f0ff + +/* + * Valid values for ARMCPRegInfo state field, indicating which of + * the AArch32 and AArch64 execution states this register is visible in. + * If the reginfo doesn't explicitly specify then it is AArch32 only. + * If the reginfo is declared to be visible in both states then a second + * reginfo is synthesised for the AArch32 view of the AArch64 register, + * such that the AArch32 view is the lower 32 bits of the AArch64 one. + * Note that we rely on the values of these enums as we iterate through + * the various states in some places. + */ +enum { + ARM_CP_STATE_AA32 =3D 0, + ARM_CP_STATE_AA64 =3D 1, + ARM_CP_STATE_BOTH =3D 2, +}; + +/* + * ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates = that + * the register has both a secure and non-secure hash entry. A single one= of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is se= cure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ +}; + +/* + * Return true if cptype is a valid type field. This is used to try to + * catch errors where the sentinel has been accidentally left off the end + * of a list of registers. + */ +static inline bool cptype_valid(int cptype) +{ + return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) + || ((cptype & ARM_CP_SPECIAL) && + ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); +} + +/* + * Access rights: + * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 + * (ie any of the privileged modes in Secure state, or Monitor mode). + * If a register is accessible in one privilege level it's always accessib= le + * in higher privilege levels too. Since "Secure PL1" also follows this ru= le + * (ie anything visible in PL2 is visible in S-PL1, some things are only + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the + * terminology a little and call this PL3. + * In AArch64 things are somewhat simpler as the PLx bits line up exactly + * with the ELx exception levels. + * + * If access permissions for a register are more complex than can be + * described with these bits, then use a laxer set of restrictions, and + * do the more restrictive/complex check inside a helper function. + */ +#define PL3_R 0x80 +#define PL3_W 0x40 +#define PL2_R (0x20 | PL3_R) +#define PL2_W (0x10 | PL3_W) +#define PL1_R (0x08 | PL2_R) +#define PL1_W (0x04 | PL2_W) +#define PL0_R (0x02 | PL1_R) +#define PL0_W (0x01 | PL1_W) + +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + +#define PL3_RW (PL3_R | PL3_W) +#define PL2_RW (PL2_R | PL2_W) +#define PL1_RW (PL1_R | PL1_W) +#define PL0_RW (PL0_R | PL0_W) + +typedef enum CPAccessResult { + /* Access is permitted */ + CP_ACCESS_OK =3D 0, + /* + * Access fails due to a configurable trap or enable which would + * result in a categorized exception syndrome giving information about + * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, + * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or + * PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_TRAP =3D 1, + /* + * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). + * Note that this is not a catch-all case -- the set of cases which may + * result in this failure is specifically defined by the architecture. + */ + CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, + /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_EL2 =3D 3, + CP_ACCESS_TRAP_EL3 =3D 4, + /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, +} CPAccessResult; + +typedef struct ARMCPRegInfo ARMCPRegInfo; + +/* + * Access functions for coprocessor registers. These cannot fail and + * may not raise exceptions. + */ +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value); +/* Access permission check functions for coprocessor registers. */ +typedef CPAccessResult CPAccessFn(CPUARMState *env, + const ARMCPRegInfo *opaque, + bool isread); +/* Hook function for register reset */ +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); + +#define CP_ANY 0xff + +/* Definition of an ARM coprocessor register */ +struct ARMCPRegInfo { + /* Name of register (useful mainly for debugging, need not be unique) = */ + const char *name; + /* + * Location of register: coprocessor number and (crn,crm,opc1,opc2) + * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a + * 'wildcard' field -- any value of that field in the MRC/MCR insn + * will be decoded to this register. The register read and write + * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 + * used by the program, so it is possible to register a wildcard and + * then behave differently on read/write if necessary. + * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 + * must both be zero. + * For AArch64-visible registers, opc0 is also used. + * Since there are no "coprocessors" in AArch64, cp is purely used as a + * way to distinguish (for KVM's benefit) guest-visible system registe= rs + * from demuxed ones provided to preserve the "no side effects on + * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest + * visible (to match KVM's encoding); cp=3D=3D0 will be converted to + * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. + */ + uint8_t cp; + uint8_t crn; + uint8_t crm; + uint8_t opc0; + uint8_t opc1; + uint8_t opc2; + /* Execution state in which this register is visible: ARM_CP_STATE_* */ + int state; + /* Register type: ARM_CP_* bits/values */ + int type; + /* Access rights: PL*_[RW] */ + int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; + /* + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when + * this register was defined: can be used to hand data through to the + * register read/write functions, since they are passed the ARMCPRegIn= fo*. + */ + void *opaque; + /* + * Value of this register, if it is ARM_CP_CONST. Otherwise, if + * fieldoffset is non-zero, the reset value of the register. + */ + uint64_t resetvalue; + /* + * Offset of the field in CPUARMState for this register. + * This is not needed if either: + * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs + * 2. both readfn and writefn are specified + */ + ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + + /* + * Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the st= atic + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used = from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expec= ted + * that both bank offsets are set when defining a banked register. Th= is + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + + /* + * Function for making any access checks for this register in addition= to + * those specified by the 'access' permissions bits. If NULL, no extra + * checks required. The access check is performed at runtime, not at + * translate time. + */ + CPAccessFn *accessfn; + /* + * Function for handling reads of this register. If NULL, then reads + * will be done by loading from the offset into CPUARMState specified + * by fieldoffset. + */ + CPReadFn *readfn; + /* + * Function for handling writes of this register. If NULL, then writes + * will be done by writing to the offset into CPUARMState specified + * by fieldoffset. + */ + CPWriteFn *writefn; + /* + * Function for doing a "raw" read; used when we need to copy + * coprocessor state to the kernel for KVM or out for + * migration. This only needs to be provided if there is also a + * readfn and it has side effects (for instance clear-on-read bits). + */ + CPReadFn *raw_readfn; + /* + * Function for doing a "raw" write; used when we need to copy KVM + * kernel coprocessor state into userspace, or for inbound + * migration. This only needs to be provided if there is also a + * writefn and it masks out "unwritable" bits or has write-one-to-clear + * or similar behaviour. + */ + CPWriteFn *raw_writefn; + /* + * Function for resetting the register. If NULL, then reset will be do= ne + * by writing resetvalue to the field specified in fieldoffset. If + * fieldoffset is 0 then no reset will be done. + */ + CPResetFn *resetfn; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; +}; + +/* + * Macros which are lvalues for the field in CPUARMState for the + * ARMCPRegInfo *ri. + */ +#define CPREG_FIELD32(env, ri) \ + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) +#define CPREG_FIELD64(env, ri) \ + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) + +#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } + +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opaque= ); +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opa= que); +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) +{ + define_arm_cp_regs_with_opaque(cpu, regs, 0); +} +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) +{ + define_one_arm_cp_reg_with_opaque(cpu, regs, 0); +} +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); + +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Is the name actually a glob pattern */ + bool is_glob; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name =3D NULL } + +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); + +/* CPWriteFn that can be used to implement writes-ignored behaviour */ +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); +/* CPReadFn that can be used for read-as-zero behaviour */ +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); + +/* + * CPResetFn that does nothing, for use if no reset is required even + * if fieldoffset is non zero. + */ +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); + +/* + * Return true if this reginfo struct's field in the cpu state struct + * is 64 bits wide. + */ +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +{ + return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); +} + +static inline bool cp_access_ok(int current_el, + const ARMCPRegInfo *ri, int isread) +{ + return (ri->access >> ((current_el * 2) + isread)) & 1; +} + +/* Raw read of a coprocessor register (as needed for migration, etc) */ +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); + +#endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index db8ff044497..d1b558385ce 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2595,144 +2595,6 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) return kvmid; } =20 -/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. - */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff - -/* Valid values for ARMCPRegInfo state field, indicating which of - * the AArch32 and AArch64 execution states this register is visible in. - * If the reginfo doesn't explicitly specify then it is AArch32 only. - * If the reginfo is declared to be visible in both states then a second - * reginfo is synthesised for the AArch32 view of the AArch64 register, - * such that the AArch32 view is the lower 32 bits of the AArch64 one. - * Note that we rely on the values of these enums as we iterate through - * the various states in some places. - */ -enum { - ARM_CP_STATE_AA32 =3D 0, - ARM_CP_STATE_AA64 =3D 1, - ARM_CP_STATE_BOTH =3D 2, -}; - -/* ARM CP register secure state flags. These flags identify security state - * attributes for a given CP register entry. - * The existence of both or neither secure and non-secure flags indicates = that - * the register has both a secure and non-secure hash entry. A single one= of - * these flags causes the register to only be hashed for the specified - * security state. - * Although definitions may have any combination of the S/NS bits, each - * registered entry will only have one to identify whether the entry is se= cure - * or non-secure. - */ -enum { - ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ - ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; - -/* Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - -/* Access rights: - * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 - * (ie any of the privileged modes in Secure state, or Monitor mode). - * If a register is accessible in one privilege level it's always accessib= le - * in higher privilege levels too. Since "Secure PL1" also follows this ru= le - * (ie anything visible in PL2 is visible in S-PL1, some things are only - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the - * terminology a little and call this PL3. - * In AArch64 things are somewhat simpler as the PLx bits line up exactly - * with the ELx exception levels. - * - * If access permissions for a register are more complex than can be - * described with these bits, then use a laxer set of restrictions, and - * do the more restrictive/complex check inside a helper function. - */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) - -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ -#ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R -#else -#define PL0U_R PL1_R -#endif - -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) - /* Return the highest implemented Exception Level */ static inline int arm_highest_el(CPUARMState *env) { @@ -2784,236 +2646,6 @@ static inline int arm_current_el(CPUARMState *env) } } =20 -typedef struct ARMCPRegInfo ARMCPRegInfo; - -typedef enum CPAccessResult { - /* Access is permitted */ - CP_ACCESS_OK =3D 0, - /* Access fails due to a configurable trap or enable which would - * result in a categorized exception syndrome giving information about - * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). - */ - CP_ACCESS_TRAP =3D 1, - /* Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). - * Note that this is not a catch-all case -- the set of cases which may - * result in this failure is specifically defined by the architecture. - */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, -} CPAccessResult; - -/* Access functions for coprocessor registers. These cannot fail and - * may not raise exceptions. - */ -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, - uint64_t value); -/* Access permission check functions for coprocessor registers. */ -typedef CPAccessResult CPAccessFn(CPUARMState *env, - const ARMCPRegInfo *opaque, - bool isread); -/* Hook function for register reset */ -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); - -#define CP_ANY 0xff - -/* Definition of an ARM coprocessor register */ -struct ARMCPRegInfo { - /* Name of register (useful mainly for debugging, need not be unique) = */ - const char *name; - /* Location of register: coprocessor number and (crn,crm,opc1,opc2) - * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a - * 'wildcard' field -- any value of that field in the MRC/MCR insn - * will be decoded to this register. The register read and write - * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 - * used by the program, so it is possible to register a wildcard and - * then behave differently on read/write if necessary. - * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 - * must both be zero. - * For AArch64-visible registers, opc0 is also used. - * Since there are no "coprocessors" in AArch64, cp is purely used as a - * way to distinguish (for KVM's benefit) guest-visible system registe= rs - * from demuxed ones provided to preserve the "no side effects on - * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest - * visible (to match KVM's encoding); cp=3D=3D0 will be converted to - * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. - */ - uint8_t cp; - uint8_t crn; - uint8_t crm; - uint8_t opc0; - uint8_t opc1; - uint8_t opc2; - /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; - /* Register type: ARM_CP_* bits/values */ - int type; - /* Access rights: PL*_[RW] */ - int access; - /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; - /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ - void *opaque; - /* Value of this register, if it is ARM_CP_CONST. Otherwise, if - * fieldoffset is non-zero, the reset value of the register. - */ - uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. - * - * This is not needed if either: - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs - * 2. both readfn and writefn are specified - */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ - - /* Offsets of the secure and non-secure fields in CPUARMState for the - * register if it is banked. These fields are only used during the st= atic - * registration of a register. During hashing the bank associated - * with a given security state is copied to fieldoffset which is used = from - * there on out. - * - * It is expected that register definitions use either fieldoffset or - * bank_fieldoffsets in the definition but not both. It is also expec= ted - * that both bank offsets are set when defining a banked register. Th= is - * use indicates that a register is banked. - */ - ptrdiff_t bank_fieldoffsets[2]; - - /* Function for making any access checks for this register in addition= to - * those specified by the 'access' permissions bits. If NULL, no extra - * checks required. The access check is performed at runtime, not at - * translate time. - */ - CPAccessFn *accessfn; - /* Function for handling reads of this register. If NULL, then reads - * will be done by loading from the offset into CPUARMState specified - * by fieldoffset. - */ - CPReadFn *readfn; - /* Function for handling writes of this register. If NULL, then writes - * will be done by writing to the offset into CPUARMState specified - * by fieldoffset. - */ - CPWriteFn *writefn; - /* Function for doing a "raw" read; used when we need to copy - * coprocessor state to the kernel for KVM or out for - * migration. This only needs to be provided if there is also a - * readfn and it has side effects (for instance clear-on-read bits). - */ - CPReadFn *raw_readfn; - /* Function for doing a "raw" write; used when we need to copy KVM - * kernel coprocessor state into userspace, or for inbound - * migration. This only needs to be provided if there is also a - * writefn and it masks out "unwritable" bits or has write-one-to-clear - * or similar behaviour. - */ - CPWriteFn *raw_writefn; - /* Function for resetting the register. If NULL, then reset will be do= ne - * by writing resetvalue to the field specified in fieldoffset. If - * fieldoffset is 0 then no reset will be done. - */ - CPResetFn *resetfn; - - /* - * "Original" writefn and readfn. - * For ARMv8.1-VHE register aliases, we overwrite the read/write - * accessor functions of various EL1/EL0 to perform the runtime - * check for which sysreg should actually be modified, and then - * forwards the operation. Before overwriting the accessors, - * the original function is copied here, so that accesses that - * really do go to the EL1/EL0 version proceed normally. - * (The corresponding EL2 register is linked via opaque.) - */ - CPReadFn *orig_readfn; - CPWriteFn *orig_writefn; -}; - -/* Macros which are lvalues for the field in CPUARMState for the - * ARMCPRegInfo *ri. - */ -#define CPREG_FIELD32(env, ri) \ - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) -#define CPREG_FIELD64(env, ri) \ - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) - -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } - -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); -} -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); - -/* - * Definition of an ARM co-processor register as viewed from - * userspace. This is used for presenting sanitised versions of - * registers to userspace when emulating the Linux AArch64 CPU - * ID/feature ABI (advertised as HWCAP_CPUID). - */ -typedef struct ARMCPRegUserSpaceInfo { - /* Name of register */ - const char *name; - - /* Is the name actually a glob pattern */ - bool is_glob; - - /* Only some bits are exported to user space */ - uint64_t exported_bits; - - /* Fixed bits are applied after the mask */ - uint64_t fixed_bits; -} ARMCPRegUserSpaceInfo; - -#define REGUSERINFO_SENTINEL { .name =3D NULL } - -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); - -/* CPWriteFn that can be used to implement writes-ignored behaviour */ -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value); -/* CPReadFn that can be used for read-as-zero behaviour */ -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); - -/* CPResetFn that does nothing, for use if no reset is required even - * if fieldoffset is non zero. - */ -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); - -/* Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. - */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) -{ - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); -} - -static inline bool cp_access_ok(int current_el, - const ARMCPRegInfo *ri, int isread) -{ - return (ri->access >> ((current_el * 2) + isread)) & 1; -} - -/* Raw read of a coprocessor register (as needed for migration, etc) */ -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); - /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index a6f938f1152..0683714733b 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -30,6 +30,7 @@ #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" +#include "target/arm/cpregs.h" =20 static struct { hwaddr io_base; diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index ed032fed548..b80d75d839b 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -17,6 +17,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qom/object.h" +#include "target/arm/cpregs.h" =20 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ #define ICMR 0x04 /* Interrupt Controller Mask register */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8404f46ee0b..2d5959db94b 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -20,6 +20,7 @@ #include "gicv3_internal.h" #include "hw/irq.h" #include "cpu.h" +#include "target/arm/cpregs.h" =20 /* * Special case return value from hppvi_index(); must be larger than diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 06f5aceee52..611085e98de 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -31,6 +31,8 @@ #include "vgic_common.h" #include "migration/blocker.h" #include "qom/object.h" +#include "target/arm/cpregs.h" + =20 #ifdef DEBUG_GICV3_KVM #define DPRINTF(fmt, ...) \ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 2b81b18351a..18212eb6eef 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -43,6 +43,7 @@ #include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" +#include "cpregs.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2974cbc0d35..af5ba1d0b3b 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,6 +34,7 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#include "cpregs.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 13d0e9b1954..0e693b182e4 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -18,6 +18,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" #endif +#include "cpregs.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ca1de475116..f01a126108f 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -19,8 +19,9 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" #include "exec/gdbstub.h" +#include "internals.h" +#include "cpregs.h" =20 typedef struct RegisterSysregXmlParam { CPUState *cs; diff --git a/target/arm/helper.c b/target/arm/helper.c index 5a244c3ed93..3f2e555d6f6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -36,6 +36,7 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#include "cpregs.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2b87e8808b6..67be91c7323 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -23,6 +23,7 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a869d573098..348a638c5cb 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -27,14 +27,12 @@ #include "translate.h" #include "internals.h" #include "qemu/host-utils.h" - #include "semihosting/semihost.h" #include "exec/gen-icount.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" - +#include "cpregs.h" #include "translate-a64.h" #include "qemu/atomic128.h" =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 37fb17cdaaf..fc7917cdf44 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -30,11 +30,10 @@ #include "qemu/bitops.h" #include "arm_ldst.h" #include "semihosting/semihost.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" +#include "cpregs.h" =20 =20 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651744732; cv=none; d=zohomail.com; s=zohoarc; b=XA/eKCJUg8fk4z3hWopc0bvJAnPs86hf1SU/Kt1uaFjnNLIdDqM/hBfyhWeJao7iIX3YyFYwyXUzzhrBl1OKBcZECh/1eWAjdN6i/PqfvOwoyBqsR0KTkwwxY5vNY58XfCD6sUrtmYWAiGxqhsqamwlL1DTsQaLEwxjObq+wWrA= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651744732; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=bYZBKnLPYoT9NJwctlvQqMu7v1ZG2DSl8oWKZwkh4ng=; b=Zdh2Uff+PygpUr7OkTw/3nmpztVmHaM7nSujrg5cLNo08XSPauK0gdw4g0NJPJLZ5y1acDIftO5FIMaRRBzT+raPZG5St5MtjHQLcIKw3QUVNfaQ95PZhlhoUbHXw+kJkP3uFJeLoxim7lR4R6n49N4EkUh+9olgjd3/O5n3BRk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651744732271833.0184429856362; Thu, 5 May 2022 02:58:52 -0700 (PDT) Received: from localhost ([::1]:43380 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYG3-0007Bz-7P for importer@patchew.org; Thu, 05 May 2022 05:58:51 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38476) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWf-0004s4-8b for qemu-devel@nongnu.org; Thu, 05 May 2022 05:11:57 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:39690) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWd-0003C1-6x for qemu-devel@nongnu.org; Thu, 05 May 2022 05:11:56 -0400 Received: by mail-wr1-x436.google.com with SMTP id d5so5217645wrb.6 for ; Thu, 05 May 2022 02:11:54 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.52 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=bYZBKnLPYoT9NJwctlvQqMu7v1ZG2DSl8oWKZwkh4ng=; b=svJCPHV3XzdhTClsT94Dwp/Jgjc8ghTeQnCP00DWuuzNtkk0Whg1Ef48OHJWPgRAi7 MX0f4worBZ8x2ltQ5Glbo94cGbVg0zh3wLCKQyancign4RRix3Zg9g+HYNGLt6yNR7qn hjUQLsGfbP7qnBZJ7j4xi61iuYevTtmkoMKPPoFKHz29TYSLSLZG3j+zZOW6GXIqfh5x 7ALagO4PVsxNqP59wiKNXQGO6DbX8iJBReC461u2hAPYeGsLtc3tRXlpWC027NSo/4wv OuuuJjW6GXiKpuNgA/xklBkp18Jr7SgAx77ecKp+H09qnqJJF+GoSGZjko1iwKrifEE6 Z2kg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=bYZBKnLPYoT9NJwctlvQqMu7v1ZG2DSl8oWKZwkh4ng=; b=S+2hoRubccV/4oouzWg2cvL+tQTj5WvLxY9wJahaxjysPtjSNTTphj90T3LLC8Kkt1 jiaX9eVlz6YdeuWiw4P99GSwGHE+PVrLhP8OCN+X5R5pDgzIGVIRD+MrDLUkX6ZNxpOX QZ0Tk/XK0IlRpe0CisesuiYY2DeEn0pTGNGZn39aJWf7Lv9wXuHo+zvhRzwD2kqHX3DB I52bQiFx7mYCVZax96Wir41FT59anjLBc039120QMjEriqeWtwVB64DmwLYoVXgGtHHU dUtrx/Q4dQOKjCUVekWl2aqLr73Q8+IYl1ESapBrsJRCnHWNEPWheO4JlrcMMURfgqBj wMDw== X-Gm-Message-State: AOAM532KrJCoP+1hJq1MVs5/nlIf1m8bzss2ylQwH5UIqHXAy3s40XTz f5CJd/U0WqaH1pcTGU2nnwMKHMaHRIr39w== X-Google-Smtp-Source: ABdhPJz6F6DXXOuxRhpXRTQZC41RNXN5xllNA7QO/9CyTVXQky+sMB53rIWPBaRFlSf73+/HVOY01g== X-Received: by 2002:adf:e3c1:0:b0:20a:aba9:9b38 with SMTP id k1-20020adfe3c1000000b0020aaba99b38mr19615869wrm.673.1651741913562; Thu, 05 May 2022 02:11:53 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 03/23] target/arm: Reorg CPAccessResult and access_check_cp_reg Date: Thu, 5 May 2022 10:11:27 +0100 Message-Id: <20220505091147.2657652-4-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651744734134100001 From: Richard Henderson Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-3-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 26 ++++++++++++-------- target/arm/op_helper.c | 56 +++++++++++++++++++++--------------------- 2 files changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8064c0763e2..7f2c30eab1c 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -167,26 +167,32 @@ static inline bool cptype_valid(int cptype) typedef enum CPAccessResult { /* Access is permitted */ CP_ACCESS_OK =3D 0, + + /* + * Combined with one of the following, the low 2 bits indicate the + * target exception level. If 0, the exception is taken to the usual + * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_EL_MASK =3D 3, + /* * Access fails due to a configurable trap or enable which would * result in a categorized exception syndrome giving information about * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). + * 0xc or 0x18). */ - CP_ACCESS_TRAP =3D 1, + CP_ACCESS_TRAP =3D (1 << 2), + CP_ACCESS_TRAP_EL2 =3D CP_ACCESS_TRAP | 2, + CP_ACCESS_TRAP_EL3 =3D CP_ACCESS_TRAP | 3, + /* * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, + CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 2, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 3, } CPAccessResult; =20 typedef struct ARMCPRegInfo ARMCPRegInfo; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 67be91c7323..76499ffa149 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -632,11 +632,13 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, uint32_t isread) { const ARMCPRegInfo *ri =3D rip; + CPAccessResult res =3D CP_ACCESS_OK; int target_el; =20 if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 && extract32(env->cp15.c15_cpar, ri->cp, 1) =3D=3D 0) { - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)= ); + res =3D CP_ACCESS_TRAP; + goto fail; } =20 /* @@ -655,48 +657,46 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, mask &=3D ~((1 << 4) | (1 << 14)); =20 if (env->cp15.hstr_el2 & mask) { - target_el =3D 2; - goto exept; + res =3D CP_ACCESS_TRAP_EL2; + goto fail; } } =20 - if (!ri->accessfn) { + if (ri->accessfn) { + res =3D ri->accessfn(env, ri, isread); + } + if (likely(res =3D=3D CP_ACCESS_OK)) { return; } =20 - switch (ri->accessfn(env, ri, isread)) { - case CP_ACCESS_OK: - return; + fail: + switch (res & ~CP_ACCESS_EL_MASK) { case CP_ACCESS_TRAP: - target_el =3D exception_target_el(env); - break; - case CP_ACCESS_TRAP_EL2: - /* Requesting a trap to EL2 when we're in EL3 is - * a bug in the access function. - */ - assert(arm_current_el(env) !=3D 3); - target_el =3D 2; - break; - case CP_ACCESS_TRAP_EL3: - target_el =3D 3; break; case CP_ACCESS_TRAP_UNCATEGORIZED: - target_el =3D exception_target_el(env); - syndrome =3D syn_uncategorized(); - break; - case CP_ACCESS_TRAP_UNCATEGORIZED_EL2: - target_el =3D 2; - syndrome =3D syn_uncategorized(); - break; - case CP_ACCESS_TRAP_UNCATEGORIZED_EL3: - target_el =3D 3; syndrome =3D syn_uncategorized(); break; default: g_assert_not_reached(); } =20 -exept: + target_el =3D res & CP_ACCESS_EL_MASK; + switch (target_el) { + case 0: + target_el =3D exception_target_el(env); + break; + case 2: + assert(arm_current_el(env) !=3D 3); + assert(arm_is_el2_enabled(env)); + break; + case 3: + assert(arm_feature(env, ARM_FEATURE_EL3)); + break; + default: + /* No "direct" traps to EL1 */ + g_assert_not_reached(); + } + raise_exception(env, EXCP_UDEF, syndrome, target_el); } =20 --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745913; cv=none; d=zohomail.com; s=zohoarc; b=CyUKeCz43Cbv5tSfazu25uJowwdIsNUR4R9cZwDO2CBqPXwqkqFvPtQoa6RCUI5cly4ka1Njl3xCcNTPkWKfDgVuWTohC9Mmi8qY+SUmsAONozXNin9W0PgkvlbTrgR5+z+htePQXDQXfi2s87kGahTfcabFGiAL9TPnJ4nw7aM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651745913; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.53 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=8+91d8rFVyZN73NPWN0m6PMw0ggbZzvPHiHIUBYcNWQ=; b=ymNGRWLTuyX9+ODhNd3ByjPv6dpedK/ASsTZ6ffIrjiyJJgqiEwAb+CGoTM7Xw1zAO 8zEHPRO6yLoAkE02c8YVe9GQcDM1X6bvrmwTmahFquywS6KMCwRn54mF7SDEDHVmm/up YQkLhGen2EGD4P+djk/mhi4uOoHjDH/KoH5lmgJvtIxcyDCgcirHowPVKzTRKB4KKc4p w2bKC0ooH8z0L+DQ1OXU+KU9fHHIK2Q9Io4Z0CxkjRW7kKEhFsZ5zMTh6MgrNHafoxl8 6YBmXFpW9H/HF+AGJckJ84PGn6CTu/tj+AwA2ZalDS60VWX3MUeob/u4FrUU9sxMSeqj ZA5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8+91d8rFVyZN73NPWN0m6PMw0ggbZzvPHiHIUBYcNWQ=; b=ZWNQfEq5KIiwFxtPsStARGVeSTvCN9z8q/MCh+xkUitMgHfr1qdj1ViPKVkfgkScEQ q6hr+bea7Xsy7K6EkH14UkC+I8hCrt3/c60FI04dbnqoE0mVKzgciWaQeHH9KII25Am5 LPsjq69xmpIUdtzS6Hs1BY3u5uPX2mLtSnbVTnxzhdiUILrHzqgNInpRCGI7ZwhaRJ5P F6UTes4xS3GNLQtkX3y/8H6WSogkeqnXIfG5Pnf35A3/APimYFWZ3D4nUv5kB7IQS6IE S1VMqJqVHC8jQ9YEvhpq8cnD1uA1uafim9t+9h4KJR/1ivx6dvo4olnyhMC1cP+ueaEH nHug== X-Gm-Message-State: AOAM532AXxydQvtXQ/p2Uv2LomA0IroyqvNwm2pKH8CUbZR/itivQEOJ iM5amtZdRnw6aX1m45nWBldtcEL28F8IYw== X-Google-Smtp-Source: ABdhPJxZDdPDhUxUFGWDK1+mKoUU5/HbLRfI1kqWlAPMw5uTRXnHX3XKaiNhHWjjP2DSZk2zcRP5pQ== X-Received: by 2002:adf:f747:0:b0:20a:d30a:5f08 with SMTP id z7-20020adff747000000b0020ad30a5f08mr19893512wrp.278.1651741914869; Thu, 05 May 2022 02:11:54 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 04/23] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Date: Thu, 5 May 2022 10:11:28 +0100 Message-Id: <20220505091147.2657652-5-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::432; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745913628100001 From: Richard Henderson Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-4-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 53 +++++++++--------- hw/arm/pxa2xx.c | 1 - hw/arm/pxa2xx_pic.c | 1 - hw/intc/arm_gicv3_cpuif.c | 5 -- hw/intc/arm_gicv3_kvm.c | 1 - target/arm/cpu64.c | 1 - target/arm/cpu_tcg.c | 4 -- target/arm/helper.c | 111 ++++++++------------------------------ 8 files changed, 48 insertions(+), 129 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7f2c30eab1c..a5231504d58 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -71,8 +71,6 @@ #define ARM_CP_NO_GDB 0x4000 #define ARM_CP_RAISES_EXC 0x8000 #define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff /* Mask of only the flag bits in a type field */ #define ARM_CP_FLAG_MASK 0x1f0ff =20 @@ -108,18 +106,6 @@ enum { ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ }; =20 -/* - * Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - /* * Access rights: * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM @@ -346,20 +332,27 @@ struct ARMCPRegInfo { #define CPREG_FIELD64(env, ri) \ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) =20 -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *re= g, + void *opaque); =20 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) { - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); + define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); } + +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, + void *opaque, size_t len); + +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ + define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ + ARRAY_SIZE(REGS)); \ + } while (0) + +#define define_arm_cp_regs(CPU, REGS) \ + define_arm_cp_regs_with_opaque(CPU, REGS, NULL) + const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 /* @@ -382,9 +375,17 @@ typedef struct ARMCPRegUserSpaceInfo { uint64_t fixed_bits; } ARMCPRegUserSpaceInfo; =20 -#define REGUSERINFO_SENTINEL { .name =3D NULL } +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, + const ARMCPRegUserSpaceInfo *mods, + size_t mods_len); =20 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); +#define modify_arm_cp_regs(REGS, MODS) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) =3D=3D 0); = \ + modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ + MODS, ARRAY_SIZE(MODS)); \ + } while (0) =20 /* CPWriteFn that can be used to implement writes-ignored behaviour */ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 0683714733b..f4f687df68e 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -384,7 +384,6 @@ static const ARMCPRegInfo pxa_cp_reginfo[] =3D { { .name =3D "PWRMODE", .cp =3D 14, .crn =3D 7, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_IO, .readfn =3D arm_cp_read_zero, .writefn =3D pxa2xx_pwrmode_write }, - REGINFO_SENTINEL }; =20 static void pxa2xx_setup_cp14(PXA2xxState *s) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index b80d75d839b..47132ab982b 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -257,7 +257,6 @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] =3D { REGINFO_FOR_PIC_CP("ICLR2", 8), REGINFO_FOR_PIC_CP("ICFP2", 9), REGINFO_FOR_PIC_CP("ICPR2", 0xa), - REGINFO_SENTINEL }; =20 static const MemoryRegionOps pxa2xx_pic_ops =3D { diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 2d5959db94b..9efba798f82 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2428,7 +2428,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .readfn =3D icc_igrpen1_el3_read, .writefn =3D icc_igrpen1_el3_write, }, - REGINFO_SENTINEL }; =20 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2682,7 +2681,6 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { .readfn =3D ich_vmcr_read, .writefn =3D ich_vmcr_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] =3D { @@ -2700,7 +2698,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_regin= fo[] =3D { .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] =3D { @@ -2732,7 +2729,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, }, - REGINFO_SENTINEL }; =20 static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) @@ -2807,7 +2803,6 @@ void gicv3_init_cpuif(GICv3State *s) .readfn =3D ich_lr_read, .writefn =3D ich_lr_write, }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, lr_regset); } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 611085e98de..2922c516e56 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -735,7 +735,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { */ .resetfn =3D arm_gicv3_icc_reset, }, - REGINFO_SENTINEL }; =20 /** diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index af5ba1d0b3b..c841d55d0e9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -91,7 +91,6 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[]= =3D { { .name =3D "L2MERRSR", .cp =3D 15, .opc1 =3D 3, .crm =3D 15, .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - REGINFO_SENTINEL }; =20 static void aarch64_a57_initfn(Object *obj) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0e693b182e4..9338088b226 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -264,7 +264,6 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void cortex_a8_initfn(Object *obj) @@ -332,7 +331,6 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - REGINFO_SENTINEL }; =20 static void cortex_a9_initfn(Object *obj) @@ -398,7 +396,6 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { #endif { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void cortex_a7_initfn(Object *obj) @@ -686,7 +683,6 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST }, { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static void cortex_r5_initfn(Object *obj) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f2e555d6f6..a68f14fe8e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -673,7 +673,6 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { @@ -702,7 +701,6 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { @@ -711,7 +709,6 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { */ { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_WFI }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { @@ -760,7 +757,6 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -889,7 +885,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, - REGINFO_SENTINEL }; =20 typedef struct pm_event { @@ -2135,7 +2130,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { @@ -2152,7 +2146,6 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { @@ -2170,7 +2163,6 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; =20 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2211,7 +2203,6 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), .accessfn =3D teehbr_access, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v6k_cp_reginfo[] =3D { @@ -2243,7 +2234,6 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -3091,7 +3081,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, }, - REGINFO_SENTINEL }; =20 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3132,7 +3121,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .readfn =3D gt_virt_cnt_read, }, - REGINFO_SENTINEL }; =20 #endif @@ -3496,7 +3484,6 @@ static const ARMCPRegInfo vapa_cp_reginfo[] =3D { .access =3D PL1_W, .accessfn =3D ats_access, .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC = }, #endif - REGINFO_SENTINEL }; =20 /* Return basic MPU access permission bits. */ @@ -3619,7 +3606,6 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), .writefn =3D pmsav7_rgnr_write, .resetfn =3D arm_cp_reset_ignore }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { @@ -3670,7 +3656,6 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, - REGINFO_SENTINEL }; =20 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3824,7 +3809,6 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { @@ -3857,7 +3841,6 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.tcr_el[3]), offsetof(CPUARMState, cp15.tcr_el[1])} }, - REGINFO_SENTINEL }; =20 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3942,7 +3925,6 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { { .name =3D "C9", .cp =3D 15, .crn =3D 9, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3975,7 +3957,6 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { { .name =3D "XSCALE_UNLOCK_DCACHE", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { @@ -3989,7 +3970,6 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { @@ -3997,7 +3977,6 @@ static const ARMCPRegInfo cache_dirty_status_cp_regin= fo[] =3D { { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { @@ -4018,7 +3997,6 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[= ] =3D { .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { @@ -4031,7 +4009,6 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo= [] =3D { { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D (1 << 30) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { @@ -4040,7 +4017,6 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, - REGINFO_SENTINEL }; =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -4107,7 +4083,6 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, .writefn =3D vmsa_ttbr_write, }, - REGINFO_SENTINEL }; =20 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5126,7 +5101,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .writefn =3D sdcr_write, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, - REGINFO_SENTINEL }; =20 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ @@ -5237,7 +5211,6 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 /* Ditto, but for registers which exist in ARMv8 but not v7 */ @@ -5246,7 +5219,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) @@ -5679,7 +5651,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { @@ -5689,7 +5660,6 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), .writefn =3D hcr_writehigh }, - REGINFO_SENTINEL }; =20 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5710,7 +5680,6 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, .access =3D PL2_RW, .accessfn =3D sel2_access, .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, - REGINFO_SENTINEL }; =20 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -5836,7 +5805,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae3_write }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -6122,7 +6090,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { @@ -6131,7 +6098,6 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - REGINFO_SENTINEL }; =20 /* Return the exception level to which exceptions should be taken @@ -6617,7 +6583,6 @@ static void define_debug_regs(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, dbgregs); } @@ -6636,7 +6601,6 @@ static void define_debug_regs(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, dbgregs); } @@ -6699,7 +6663,6 @@ static void define_pmu_regs(ARMCPU *cpu) .type =3D ARM_CP_IO, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, pmev_regs); g_free(pmevcntr_name); @@ -6717,7 +6680,6 @@ static void define_pmu_regs(ARMCPU *cpu) .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v81_pmu_regs); } @@ -6814,7 +6776,6 @@ static const ARMCPRegInfo lor_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, .access =3D PL1_R, .accessfn =3D access_lor_ns, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 #ifdef TARGET_AARCH64 @@ -6877,7 +6838,6 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo tlbirange_reginfo[] =3D { @@ -6989,7 +6949,6 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_rvae3_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo tlbios_reginfo[] =3D { @@ -7061,7 +7020,6 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae3is_write }, - REGINFO_SENTINEL }; =20 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7100,7 +7058,6 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, .access =3D PL0_R, .readfn =3D rndr_readfn }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -7136,7 +7093,6 @@ static const ARMCPRegInfo dcpop_reg[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo dcpodp_reg[] =3D { @@ -7144,7 +7100,6 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ =20 @@ -7246,14 +7201,12 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { @@ -7305,7 +7258,6 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { .accessfn =3D aa64_zva_access, #endif }, - REGINFO_SENTINEL }; =20 #endif @@ -7351,7 +7303,6 @@ static const ARMCPRegInfo predinv_reginfo[] =3D { { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - REGINFO_SENTINEL }; =20 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7366,7 +7317,6 @@ static const ARMCPRegInfo ccsidr2_reginfo[] =3D { .access =3D PL1_R, .accessfn =3D access_aa64_tid2, .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, - REGINFO_SENTINEL }; =20 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, @@ -7427,7 +7377,6 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, .accessfn =3D access_joscr_jmcr, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo vhe_reginfo[] =3D { @@ -7492,7 +7441,6 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, #endif - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -7505,7 +7453,6 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo ats1cp_reginfo[] =3D { @@ -7517,7 +7464,6 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write }, - REGINFO_SENTINEL }; #endif =20 @@ -7539,7 +7485,6 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 void register_cp_regs_for_features(ARMCPU *cpu) @@ -7646,7 +7591,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar6 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); @@ -7914,7 +7858,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .resetvalue =3D cpu->pmceid1 }, - REGINFO_SENTINEL }; #ifdef CONFIG_USER_ONLY ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { @@ -7944,7 +7887,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits =3D 0x000000f0ffffffff }, { .name =3D "ID_AA64ISAR*_EL1_RESERVED", .is_glob =3D true }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); #endif @@ -7984,7 +7926,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL2_RW, .resetvalue =3D vmpidr_def, .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el2_cp_reginfo); @@ -8023,7 +7964,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); @@ -8046,7 +7986,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .raw_writefn =3D raw_write, .writefn =3D sctlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), .resetvalue =3D cpu->reset_sctlr }, - REGINFO_SENTINEL }; =20 define_arm_cp_regs(cpu, el3_regs); @@ -8181,7 +8120,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - REGINFO_SENTINEL }; ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -8201,7 +8139,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, - REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ @@ -8219,7 +8156,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_aa32_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; /* TLBTR is specific to VMSA */ ARMCPRegInfo id_tlbtr_reginfo =3D { @@ -8246,25 +8182,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MIDR_EL1", .exported_bits =3D 0x00000000ffffffff }, { .name =3D "REVIDR_EL1" }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); #endif if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { - ARMCPRegInfo *r; + size_t i; /* Register the blanket "writes ignored" value first to cover = the * whole space. Then update the specific ID registers to allow= write * access, so that they ignore writes rather than causing them= to * UNDEF. */ define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); - for (r =3D id_pre_v8_midr_cp_reginfo; - r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; + for (i =3D 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { + id_pre_v8_midr_cp_reginfo[i].access =3D PL1_RW; } - for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; + for (i =3D 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { + id_cp_reginfo[i].access =3D PL1_RW; } id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; @@ -8287,13 +8221,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, - REGINFO_SENTINEL }; #ifdef CONFIG_USER_ONLY ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .fixed_bits =3D 0x0000000080000000 }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); #endif @@ -8314,7 +8246,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, auxcr_reginfo); if (cpu_isar_feature(aa32_ac2, cpu)) { @@ -8349,7 +8280,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type =3D ARM_CP_CONST, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, - REGINFO_SENTINEL }; /* We don't implement a r/w 64 bit CBAR currently */ assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); @@ -8379,7 +8309,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vbar_cp_reginfo); } @@ -8833,8 +8762,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->writefn); } } - /* Bad type field probably means missing sentinel at end of reg list */ - assert(cptype_valid(r->type)); + for (crm =3D crmmin; crm <=3D crmmax; crm++) { for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { @@ -8880,13 +8808,13 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } } =20 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque) +/* Define a whole list of registers */ +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, + void *opaque, size_t len) { - /* Define a whole list of registers */ - const ARMCPRegInfo *r; - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); + size_t i; + for (i =3D 0; i < len; ++i) { + define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); } } =20 @@ -8898,17 +8826,20 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, * user-space cannot alter any values and dynamic values pertaining to * execution state are hidden from user space view anyway. */ -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, + const ARMCPRegUserSpaceInfo *mods, + size_t mods_len) { - const ARMCPRegUserSpaceInfo *m; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=YjElCrdn3SbyJTPO/xD9X6anEjzd2DD/bUoEpuTw2Og=; b=jW9A5bjXRH+ElNJJaw28EZLD6vj/3dCXgloKdehl4ei/9aIz2JjIKj0MQha7UrzJNk 0PxXdiCIH2F84AzOorgrluEpmhup0AEzBIT2b1nAjfsGvA316lQvwW4mLd1StDyYx/za DPCkbllE+aYCgzGVQ6RRzBCA4XWfkFlL3VD0A7DOl058wpZ+uktQt6G+XpTgAgt9deM+ SP+5URG0pT3wBjdtDJeo8hsJ05TlIpQtKsUn2rFmNlAWrpGZE5vAUqsnE1tL76XEsI+W SnWyIkzG6esKXBSTK9vf7LLt2SYo+T+Z4OHKT4GMF38yFWjOqT4xoHoNrz1xO9iITpjM gVSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YjElCrdn3SbyJTPO/xD9X6anEjzd2DD/bUoEpuTw2Og=; b=SpntCB5wwW8Xspp+Qe1mFELD48oLG5hQ3zOXv1kt9pauDRXHHxmKNb7iU3DUXWEiee 0fBNlsmf2zjewMDpIrEiBDKGbBl2b/OBMcr5VpzQvTGbrg7us/Mtl2XOztkF7ZHfd0jn TJ15pgqRKgzndLHUFAXiN7zEX5OXZKlU3WM0mjJYFvJ9gygUD0oTjjaoZdBCf/di6GZ8 1uINf7I9ngzR9EMp0dHC3kJJ39D/KOd0CrkFMFQCaUxFlq/X8l88AbvQicbJcccyVgQe iu79KWi/MpDJOOuBhazJ2n6IuopXDBWsm3j11zVWZkfrDs+aK6GDl7HMdzAwK17zGjD4 ZMsw== X-Gm-Message-State: AOAM531CoYpx5tMqhZg/p+oam217bcq1i10VrilPwdWporJgoJlRlL/O +pMhkEayggn2Y09uM7WfaFFXEIJMuxG9Ww== X-Google-Smtp-Source: ABdhPJwh26tp5gPjQVDW8nnXX9xCUCZZezTPUJlPk0bxji4Kmp4ivWuGk7jgI+iULnYp3SUJCGwqng== X-Received: by 2002:a5d:4f8b:0:b0:20c:6970:fb3c with SMTP id d11-20020a5d4f8b000000b0020c6970fb3cmr12687783wru.554.1651741915789; Thu, 05 May 2022 02:11:55 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 05/23] target/arm: Make some more cpreg data static const Date: Thu, 5 May 2022 10:11:29 +0100 Message-Id: <20220505091147.2657652-6-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745052457100001 From: Richard Henderson These particular data structures are not modified at runtime. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-5-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a68f14fe8e2..ca6ba9bd820 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7860,7 +7860,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { + static const ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { { .name =3D "ID_AA64PFR0_EL1", .exported_bits =3D 0x000f000f00ff0000, .fixed_bits =3D 0x0000000000000011 }, @@ -8000,7 +8000,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL1_RW, .accessfn =3D nsacr_access, @@ -8008,7 +8008,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &nsacr); } else { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL3_RW | PL1_R, @@ -8019,7 +8019,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } else { if (arm_feature(env, ARM_FEATURE_V8)) { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL1_R, @@ -8172,13 +8172,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; - ARMCPRegInfo crn0_wi_reginfo =3D { + static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { + static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = =3D { { .name =3D "MIDR_EL1", .exported_bits =3D 0x00000000ffffffff }, { .name =3D "REVIDR_EL1" }, @@ -8223,7 +8223,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { + static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .fixed_bits =3D 0x0000000080000000 }, }; @@ -8302,7 +8302,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (arm_feature(env, ARM_FEATURE_VBAR)) { - ARMCPRegInfo vbar_cp_reginfo[] =3D { + static const ARMCPRegInfo vbar_cp_reginfo[] =3D { { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745378; cv=none; d=zohomail.com; s=zohoarc; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.55 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=IuSpAmHPbsd9vxR/x219V7l1HJzViUnpVRA6Wdv5c30=; b=x9RfJ1N04NsAL4wsi4I/4KGunGNUvsHEMSB71zbjdTc0cRp3gVyPZ0pFaHFl0ImGJV u07f5JHAzP3gQb0P6BaBMQ+RZ9BWkqd/N70aheZuxdO6jrxMYzBrMMnhMf0ple8Efl88 Xr4Xb817BsHF+v6amEFxa6xB3oMZnMmGw1sytlHL9wZm0/mofKAtYS7uqH8hjz++l3rC tytgEeNIdRI2Iyck72/bJnUoNCqWGnt0dd2DavGAY4p259CbZo3ye7PO7Kh7GtTV/DpU v9tfqvhS2fo57QAexUoPzYawEYB/o9ZC1zb6vS7TY7mHam3kp7CEOtDw6iYkfCGZoP60 kjSw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=IuSpAmHPbsd9vxR/x219V7l1HJzViUnpVRA6Wdv5c30=; b=p9HsF+BD7LeVO7rTpbApdUfrOcRvM6KsUykQZHGntqEnYIKOloK2H1qszeFD6vd8qJ VEmSp25Mdu34YiJaFnukklH/mSrerc31lwr+D5Zo8FG4x84wAqbNmJcWyvyQB9sFqbx+ irY3lkLu5mBTgVUxqLEeIbC9VwLBm5G22qDL65jKwCNx0EdAbIKJIqUZ+RHHP2yUJudb 3vIi+oBGcDPZnsGFSqwMZ8GqUrs+sxeDQPzW2ziNbaDwOso3yUUzoL/T+Rcgn+uqmsEN cn4C9FqQjI0IRcXJNP4q8/QLnwXg+7CyhVoDqG1SoF5VBaE6trgwnw0Tk/CBUt6kgBRG zbIw== X-Gm-Message-State: AOAM533ScHA5NAxygEYv3anN+U/tyLcXkmk0EelsFioTw6gTvcsRzYXn tA6ElGBo8Yc9e3mUQ8c4pz0O7LsQEg9LNA== X-Google-Smtp-Source: ABdhPJxZ98d06VGcRNv+9MrcCeWhnObK55YbyRD8dC4SUmEljn8lkzUWkvzCCs+CuK80asQsqhVx5g== X-Received: by 2002:a05:6000:15c5:b0:20c:565e:fd64 with SMTP id y5-20020a05600015c500b0020c565efd64mr18931533wry.499.1651741916715; Thu, 05 May 2022 02:11:56 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 06/23] target/arm: Reorg ARMCPRegInfo type field bits Date: Thu, 5 May 2022 10:11:30 +0100 Message-Id: <20220505091147.2657652-7-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745380631100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-6-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 130 +++++++++++++++++++++++-------------- target/arm/cpu.c | 4 +- target/arm/helper.c | 4 +- target/arm/translate-a64.c | 6 +- target/arm/translate.c | 6 +- 5 files changed, 92 insertions(+), 58 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index a5231504d58..ff3817decbd 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,57 +22,87 @@ #define TARGET_ARM_CPREGS_H =20 /* - * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. + * ARMCPRegInfo type field bits: */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff +enum { + /* + * Register must be handled specially during translation. + * The method is one of the values below: + */ + ARM_CP_SPECIAL_MASK =3D 0x000f, + /* Special: no change to PE state: writes ignored, reads ignored. */ + ARM_CP_NOP =3D 0x0001, + /* Special: sysreg is WFI, for v5 and v6. */ + ARM_CP_WFI =3D 0x0002, + /* Special: sysreg is NZCV. */ + ARM_CP_NZCV =3D 0x0003, + /* Special: sysreg is CURRENTEL. */ + ARM_CP_CURRENTEL =3D 0x0004, + /* Special: sysreg is DC ZVA or similar. */ + ARM_CP_DC_ZVA =3D 0x0005, + ARM_CP_DC_GVA =3D 0x0006, + ARM_CP_DC_GZVA =3D 0x0007, + + /* Flag: reads produce resetvalue; writes ignored. */ + ARM_CP_CONST =3D 1 << 4, + /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ + ARM_CP_64BIT =3D 1 << 5, + /* + * Flag: TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). + */ + ARM_CP_SUPPRESS_TB_END =3D 1 << 6, + /* + * Flag: Permit a register definition to override a previous definition + * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new + * or the old must have the ARM_CP_OVERRIDE bit set. + */ + ARM_CP_OVERRIDE =3D 1 << 7, + /* + * Flag: Register is an alias view of some underlying state which is a= lso + * visible via another register, and that the other register is handli= ng + * migration and reset; registers marked ARM_CP_ALIAS will not be migr= ated + * but may have their state set by syncing of register state from KVM. + */ + ARM_CP_ALIAS =3D 1 << 8, + /* + * Flag: Register does I/O and therefore its accesses need to be marked + * with gen_io_start() and also end the TB. In particular, registers w= hich + * implement clocks or timers require this. + */ + ARM_CP_IO =3D 1 << 9, + /* + * Flag: Register has no underlying state and does not support raw acc= ess + * for state saving/loading; it will not be used for either migration = or + * KVM state synchronization. Typically this is for "registers" which = are + * actually used as instructions for cache maintenance and so on. + */ + ARM_CP_NO_RAW =3D 1 << 10, + /* + * Flag: The read or write hook might raise an exception; the generated + * code will synchronize the CPU state before calling the hook so that= it + * is safe for the hook to call raise_exception(). + */ + ARM_CP_RAISES_EXC =3D 1 << 11, + /* + * Flag: Writes to the sysreg might change the exception level - typic= ally + * on older ARM chips. For those cases we need to re-read the new el w= hen + * recomputing the translation flags. + */ + ARM_CP_NEWEL =3D 1 << 12, + /* + * Flag: Access check for this sysreg is identical to accessing FPU st= ate + * from an instruction: use translation fp_access_check(). + */ + ARM_CP_FPU =3D 1 << 13, + /* + * Flag: Access check for this sysreg is identical to accessing SVE st= ate + * from an instruction: use translation sve_access_check(). + */ + ARM_CP_SVE =3D 1 << 14, + /* Flag: Do not expose in gdb sysreg xml. */ + ARM_CP_NO_GDB =3D 1 << 15, +}; =20 /* * Valid values for ARMCPRegInfo state field, indicating which of diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 18212eb6eef..a7cd692010c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -117,7 +117,7 @@ static void cp_reg_reset(gpointer key, gpointer value, = gpointer opaque) ARMCPRegInfo *ri =3D value; ARMCPU *cpu =3D opaque; =20 - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { return; } =20 @@ -153,7 +153,7 @@ static void cp_reg_check_reset(gpointer key, gpointer v= alue, gpointer opaque) ARMCPU *cpu =3D opaque; uint64_t oldvalue, newvalue; =20 - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { return; } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index ca6ba9bd820..f84377babe1 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8600,7 +8600,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if ((r->type & ARM_CP_SPECIAL)) { + if (r->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || @@ -8750,7 +8750,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Check that the register definition has enough info to handle * reads and writes if they are permitted. */ - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { + if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { if (r->access & PL3_R) { assert((r->fieldoffset || (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 348a638c5cb..a82f5d5984b 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1833,7 +1833,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } =20 /* Handle special cases first */ - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { + switch (ri->type & ARM_CP_SPECIAL_MASK) { + case 0: + break; case ARM_CP_NOP: return; case ARM_CP_NZCV: @@ -1908,7 +1910,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } return; default: - break; + g_assert_not_reached(); } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; diff --git a/target/arm/translate.c b/target/arm/translate.c index fc7917cdf44..050c237b076 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4744,7 +4744,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } =20 /* Handle special cases first */ - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { + switch (ri->type & ARM_CP_SPECIAL_MASK) { + case 0: + break; case ARM_CP_NOP: return; case ARM_CP_WFI: @@ -4756,7 +4758,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, s->base.is_jmp =3D DISAS_WFI; return; default: - break; + g_assert_not_reached(); } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651742611; cv=none; d=zohomail.com; s=zohoarc; b=gW+0ZL7qnPSw8swJeViajnek8ZqjndYEmLNMFsDDNKefm0ug4mU7JTuyUHacQOGBZCUJ3OlswnQbgXm16c6OXTMAI9nBjtrSYBDZDtMSScOHxmmttBm7NuPaOoZCLaejRPkL4C5eKZkPb8RMsZl70RFB/F5UoyQb6cbxpWILu68= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651742611; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=hSAkfjiq8NHovzsRkuZFZACusQ6Byf9p05IGivYIsEk=; b=IVekebWkO0F7fFZ0iVZSrZEf0xMpwSwca1X1B1Cg3Zu4zm2XHKUpKqLcNYKY+iBn7GE3Kfhg9kXz8oIqT9YwUx1WB0PXcdYv5RJVG7WY+VQ0J1SOdhTKNeGOuWxpU/Z3oJkzDLyRsE21wEgujOu8IlhJR3meNknBy+xknOkbReA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651742611161237.34526319618942; Thu, 5 May 2022 02:23:31 -0700 (PDT) Received: from localhost ([::1]:42370 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmXhq-0000ld-1D for importer@patchew.org; Thu, 05 May 2022 05:23:30 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWi-00051f-Um for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:01 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:43667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWh-0003HP-5y for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:00 -0400 Received: by mail-wm1-x331.google.com with SMTP id r1-20020a1c2b01000000b00394398c5d51so2243166wmr.2 for ; Thu, 05 May 2022 02:11:58 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=hSAkfjiq8NHovzsRkuZFZACusQ6Byf9p05IGivYIsEk=; b=BnnXWoEls/1ZUJBnUPnoGJEGoOKXhnk/9Ow5zmAyIOlY8sKr4PEIsRP9xJopWGM187 OD0rFpZHJE20Qj/7UlsYWbFBg6mP2HTpXNtUuzL49fc8ANX/AuC8GctRY35zVNDsBMKE ribhN4T3tDVCU5XqNbvRtiXyKKz+xoObpo7E1xeIT7jrHn5buFDFhvTID6LVNEWseL6y rgQUVis9hVrHpUqWRETzbBQ0HZMBLGfGkdVTVzv5/D7szD50V9F8PjhNsCV9SnnBoLQZ Zpwyhdw/w/fBhnp+0INwwE7A+UB55ka0PjY7fZQMvLdpMz35/04ZqXQJsZ2cm5lSYwSu 7MCg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=hSAkfjiq8NHovzsRkuZFZACusQ6Byf9p05IGivYIsEk=; b=m1FCV3wqIi5VKr0jLuwsQlaQpuI+qIyFbz7ONsqprxQ+F5ijy77Z9RG2Um63d+K43a y8atYVsfPjZwH3HECyohWCrLem2iOmlUkpjebCiM7kH4X1t16YvxMyf1Lf8jyjN5UuY2 /XG7iIVvaoth1QzxGtcwxL+1SiIJwioD9eGp4DypMa18/7cQa4Xw6Vol0ftNUyF7PCil SUoa9zvzNsOPRedtKasZAZ6n5MX7oFiwFwvABgN9Pyh4E6utC83xnTIqJic92fcdiblr 20AdZIS7X00rZu9lUjVmBYXpwdy+xO8MRGj6Ap+z2dd27utdFySKsb/XUwfKJey4XMbJ D2nw== X-Gm-Message-State: AOAM533i1Ea4wYho38EgOVk8hgHDppJGG95iKtKkbhAUtSGDljzbipT0 TCTIAn9ddti1F3SfsQrFJdcweoN7dibKqQ== X-Google-Smtp-Source: ABdhPJyhiMsq9V4krNmuQHXP7bvS0axIBqbHAaukZt9d1UjYGAegNdl1JCJOd0NytLVyZxGs9YVguQ== X-Received: by 2002:a7b:ce04:0:b0:394:1f46:213 with SMTP id m4-20020a7bce04000000b003941f460213mr3489656wmc.157.1651741917613; Thu, 05 May 2022 02:11:57 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 07/23] target/arm: Avoid bare abort() or assert(0) Date: Thu, 5 May 2022 10:11:31 +0100 Message-Id: <20220505091147.2657652-8-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651742612710100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-7-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 7 +++---- target/arm/hvf/hvf.c | 2 +- target/arm/kvm-stub.c | 4 ++-- target/arm/kvm.c | 4 ++-- target/arm/machine.c | 4 ++-- target/arm/translate-a64.c | 4 ++-- target/arm/translate-neon.c | 2 +- target/arm/translate.c | 4 ++-- 8 files changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f84377babe1..06f8864c778 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8740,8 +8740,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, break; default: /* broken reginfo with out-of-range opc1 */ - assert(false); - break; + g_assert_not_reached(); } /* assert our permissions are not too lax (stricter is fine) */ assert((r->access & ~mask) =3D=3D 0); @@ -10823,7 +10822,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint= 32_t address, break; default: /* Never happens, but compiler isn't smart enough to tell. */ - abort(); + g_assert_not_reached(); } } *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); @@ -10944,7 +10943,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, break; default: /* Never happens, but compiler isn't smart enough to tell. */ - abort(); + g_assert_not_reached(); } } if (domain_prot =3D=3D 3) { diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b11a8b9a189..86710509d20 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1200,7 +1200,7 @@ int hvf_vcpu_exec(CPUState *cpu) /* we got kicked, no exit to process */ return 0; default: - assert(0); + g_assert_not_reached(); } =20 hvf_sync_vtimer(cpu); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 56a7099e6b9..965a486b320 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -15,10 +15,10 @@ =20 bool write_kvmstate_to_list(ARMCPU *cpu) { - abort(); + g_assert_not_reached(); } =20 bool write_list_to_kvmstate(ARMCPU *cpu, int level) { - abort(); + g_assert_not_reached(); } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5fc37ac10a5..4339e1cd6e0 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -540,7 +540,7 @@ bool write_kvmstate_to_list(ARMCPU *cpu) ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); break; default: - abort(); + g_assert_not_reached(); } if (ret) { ok =3D false; @@ -575,7 +575,7 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) r.addr =3D (uintptr_t)(cpu->cpreg_values + i); break; default: - abort(); + g_assert_not_reached(); } ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 135d2420b5c..285e387d2c3 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -661,7 +661,7 @@ static int cpu_pre_save(void *opaque) if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ - abort(); + g_assert_not_reached(); } =20 /* @@ -672,7 +672,7 @@ static int cpu_pre_save(void *opaque) } else { if (!write_cpustate_to_list(cpu, false)) { /* This should never fail. */ - abort(); + g_assert_not_reached(); } } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a82f5d5984b..b80313670f9 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6151,7 +6151,7 @@ static void handle_fp_1src_half(DisasContext *s, int = opcode, int rd, int rn) gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); break; default: - abort(); + g_assert_not_reached(); } =20 write_fp_sreg(s, rd, tcg_res); @@ -6392,7 +6392,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, break; } default: - abort(); + g_assert_not_reached(); } } =20 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 2e4d1ec87d9..321c17e2c7e 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -679,7 +679,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) } break; default: - abort(); + g_assert_not_reached(); } if ((vd + a->stride * (nregs - 1)) > 31) { /* diff --git a/target/arm/translate.c b/target/arm/translate.c index 050c237b076..4e19191ed5c 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5156,7 +5156,7 @@ static void gen_srs(DisasContext *s, offset =3D 4; break; default: - abort(); + g_assert_not_reached(); } tcg_gen_addi_i32(addr, addr, offset); tmp =3D load_reg(s, 14); @@ -5181,7 +5181,7 @@ static void gen_srs(DisasContext *s, offset =3D 0; break; default: - abort(); + g_assert_not_reached(); } tcg_gen_addi_i32(addr, addr, offset); gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745568; cv=none; d=zohomail.com; s=zohoarc; b=ZXl9eeVLu3SrRkv2rbhhOgEHGSNGYH4CF8ILpkF+qGG0t0WzBbPYTPiXLKHpH1AU2RQ5P5E4i9SDk02IPQ04auaMyEuNOg91aSJA8qtD8+mTMbla5P+uU34+4aHWIT1vsSLRZj7oKtrTIqph1pyTHkPEztjFxsHB11SFuOOYm3k= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.57 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=ArM5vDP/EbKZawRU57Aqm2WP6vjT8p7Zzo7XHj++yzg=; b=CjHMDuHYM8Nk/cP8pe5ZJtiSurn/naPnyefnFzK5ZTV/ajoCFkaArmGmNEj1Hwcb5M UwU0wWhJ+2vjcS7QbehH6b4vCcYkykQgn54/dDys3ye01kR0ammrph6mdGTKSA5BXUnr dOUc9m0RIH9VCUa7yG5WImBBBPBNGGiKvbP1NgbMbNOpomsVyfLLXjdGUWV/0JOh1azN 0e41K2VA/WwqnPzMCl4Bd/YNIVP8xb/Ti6wxFQy33Y2esaPinA6Po2pZaN12J+cceJgs mJ6sg0r2ZFjNTZSEX4orMbZBYVbmqCB90u2Mq3rp6WLk+w0Mxzo6Z6XNAwtiSJFH773p /ugA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ArM5vDP/EbKZawRU57Aqm2WP6vjT8p7Zzo7XHj++yzg=; b=lgbt3hwfwPkDg+php2ON7S8RZ2Vuvs3qdT3F3cZZ0zOyZiNYfn2gvzBb0qTBZ7wOfJ 3SlGLad9ocWLlz4DmdCSISuvAL2y6FOOZ3c902GbbuA2oUSpWv+kRvEFSPR3dfuFmEuD P/ahxmzM0rig5H9VYLbFYAuU5AnuniFdYP56xB9jIH9YtVK+z+FIFOTsP05i/gSOg5YA DJJmgavQQsnlOP++CvvI8Ct3SVqWLTNL1ZVI26+uahwFNFWct07po7XY08yaado28J+7 moXu1EFI5sxfQ2loVDcf26Sb/6BuEGgwBX9DCkmczw1jdMaZpO+Mpslpl3fdk3WAcwjA PDww== X-Gm-Message-State: AOAM531hvVZKaCPeOX6aJn0ag8fK4kY+q5vjfHeXkPgCIVmCmRJ0jzqo Pk4v13hY264NnkfqQgCHquwzd71t3dVUeQ== X-Google-Smtp-Source: ABdhPJxDpvMOoQjSoA8SlytKssm3LRBRgzAEtd69HIND31ZHVw4Ei/wZXWsmlif5iweLZHM2izSltg== X-Received: by 2002:a05:600c:3391:b0:393:fbba:3789 with SMTP id o17-20020a05600c339100b00393fbba3789mr3618049wmp.206.1651741918389; Thu, 05 May 2022 02:11:58 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 08/23] target/arm: Change cpreg access permissions to enum Date: Thu, 5 May 2022 10:11:32 +0100 Message-Id: <20220505091147.2657652-9-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745569377100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-8-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 44 +++++++++++++++++++++++--------------------- target/arm/helper.c | 2 +- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index ff3817decbd..858c5da57d8 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -154,31 +154,33 @@ enum { * described with these bits, then use a laxer set of restrictions, and * do the more restrictive/complex check inside a helper function. */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) +typedef enum { + PL3_R =3D 0x80, + PL3_W =3D 0x40, + PL2_R =3D 0x20 | PL3_R, + PL2_W =3D 0x10 | PL3_W, + PL1_R =3D 0x08 | PL2_R, + PL1_W =3D 0x04 | PL2_W, + PL0_R =3D 0x02 | PL1_R, + PL0_W =3D 0x01 | PL1_W, =20 -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ + /* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ #ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R + PL0U_R =3D PL0_R, #else -#define PL0U_R PL1_R + PL0U_R =3D PL1_R, #endif =20 -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) + PL3_RW =3D PL3_R | PL3_W, + PL2_RW =3D PL2_R | PL2_W, + PL1_RW =3D PL1_R | PL1_W, + PL0_RW =3D PL0_R | PL0_W, +} CPAccessRights; =20 typedef enum CPAccessResult { /* Access is permitted */ @@ -262,7 +264,7 @@ struct ARMCPRegInfo { /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ - int access; + CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ int secure; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 06f8864c778..a19e04bb0bf 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8711,7 +8711,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * to encompass the generic architectural permission check. */ if (r->state !=3D ARM_CP_STATE_AA32) { - int mask =3D 0; + CPAccessRights mask; switch (r->opc1) { case 0: /* min_EL EL1, but some accessible to EL0 via kernel ABI */ --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651742808; cv=none; d=zohomail.com; s=zohoarc; b=MdVM9Wlcy6UcX0FuKhRZC86u470mP6adz9W1ilBzAQyX839k98d6/y9DcFlDA/emmyagHIrs+ihWMGTbF5S/FNvNiYTSwg4GEdOOUPK/eUFCaBLciwwymV2gKDy9pRdi7X2of1dxKnuqrQ6MmMj+O62e1A9hpyqJ9KDEvQqZd58= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651742808; h=Content-Type:Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=N2UffwlLDOoC/zClIRs7vxRVjajQoB+uc9PlF30Umps=; b=heJA0qaWjFsTw6DirChf+soh/k8gnrmlzDE3OBnPr39dt3SU4diIQAAyF35ktfj+1BZvUl1tTrq3uzURz1b7ipxsEpPZ/5ybkzONE6v2xqPCRfOp+iy52+oTFKcAMvOkU9wQCtyCF8esvp78pDCK3P+9Pb+cs5AvDbxK9vIBnio= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651742808883836.6222836267019; Thu, 5 May 2022 02:26:48 -0700 (PDT) Received: from localhost ([::1]:51070 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmXl1-0006mW-Et for importer@patchew.org; Thu, 05 May 2022 05:26:47 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38584) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWk-00055A-7r for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:02 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:35728) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWi-0003Hq-KO for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:01 -0400 Received: by mail-wr1-x436.google.com with SMTP id j15so5248983wrb.2 for ; Thu, 05 May 2022 02:12:00 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.58 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=N2UffwlLDOoC/zClIRs7vxRVjajQoB+uc9PlF30Umps=; b=YtYd66k6pBaf1JcEAJdQEzT0zTti8Nu2hRbQ35Ev1CY14Y7ZXeLjF9tpdirNKhgHq3 9k6P1fRHhv4Dsye8LQV6gbxjZsIONEYOMluAjgdL3J+Jg6zNyF4YfHF6jImSNAwvvtYl 0hC91ZYHVajScp9mVHeuki58nnRcOgYct2oF3jKUJUhRVDupKT1ndEbMtigdDn7GxAun FpWeUt8zzgKU5wxEGbnsljEM7KHMU8oMXvMhkJJ11TQSGSLNLIXyUjSTs+eNlIq0z0I/ 8Kp9jKPltVNbdvkjA0TG151j6lppf3PhpRWkGnidEufM83qn21Km9kyyWHTYy+r2x8SJ PP0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=N2UffwlLDOoC/zClIRs7vxRVjajQoB+uc9PlF30Umps=; b=Afv2/boZ6o/QwxlARWRgpmQDRbnHBMiiecra0rZweOQdwFGrwCHPA73N5S6JEYXLUk 4ZyBpHnnQ5ZAVUMHNJg/3O1MqhD9npqMOV9ynlyiXfGccNKN6t/RYvaC2EyJHewc+PJm pTNIw2rRxtmfoM9YmuMFSczIY2AbXqv12jHItTGai7j3H17Bni1lNxrK6ERnPgdEg44O +882+C2rDlW4dwd4BcEB6w5jDoqy24qekR5lSG5pThbYvH+ae7xW6gx+PNiqgJf9RSPm 60zNmQnDxXw/czxA227ZufxTx7UJ2AoEQqfdDzaHk0CjHl7GT//y6xAgSboEpLYL02cF anAQ== X-Gm-Message-State: AOAM533DNGRuKJ5TLHZ8Np6qOBPhIpMca7KuiH/71oN+X9qcVQPmaxGE C4gvpiRJr/w+d/Kz5OtpiwpGSOJt2YkCCw== X-Google-Smtp-Source: ABdhPJxJc5wWBIAx1UADiKNNAlSq1zMvOYFNuru3VpP4WA7Ii7vOkwwGcKz8gVFIFlj5oRQhH0l6xQ== X-Received: by 2002:a05:6000:156e:b0:20c:5218:8907 with SMTP id 14-20020a056000156e00b0020c52188907mr19702720wrz.297.1651741919135; Thu, 05 May 2022 02:11:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 09/23] target/arm: Name CPState type Date: Thu, 5 May 2022 10:11:33 +0100 Message-Id: <20220505091147.2657652-10-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651742810206100003 From: Richard Henderson Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-9-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 6 +++--- target/arm/helper.c | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 858c5da57d8..4179a8cdd5a 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -114,11 +114,11 @@ enum { * Note that we rely on the values of these enums as we iterate through * the various states in some places. */ -enum { +typedef enum { ARM_CP_STATE_AA32 =3D 0, ARM_CP_STATE_AA64 =3D 1, ARM_CP_STATE_BOTH =3D 2, -}; +} CPState; =20 /* * ARM CP register secure state flags. These flags identify security state @@ -260,7 +260,7 @@ struct ARMCPRegInfo { uint8_t opc1; uint8_t opc2; /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; + CPState state; /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ diff --git a/target/arm/helper.c b/target/arm/helper.c index a19e04bb0bf..d560a6a6a92 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8502,7 +8502,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) } =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, int secstate, + void *opaque, CPState state, int secsta= te, int crm, int opc1, int opc2, const char *name) { @@ -8662,13 +8662,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2, state; + int crm, opc1, opc2; int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + CPState state; + /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); /* op0 only exists in the AArch64 encodings */ --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745800; cv=none; d=zohomail.com; s=zohoarc; b=aJXinDPoLC6bDSvcTtI6aF58zF4TeCMOK7qZV8FrtRoow+Mj3qLfzmvWhi28t/5FC52ZDl9At07/fFUaKqJlW1SLE+SJ/1psamefXl778Af/WgB94AZW1B5SCt+24FVfgQKBN9rNhABpCmSKK5dRhcBHLIBfet2NmH/KIjpKFko= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651745800; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=LaJS8axx1oTqwF/wDMx3/UUoY2E8r+rcnLggrj6DlFM=; b=UFiBSqbRhkZ1DXDydZ2mdXZ/RgF8CIuvnhO5Kx1IBeWtSaDUfzyvzoSDfnJBkfM0p6+CJ+03PjCVNzRCXAqnqzxxQf8kHkK8cpCHREoaEYOQt/jMiXsLMQ1Sfz3S3Kxaf72hdd8uztqsb27i4SpioZdOXPWnccT0wskbyaHmXyk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651745800688191.18185524087266; Thu, 5 May 2022 03:16:40 -0700 (PDT) Received: from localhost ([::1]:46266 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYXH-0003tB-Go for importer@patchew.org; Thu, 05 May 2022 06:16:39 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38612) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWl-00057t-6e for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:03 -0400 Received: from mail-wm1-x32f.google.com ([2a00:1450:4864:20::32f]:40512) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWj-0003I5-FZ for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:02 -0400 Received: by mail-wm1-x32f.google.com with SMTP id v64-20020a1cac43000000b0038cfd1b3a6dso4684163wme.5 for ; Thu, 05 May 2022 02:12:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.11.59 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:11:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=LaJS8axx1oTqwF/wDMx3/UUoY2E8r+rcnLggrj6DlFM=; b=WFDioX9AumiSFIPoJhI4z+r4amQuCBCyNKnkmLTxHeYIJSwTuYtlw3s4Q3zumXQFkP ghzpYJ2W28Fc+lNV7QVp5vdOXL9CIAQ+wVZNbAVhw1uRvKdE/L1Nj/LUIjBIvI2sn4y4 ptGGkQgTpJV3mxGS+fXFC8w1phRRICq4kVRrDukcEcgdGbSg4r067MBvqBbk2l1oWlj7 36AncHjzkB2r8EUREub2j5BzA+8wKEZkwnJTAAv1DhJ02oX3HyyDEzkYtcnsX7072BcL FKlM2N+vpjDe2Mg6ii65mkqJChx63kKxBl1ispNKFKBEjtxSYY7LjomJ8MZP/U01/juZ XRIg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LaJS8axx1oTqwF/wDMx3/UUoY2E8r+rcnLggrj6DlFM=; b=UsiQFrxpVCtBhPOplw7NbxLCgoeYYiIy6K8wlbbQCJhMwHh0RScGLZuvhHiCSigJPK WeugNrBSRqOZeFluhU/etumWAld3JLwUdtlsKmMDxj+ZCIdzXOAmmU+98MNyx9fhCHkg XwA3lt+Qs4Tws4BuR4s5t6A6mK90qeellYRYXG/G+sSnX7IKfAusfSjyMHt992fmqcaV oKLsDMTmDHrW/Dr3oY0X4FAqjwe//WI1Oin4xlZmEAjUBscCbuALX7UOtWrtpC8Xbk2O BTBRzC2GM4c//GetvIA9yUt2zr5QZJVt0uHlkkT2B9dlg8mchAkEdRXfi/xaDlKRN3yl CinA== X-Gm-Message-State: AOAM532agpDATwDF1TMgN6FUA2Rp8OThB8172MDD5ZJ2bNhf6TL8qtRA bM2yrkLZx0ZZdMWlDC3RskQwtHww/LFjDQ== X-Google-Smtp-Source: ABdhPJzXEWElt++ova98RIBEmGuR/5a2BN1/LSJGOJAT9ezNBYSFdVSTIQrL7vbuFG/PRdllecqH1Q== X-Received: by 2002:a05:600c:3b93:b0:394:57c8:5901 with SMTP id n19-20020a05600c3b9300b0039457c85901mr3608947wms.77.1651741919930; Thu, 05 May 2022 02:11:59 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 10/23] target/arm: Name CPSecureState type Date: Thu, 5 May 2022 10:11:34 +0100 Message-Id: <20220505091147.2657652-11-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32f; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745801175100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpregs.h | 7 ++++--- target/arm/helper.c | 7 +++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 4179a8cdd5a..73984549d25 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -131,10 +131,11 @@ typedef enum { * registered entry will only have one to identify whether the entry is se= cure * or non-secure. */ -enum { +typedef enum { + ARM_CP_SECSTATE_BOTH =3D 0, /* define one cpreg for each secstat= e */ ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; +} CPSecureState; =20 /* * Access rights: @@ -266,7 +267,7 @@ struct ARMCPRegInfo { /* Access rights: PL*_[RW] */ CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; + CPSecureState secure; /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/helper.c b/target/arm/helper.c index d560a6a6a92..50ad2e3e37b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8502,7 +8502,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) } =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, int secsta= te, + void *opaque, CPState state, + CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -8785,7 +8786,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->secure, crm, opc1, o= pc2, r->name); break; - default: + case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, @@ -8795,6 +8796,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); break; + default: + g_assert_not_reached(); } } else { /* AArch64 registers get mapped to non-secure inst= ance --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651746229; cv=none; d=zohomail.com; s=zohoarc; b=R7LFYBrL5hgng/58zS/+T1IQh8jNRXdQizWY04Dn2C2KXGDQ5tj56wcHgnIAAEsFkDy8q6LEJCxEr+t4oDSoXcyhrleaS+u1NHPphbsYC+jmvGaMwL4PjQNs5zD8SJzxw7dJ/QOgGXoLvVCzdD5uV670L+15QtVi6FIBL3UacFg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651746229; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=WcGb4SYoeOpCKBA3Iri0N3zedF8sXwlwuq0AwAakMGQ=; b=mb+yHoHXWPWyj56VPetS70PE5wTiHTL8bfu41Cunu77JKkBr13b/X1Up2iDevqUhHTYDw2AbjGQpRzpbxS6bzpRozPhttaMD+QuQlb8lnxv52YWZXteDXvQvhPWUjO4AjHJBk+kNeyt9LfHdhnbm2sj+McKcwd244hFQ4d3zvgg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165174622981970.434145671961; Thu, 5 May 2022 03:23:49 -0700 (PDT) Received: from localhost ([::1]:57178 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYeC-0003Tp-OX for importer@patchew.org; Thu, 05 May 2022 06:23:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38630) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWl-00059P-Qb for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:03 -0400 Received: from mail-wm1-x32e.google.com ([2a00:1450:4864:20::32e]:37490) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWk-0003IE-62 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:03 -0400 Received: by mail-wm1-x32e.google.com with SMTP id o12-20020a1c4d0c000000b00393fbe2973dso4709153wmh.2 for ; Thu, 05 May 2022 02:12:01 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=WcGb4SYoeOpCKBA3Iri0N3zedF8sXwlwuq0AwAakMGQ=; b=o9gsUH2dezjCiILvHhVjOm5314mwxH8xeSLTI+qdjVJCYlb//n03U7T51rsB90XEz2 nQPlrPyfNrE78sE6f0uA/rls0lzTkbQlU157F0/EZF1c42A8Dpad7dTUAjh8iF2517gJ 7iqIjGTv9a0qQTu31NUNU64qp9hBWiyHJl56IdeFbUyhHeyq/w2cKd7w1MnqKu8DcVTS Qtvu9iQwLWF7oROSLEJi8nXNUQ0Uk0qJ3mWhyoCbYq3F6B8ofwPOl6KEPvkm3bjWlSWs ELCy1o3z7FRzuKFG0Kt/AGoYW19E8lpGw2P1vdHZa/7QxXnyBcmtja4U6vxQeD6UI8Nu gcPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=WcGb4SYoeOpCKBA3Iri0N3zedF8sXwlwuq0AwAakMGQ=; b=TTP2eJiL5EFQLeiKYvLr4kjDJKo54Gc85wqoPkRtOLnb01n01yTxmpBS0YoeybTAE1 vw/nFbg7+SBQ9wpffSeU8TwExyEjzkZX8OfBxoQxNlDe7tXtAlMBTFmEt2zRJQXq0NtP uoZFymyxCX5FmG+0KqwnUMgMM+WG1ktz8RMby0nQDWQCNgDA7Hks8y5vvHrcNWbJooWX +uIMxQ1+IDSgxBtNyU7uwgsV4YhEg2rGZhbg9rZ4hSqoLrrH0Jqo5ls9HP5cnXlYvyGQ XytEBzVCbN4R4zFFxexJb4PeZJO/sNxrcGyl7UXCumqGWSgvql9UFtYYicVCwThs7SwY IEcQ== X-Gm-Message-State: AOAM530CVnCqCb5g4ssUY+CD/LAQ6ijWdJu3DsSvOfGhpBILramMT4JP OkBWqvx4gq7UlK46TDQMN2ndfnGsv6hV0w== X-Google-Smtp-Source: ABdhPJxkIjRWJdUQqZCxAC1wvVbKNKeIBV+KpErgJnNFmWNP04thlT/DFgXILe87iel7sRDyRM9BmQ== X-Received: by 2002:a05:600c:4ecc:b0:394:3222:23be with SMTP id g12-20020a05600c4ecc00b00394322223bemr3517218wmq.175.1651741920685; Thu, 05 May 2022 02:12:00 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 11/23] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases Date: Thu, 5 May 2022 10:11:35 +0100 Message-Id: <20220505091147.2657652-12-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32e; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651746230663100003 Content-Type: text/plain; charset="utf-8" From: Richard Henderson The new_key field is always non-zero -- drop the if. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-11-richard.henderson@linaro.org [PMM: reinstated dropped PL3_RW mask] Signed-off-by: Peter Maydell --- target/arm/helper.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 50ad2e3e37b..70dc1482dd7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5914,7 +5914,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg; + ARMCPRegInfo *src_reg, *dst_reg, *new_reg; + uint32_t *new_key; + bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; @@ -5933,19 +5935,16 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) g_assert(src_reg->opaque =3D=3D NULL); =20 /* Create alias before redirection so we dup the right data. */ - if (a->new_key) { - ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); - uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); - bool ok; + new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); + new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D PL2_RW | PL3_RW; =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); - g_assert(ok); - } + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); =20 src_reg->opaque =3D dst_reg; src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651746935; cv=none; d=zohomail.com; s=zohoarc; b=jpwtqu/8GaJpeLnhnuWBBbITvSmGylBVBHR32XpkOGnf16aH2ZjdRXrQjBHI1gOi1pMrwDC0eIJVv+JiQTQUgCSLQDLf1xz0gfroiNFxLcvZiWLejDvwAa9gBRAILhalVYrdzVu1J0mGI5SurYru8KVmV2n8Qs++NzDw9RGKhVY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651746935; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=RGoRBcklgW4bJquVq1HVnNxC0lCcDz2r+Ent1cSjiow=; b=WomcdjehmNrzuSh5Xy43ZybBA4skumrh4UZWk+xVEpIfIZT2PsmIGZpzLrPvsISHDdxsK0hLmfR8WVCoANo3pchVK4QztgQcBfpvtjPAIV8OLd9iI6dgFFsAv44UCgFn7H/dGR3zNUZUtJnaNBPleGFgoFVIH3/sj1ZRsBsk4Dk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651746935023881.9364320706065; Thu, 5 May 2022 03:35:35 -0700 (PDT) Received: from localhost ([::1]:42500 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYpZ-0005TK-Gn for importer@patchew.org; Thu, 05 May 2022 06:35:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38666) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWn-0005CF-Dy for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:05 -0400 Received: from mail-wm1-x32b.google.com ([2a00:1450:4864:20::32b]:33105) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWl-0003JU-1A for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:04 -0400 Received: by mail-wm1-x32b.google.com with SMTP id p7-20020a05600c358700b00393e80c59daso3670512wmq.0 for ; Thu, 05 May 2022 02:12:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.00 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=RGoRBcklgW4bJquVq1HVnNxC0lCcDz2r+Ent1cSjiow=; b=Bd5T2xG5WGZINCoCQxJNO0PuTvDedEJoypoyE5V5SOr6qBqI6OuS48lcZgr+q2w1nP o1jr3rTjn9+0OQh0hDbQaX/ApPRLwQQvnDbbH03v2yR2VBWwXwF3Tyi5UvXwY1GYjA2F zZYsC9CZEkd7VuuckN3nv3QaPMpdiXv9BV/NJ8OM/0+78qAedXDaJBDvAzyesjStGSbu dUmtpHnr2BN+1InO9WqjTqFd0XOPgZaZawyy/3LcuIYUztnvo4LBk+a9kSQmD+f13aN2 pYskQivX99chLEysRJHq0jSS8Aavix/HRs/mCvcczqI4Xhx6Ke+fj0Sf6ENkTkAvc8YQ rEzQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RGoRBcklgW4bJquVq1HVnNxC0lCcDz2r+Ent1cSjiow=; b=R5ttYUNeakUI9y04+vRNTzZS1wOUzq/pm3W0rmcAFwbbHzFx2JPxvXtEkeYJ6M+ytu ER3aIPvhcVL6W942qV5G7dQyFqQtGLfB0w/4r2mGpLFf6VIJ+51VFmQOvISbDSZojG0X 4Yxx4IyfV72p0wf4SW5YTxkOgpc8VZmQKdAh03njNlzf1Hkn3w/cfgwqUBIBrfTyCbez vCr/bXBbI1jlYwrvd+M/7D88k5TEVGfnYvMeNVgdyslrST1Rw9flERmJuLU7TGpZ0aoe 7SqCuSAC71gsIWkqYIvFd9jgB1gEghmclt+Rd34yk6nZLyUjGE2VKJGQcxkqJRamSsLg jVBg== X-Gm-Message-State: AOAM531yNAqXMJ5ehf58rCFRFfpdUpoPFErcPMXFeVOTbT/unG4p+VA5 GQ26K1+pliglj0OK2cbIrL1g1Lxh6Wz4bQ== X-Google-Smtp-Source: ABdhPJyfJCXaEGHRb5RPggIG4Hw9g3oRafusw7iZ1L7OyDsvXcky/MlTVIFBtLiA1tpU0ApCHoWCpg== X-Received: by 2002:a7b:c24d:0:b0:393:fac9:3015 with SMTP id b13-20020a7bc24d000000b00393fac93015mr3545227wmj.186.1651741921514; Thu, 05 May 2022 02:12:01 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 12/23] target/arm: Store cpregs key in the hash table directly Date: Thu, 5 May 2022 10:11:36 +0100 Message-Id: <20220505091147.2657652-13-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651746937992100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Cast the uint32_t key into a gpointer directly, which allows us to avoid allocating storage for each key. Use g_hash_table_lookup when we already have a gpointer (e.g. for callbacks like count_cpreg), or when using get_arm_cp_reginfo would require casting away const. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-12-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 4 ++-- target/arm/gdbstub.c | 2 +- target/arm/helper.c | 41 ++++++++++++++++++----------------------- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index a7cd692010c..602c060fff7 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1090,8 +1090,8 @@ static void arm_cpu_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); - cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, - g_free, cpreg_hashtable_data_dest= roy); + cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, + NULL, cpreg_hashtable_data_destro= y); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f01a126108f..f5b35cd55f0 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -273,7 +273,7 @@ static void arm_gen_one_xml_sysreg_tag(GString *s, Dyna= micGDBXMLInfo *dyn_xml, static void arm_register_sysreg_for_xml(gpointer key, gpointer value, gpointer p) { - uint32_t ri_key =3D *(uint32_t *)key; + uint32_t ri_key =3D (uintptr_t)key; ARMCPRegInfo *ri =3D value; RegisterSysregXmlParam *param =3D (RegisterSysregXmlParam *)p; GString *s =3D param->s; diff --git a/target/arm/helper.c b/target/arm/helper.c index 70dc1482dd7..2bc81dbc5ec 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -214,11 +214,8 @@ bool write_list_to_cpustate(ARMCPU *cpu) static void add_cpreg_to_list(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + uint32_t regidx =3D (uintptr_t)key; + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); @@ -230,11 +227,9 @@ static void add_cpreg_to_list(gpointer key, gpointer o= paque) static void count_cpreg(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; const ARMCPRegInfo *ri; =20 - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + ri =3D g_hash_table_lookup(cpu->cp_regs, key); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_array_len++; @@ -243,8 +238,8 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) { - uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); - uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); + uint64_t aidx =3D cpreg_to_kvm_id((uintptr_t)a); + uint64_t bidx =3D cpreg_to_kvm_id((uintptr_t)b); =20 if (aidx > bidx) { return 1; @@ -5915,15 +5910,16 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - uint32_t *new_key; bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; } =20 - src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + src_reg =3D g_hash_table_lookup(cpu->cp_regs, + (gpointer)(uintptr_t)a->src_key); + dst_reg =3D g_hash_table_lookup(cpu->cp_regs, + (gpointer)(uintptr_t)a->dst_key); g_assert(src_reg !=3D NULL); g_assert(dst_reg !=3D NULL); =20 @@ -5936,14 +5932,14 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 /* Create alias before redirection so we dup the right data. */ new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 new_reg->name =3D a->new_name; new_reg->type |=3D ARM_CP_ALIAS; /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ new_reg->access &=3D PL2_RW | PL3_RW; =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + ok =3D g_hash_table_insert(cpu->cp_regs, + (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); =20 src_reg->opaque =3D dst_reg; @@ -8509,7 +8505,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. */ - uint32_t *key =3D g_new(uint32_t, 1); + uint32_t key; ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; @@ -8576,10 +8572,10 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { r2->cp =3D CP_REG_ARM64_SYSREG_CP; } - *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, + r2->opc0, opc1, opc2); } else { - *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); + key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); } if (opaque) { r2->opaque =3D opaque; @@ -8621,8 +8617,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * requested. */ if (!(r->type & ARM_CP_OVERRIDE)) { - ARMCPRegInfo *oldreg; - oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { fprintf(stderr, "Register redefined: cp=3D%d %d bit " "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " @@ -8632,7 +8627,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, g_assert_not_reached(); } } - g_hash_table_insert(cpu->cp_regs, key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 =20 @@ -8864,7 +8859,7 @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, = size_t regs_len, =20 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) { - return g_hash_table_lookup(cpregs, &encoded_cp); + return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); } =20 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651746591; cv=none; d=zohomail.com; s=zohoarc; b=IX2l4tizmn7uaAPyhUsAQEm2cUjo1gPjWHyrx3Jm0u0q/0yaDguvXwBep7IzD2cZUqC/BSsN2mcchMXkLOugqDWyQ3RByrmpYQk78kmSGSqlr2d9tgq5A90dylL4snesm7vWBVqiI24EeHfgffegWA1NJQnUK3DrjVQXlGf4Yxg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651746591; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=SjjyaPs6OMir0qoBbc7kdJL63HtWlrJst0Uy7ZOsTsk=; b=TTx2zkGzOPlrz2GPKRXgNq9nRwjMjlzygH3nkfjverSyfmCC03HIxqVWLqZkX3AZ0YiwNf7LZtM2etWLCCM5OH98nAhstV4D2mydWhTOeseoruDImxd6pC4d7zL4rOjlQ3Y0yx3vfQ2Yt2VPlIDJX6eoQwJFCTkjx0VCOyH21I8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651746590867223.51026391667983; Thu, 5 May 2022 03:29:50 -0700 (PDT) Received: from localhost ([::1]:36034 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYk1-0000IT-Dh for importer@patchew.org; Thu, 05 May 2022 06:29:49 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38664) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWn-0005CB-CJ for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:05 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:39690) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWl-0003C1-6Q for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:04 -0400 Received: by mail-wr1-x436.google.com with SMTP id d5so5217645wrb.6 for ; Thu, 05 May 2022 02:12:02 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.01 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=SjjyaPs6OMir0qoBbc7kdJL63HtWlrJst0Uy7ZOsTsk=; b=XhGUE1qiNtk50sHhwvlqPT2YlWr7g7Szn1wqBbaZpDaDgFTyrj7nGnBOzf3Nf30EkO ADjVq22yTkYcg/25QBUd5CWhiutBFxK1aY5gi2LnLJoQHyNmMn0VXXtNNSlkHjeb4iiw vY+JuQXWFlrT0E6WFDqktkHiBh12EOO2ZFkthN9bp+wsnYoRlIwxaX1mS4yef7u4WM77 6I0vXZljzs+HZ6IwTsKhYbp92Sy8kbYHnWbTDKAGHCru2Qzj78GjmmKNRv/JgxKPQFvV kJhp5NXdacbnyDwATvhttYgKQFMO95RpAb6mpq+QGygCquPmZOVYEsSqw5uugkPw3gKC XEJw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=SjjyaPs6OMir0qoBbc7kdJL63HtWlrJst0Uy7ZOsTsk=; b=EgxseGn4qYmyDYyvO654ptGAdGbe/6VzOyNLviYmV4so2tKYbz4qdAMnCrbXR+TJg1 vHRrn0Qr8QUXd7/hE1kvN3GErqQOQD5bN/SyZ1YafYeySq4IXz/3Ah0Yx6QqLAXpgB9W cnO8frUuAkFhMa1qHv7n9htiWAWu0MGB0xrelzjccHIABhury1+wiPlV7GXfZld9dWCg HrBeSRg8F3ErxE0TAJUFFVMzmcMJ0A1uTFMpfoNiwiJ19hONK5ictxXPUnfMB5P/HbRk Xy16KU7tBVV2ZK1ktX4GCduoE2p+NwrBN/s0gnxMnOIpM4qkfUSAs2UA9jGa+3eob3oh 7uBw== X-Gm-Message-State: AOAM531jJ8P9iIf/WpiKhFJVGBOSbEQKElXtGbWZXriJEkWr/E21KwzH bvy7gXrppAGOqxc/XSpNfV1uDOD9Z6e/cA== X-Google-Smtp-Source: ABdhPJzf9uOES74xHr8eU/FagYNiz9B9c7HVrM5QHZXXVMz3nBLgLk5p1uWzvsC5ty1ZtqeTvvssJg== X-Received: by 2002:adf:d1e7:0:b0:20c:61a7:de2a with SMTP id g7-20020adfd1e7000000b0020c61a7de2amr14896318wrd.332.1651741922299; Thu, 05 May 2022 02:12:02 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 13/23] target/arm: Merge allocation of the cpreg and its name Date: Thu, 5 May 2022 10:11:37 +0100 Message-Id: <20220505091147.2657652-14-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651746592499100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Simplify freeing cp_regs hash table entries by using a single allocation for the entire value. This fixes a theoretical bug if we were to ever free the entire hash table, because we've been installing string literal constants into the cpreg structure in define_arm_vh_e2h_redirects_aliases. However, at present we only free entries created for AArch32 wildcard cpregs which get overwritten by more specific cpregs, so this bug is never exposed. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-13-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.c | 16 +--------------- target/arm/helper.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 602c060fff7..01176b2569f 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1071,27 +1071,13 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } =20 -static void cpreg_hashtable_data_destroy(gpointer data) -{ - /* - * Destroy function for cpu->cp_regs hashtable data entries. - * We must free the name string because it was g_strdup()ed in - * add_cpreg_to_hashtable(). It's OK to cast away the 'const' - * from r->name because we know we definitely allocated it. - */ - ARMCPRegInfo *r =3D data; - - g_free((void *)r->name); - g_free(r); -} - static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, - NULL, cpreg_hashtable_data_destro= y); + NULL, g_free); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/helper.c b/target/arm/helper.c index 2bc81dbc5ec..d92fd23445b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8506,11 +8506,17 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, * add a single reginfo struct to the hash table. */ uint32_t key; - ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); + ARMCPRegInfo *r2; int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + size_t name_len; + + /* Combine cpreg and name into one allocation. */ + name_len =3D strlen(name) + 1; + r2 =3D g_malloc(sizeof(*r2) + name_len); + *r2 =3D *r; + r2->name =3D memcpy(r2 + 1, name, name_len); =20 - r2->name =3D g_strdup(name); /* Reset the secure state to the specific incoming state. This is * necessary as the register may have been defined with both states. */ --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651744854; cv=none; d=zohomail.com; s=zohoarc; b=IXqa6avJ49O6VEuseYp3tUHaT0VHrC6G2LE5A6Z/NLRyh2tW410mH2ysr2+K2o2Dt4OcimM3ZjhIcLpHv6kMcw7QECzF8oMV2INDvyYGeoW8uSV2a9pl8Jf6im2CA4MKo6TgsNI9o6e9IT4dPuuk13EpftKvb5WWurSLRr5oOLk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651744854; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=Gw9AdCbfVxgEkULN3gOVJuvRjbon3y1ncll8PnUnHtE=; b=morScIydlBxYQrokiWiMnV6RkrJj3L+dnxUNj34Ov6OI9UpkQh8XDwKQioJ9tMOrn/ILggWpWswUO+pWyB9sHiaeNVsFWRuk4xjxTxkl3UHhEgqA7MMZrA7YXiF0XhcB1sRe0hrcLXkPJZCI0N8uEfFTas1iHwczAFKuIXmg2AY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651744854238371.54649440507876; Thu, 5 May 2022 03:00:54 -0700 (PDT) Received: from localhost ([::1]:46528 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYI0-0000uA-VI for importer@patchew.org; Thu, 05 May 2022 06:00:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38706) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWp-0005Dk-3t for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:07 -0400 Received: from mail-wr1-x433.google.com ([2a00:1450:4864:20::433]:43765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWn-0003LF-3g for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:06 -0400 Received: by mail-wr1-x433.google.com with SMTP id v12so5207350wrv.10 for ; Thu, 05 May 2022 02:12:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.02 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=Gw9AdCbfVxgEkULN3gOVJuvRjbon3y1ncll8PnUnHtE=; b=qrO23VvpfEVqJBPfTqjwby9GcLUy69XScSBYWWNiWvediHZGS6byvTuIdh3GaZpLG9 G6j939US0o0ydbliFK23KmTA4fd3d8s7EL1WENVwQORQKA5uOwl5lC2cg40iUjezhGjl gss3J2ybRBIxZ26tPOtFhqzifYn06G9XY6tFaxByv3miGIVK+6dAymTppwkHWKH/YjP2 NeUQ+dpANnD8mgogvFBYg8fonAPNwhyHKMj4ov8a1CD5dAzw8xItekt03+U6eof9FjEz Gmvtv74JMZKs7lXhH00UAsC1S0L/+CTwLvB2KPQO/cTiEtZmwGf9wXiGf0GX8ElffYNm qmpg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Gw9AdCbfVxgEkULN3gOVJuvRjbon3y1ncll8PnUnHtE=; b=llHFiUVllbcfzqVgkUfJBJKQxE7a41X+t4AL0HPUqU7lN4lEHrGDPik3IllxuMMQ0L 17EFD1N8Ge4PsM1BiIkVcgz8R2KVQkpMAllT/bdmueZhxzqgMvUf6JlCNHYrhHRuXEm7 d6UjKK5YMPjTr+A8ChahedAjlTVX1YnlXq/DH3ipmmnfEkdKUExyqaSa2jt/dQRsPNcL iJbghE5az82fWdEMsHgi3YlGF61BYEp9VlWFF5BrkJY2zUpvUL6ducYz+1bVdrhPMl79 1UhX5+A2Gg6jvVocdvmGqCjKbWyBK3eHzk4GP2fdt54JtiqRwavaE+bbyK4PEinzAxNJ uWlg== X-Gm-Message-State: AOAM533dt6zxGiF1WxJuBUychWnBB3iak2xA1UIndZz+qwoizXLhNfy+ WExw12ow3ZxtPfexCUM45yB3pWN0J+Tf7Q== X-Google-Smtp-Source: ABdhPJwu0DSwwhty/Usi3/17XZzn2MoSaKcBEHO8MnGWO2O1h1kmZOOya0e2IrCDcQMkfTA21QOUKg== X-Received: by 2002:adf:c64c:0:b0:20a:79c7:4bf2 with SMTP id u12-20020adfc64c000000b0020a79c74bf2mr19535617wrg.587.1651741923086; Thu, 05 May 2022 02:12:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 14/23] target/arm: Hoist computation of key in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:38 +0100 Message-Id: <20220505091147.2657652-15-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::433; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651744855141100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Move the computation of key to the top of the function. Hoist the resolution of cp as well, as an input to the computation of key. This will be required by a subsequent patch. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-14-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 49 +++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index d92fd23445b..cbc873e3e60 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8509,8 +8509,34 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, ARMCPRegInfo *r2; int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + int cp =3D r->cp; size_t name_len; =20 + switch (state) { + case ARM_CP_STATE_AA32: + /* We assume it is a cp15 register if the .cp field is left unset.= */ + if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) { + cp =3D 15; + } + key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); + break; + case ARM_CP_STATE_AA64: + /* + * To allow abbreviation of ARMCPRegInfo definitions, we treat + * cp =3D=3D 0 as equivalent to the value for "standard guest-visi= ble + * sysreg". STATE_BOTH definitions are also always "standard sysr= eg" + * in their AArch64 view (the .cp value may be non-zero for the + * benefit of the AArch32 view). + */ + if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { + cp =3D CP_REG_ARM64_SYSREG_CP; + } + key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); + break; + default: + g_assert_not_reached(); + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8554,12 +8580,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } =20 if (r->state =3D=3D ARM_CP_STATE_BOTH) { - /* We assume it is a cp15 register if the .cp field is left un= set. - */ - if (r2->cp =3D=3D 0) { - r2->cp =3D 15; - } - #if HOST_BIG_ENDIAN if (r2->fieldoffset) { r2->fieldoffset +=3D sizeof(uint32_t); @@ -8567,22 +8587,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, #endif } } - if (state =3D=3D ARM_CP_STATE_AA64) { - /* To allow abbreviation of ARMCPRegInfo - * definitions, we treat cp =3D=3D 0 as equivalent to - * the value for "standard guest-visible sysreg". - * STATE_BOTH definitions are also always "standard - * sysreg" in their AArch64 view (the .cp value may - * be non-zero for the benefit of the AArch32 view). - */ - if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - r2->cp =3D CP_REG_ARM64_SYSREG_CP; - } - key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); - } else { - key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); - } if (opaque) { r2->opaque =3D opaque; } @@ -8593,6 +8597,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, /* Make sure reginfo passed to helpers for wildcarded regs * has the correct crm/opc1/opc2 for this reg, not CP_ANY: */ + r2->cp =3D cp; r2->crm =3D crm; r2->opc1 =3D opc1; r2->opc2 =3D opc2; --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651747109; cv=none; d=zohomail.com; s=zohoarc; b=oKblFR1uUqfwhzgBpJeU3+a4+Irmo8u7FlVbO8sNu2T2u03DWAydm6VG9cbMkUkzzUjtaJVWU++Qh3I7ZU88qcV6oqrSdcai5m93tjvjUMY2Z1/lPumiEpvEKL9JKEigPB9ya5dsDEvA99O9CIYorbsNpGdIHBVkg9nxvuOdzhg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651747109; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=cBRWuGW1oEM07qzwDlQeqzeKAnOLvL3dCwuFE/tT94s=; b=WaGJs1PHHFI25VI3dHGXTL+bGuP4i3tFhOyDTGmrTL7gc9MKxnIaFZAi1puARylBYLX+vk+DRauAtgHfZIckpuZH3AEp8u3S4MEb+XSzoDW9+574lyNZTozp4ZJSJFzrKvSJwZ/FreF6FcqOV7xkjOTkuIjGO8iRjZky6SBG+ds= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651747109145167.7174292208142; Thu, 5 May 2022 03:38:29 -0700 (PDT) Received: from localhost ([::1]:49014 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYsN-0001pj-O6 for importer@patchew.org; Thu, 05 May 2022 06:38:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38704) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWp-0005Di-3N for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:07 -0400 Received: from mail-wm1-x329.google.com ([2a00:1450:4864:20::329]:52032) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWn-0003Hd-4F for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:06 -0400 Received: by mail-wm1-x329.google.com with SMTP id q20so2247239wmq.1 for ; Thu, 05 May 2022 02:12:04 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=cBRWuGW1oEM07qzwDlQeqzeKAnOLvL3dCwuFE/tT94s=; b=RpQT4ZPj3XLPLQnLT5FHpfIFCL6CGVRBLwta0hR8EptMxLzkw1Wrkr1pLcY4O69KOU jpdZhJkLPxQXTiQ6uIHQ0dsZAYdCf96/lsUx5zVQE1pmrrUJYFAn7PJkHloUrg2cCNgn wtdS8mpxtdruydjRUoxBwlHOrZaB2dX4G2VAkpWluXFSquvlvJyop4kYzOddSGivXcvZ 65rb2BQQKh0UjOO7jXdEp+rXiqgiHzLlLDy6yZOg6tdjv83H+BPqLFz56MClDJXyoIVH v81VgVH1XW012ARh46qyQHX3grI4ud4eEfkRKu6auiJJ7B8LA6JbWcWMR/i/86hBntmq Gxog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cBRWuGW1oEM07qzwDlQeqzeKAnOLvL3dCwuFE/tT94s=; b=u3CILVkDmD0niJk8pwxwK535gckeJC3AURRBzyHV2FiWFTM5vZGKP6Wqb7OCAQl0li IkwZ2joy6yfudNd4H+8oxQUxd6ep61tqPGNF0dlxzhHTc3EuCNxyYlOYmaVL88PdGN/x iY/LR1RzmCBLslp+NLz3HtKdoGKYrtODjnNlz37eAjSsSlA9UkLOmbQuYEGyFATcHeEU fYQOrhjPsTwgAhoVMMSk9lXY/IHnt4E7emsYmHR25fkGXcE63a8iYDbpM4OCGkB/ZwQM u0fbSntz06aqsEwFJQmKmS5smtWf6N12zZpq03CeUhWRvlEEbJERBjszQsUTyeq5MGF+ 4j8g== X-Gm-Message-State: AOAM533uRFZDAzo1D+GOjshK113efmedP7qUHmsWeLNZUw++u1NDJ/nR sbcFNDKSNuqPEDcn88k3LoCSVqXEFE61fg== X-Google-Smtp-Source: ABdhPJy2GsRp7P+ytDA8et1hr84yKg+sQLX4EmkM1/rQnW27xeACfwUlqL+Grma+H+S2bSHHPLoiBQ== X-Received: by 2002:a05:600c:4e06:b0:394:56be:19c with SMTP id b6-20020a05600c4e0600b0039456be019cmr3532434wmq.168.1651741923791; Thu, 05 May 2022 02:12:03 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 15/23] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:39 +0100 Message-Id: <20220505091147.2657652-16-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::329; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x329.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651747110604100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Put most of the value writeback to the same place, and improve the comment that goes with them. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-15-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index cbc873e3e60..8ee96d5c042 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8543,10 +8543,19 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, *r2 =3D *r; r2->name =3D memcpy(r2 + 1, name, name_len); =20 - /* Reset the secure state to the specific incoming state. This is - * necessary as the register may have been defined with both states. + /* + * Update fields to match the instantiation, overwiting wildcards + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. */ + r2->cp =3D cp; + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + r2->state =3D state; r2->secure =3D secstate; + if (opaque) { + r2->opaque =3D opaque; + } =20 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { /* Register is banked (using both entries in array). @@ -8587,20 +8596,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, #endif } } - if (opaque) { - r2->opaque =3D opaque; - } - /* reginfo passed to helpers is correct for the actual access, - * and is never ARM_CP_STATE_BOTH: - */ - r2->state =3D state; - /* Make sure reginfo passed to helpers for wildcarded regs - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: - */ - r2->cp =3D cp; - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; + /* By convention, for wildcarded registers only the first * entry is used for migration; the others are marked as * ALIAS so we don't try to transfer the register --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745168; cv=none; d=zohomail.com; s=zohoarc; b=KDm63vOs6JNwjp8dAbc6pTQrcachTj8FIa48ehwifvv+0eTzh38mtVmv1MkZlA/WfV3lBp3wM0Bcm1sWyCXx0ytHqfuc/t1T4u3As/ByUqIlQpEjGeEz2FlGtABZRG4LCdstyCVwfV4YqIu3LQeuYFBvRSBwPcsJS5GK11GwuQg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651745168; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=0QUzI2/FD81tuRNLLLXX+GyatmmpQmLOhxx+o3WhZiE=; b=JwlcHWZZaIh6YYHkBIYXbAmTV/xoKGXhPiZXWjIkyWye0zDXYRrgqkvVltLAZsPm3Yw5u88ttX5OVi4Y5hHp3zJV9sa9yGw9a5Czf4uy8IqGC9w7z4fnF8xt5yATp4SPkOk42KG5wwoh0CvyUmHHlB86xLs8O9lH2YfeT1D1EY0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651745168296369.5083353383478; Thu, 5 May 2022 03:06:08 -0700 (PDT) Received: from localhost ([::1]:55030 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYN4-0006yy-PH for importer@patchew.org; Thu, 05 May 2022 06:06:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38730) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWp-0005FG-T0 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:07 -0400 Received: from mail-wm1-x331.google.com ([2a00:1450:4864:20::331]:43667) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWn-0003HP-EJ for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:07 -0400 Received: by mail-wm1-x331.google.com with SMTP id r1-20020a1c2b01000000b00394398c5d51so2243166wmr.2 for ; Thu, 05 May 2022 02:12:05 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.03 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=0QUzI2/FD81tuRNLLLXX+GyatmmpQmLOhxx+o3WhZiE=; b=SbANoYQJFLLJ3c8jbLidGtYUk+tVGDnAHYHFP53ilfZawv2sexopLVJJcG1vJSUgbo uwJ1EL4Ag9aakIeSJ408fPu/h1eS5LbLiSKce9Hcnj/WTEyzzf/GKmKz2sEjdmZOSfsl el5T+3hUZTgdK8Difd4PC/h9XuG4ohnC3hKwGOrto9r3pvOphyfY+sM7BnQIzSsqdlz0 lH21RevOOcKEHiwBjPSoDIxz8VZbvZ6yDO6lEKmc2vafG1RGLd+YK8xPw+wWRpm1cWYg X/f411vhsF+gLHKnmToe3wAQgWvIEb1gK616lzROPqfHMNdhQ8y6EOGUFUdQsjoJQKru P9rQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0QUzI2/FD81tuRNLLLXX+GyatmmpQmLOhxx+o3WhZiE=; b=hTNqztVeN4m5jd2/C+7TqQGqttwO0Vx5RJEeWcH9E4U5LuQ0ap4nXqTZ/QxkVx1Djb xyd+NrtGT7QxBx5ghlZNRdsxBDjE2HnJBF6NXfq4uEjx+Mf8U2LVYNdBL4k0tOZ0rq4b jINFGGOxmWNCEQBp5c53Rza0bfFaG1NovOKn7Qgd7MnOWx6MlRVxFSmfjLFnXVbOQoFJ PzT6YQhqUXKoXWrmQmKN0kQN5NeeWp2/8N1cvf6N4PlZUXZjikfLzAmUUlctl6vHdkWQ ed/kZ2A2LlIm8Mr4Zx9AeONnXIYI0P+ZMJkh5vAxEnw4AoCpNIK4W2K7lzlxxcLbt0KU hC0g== X-Gm-Message-State: AOAM531wtvds6m8ZjM/MAi6XfdrCVZuQDz1+SY6ZowNNcbCdUdg1LRSF HNCi0f5cJ5gwixSkj3/9cZueIUaUdiTmiw== X-Google-Smtp-Source: ABdhPJz5Kec+w4le8b3NITX3D51pfgNHsNyl03vaJCSDSEU/dYgYp9C20Tu3AQDP5LB15bNywt4jew== X-Received: by 2002:a7b:c095:0:b0:393:fd2e:9191 with SMTP id r21-20020a7bc095000000b00393fd2e9191mr3587417wmh.137.1651741924565; Thu, 05 May 2022 02:12:04 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 16/23] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:40 +0100 Message-Id: <20220505091147.2657652-17-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::331; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x331.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745170143100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Bool is a more appropriate type for these variables. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-16-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 8ee96d5c042..bba010d7cf5 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8507,8 +8507,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, */ uint32_t key; ARMCPRegInfo *r2; - int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; - int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + bool is64 =3D r->type & ARM_CP_64BIT; + bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; size_t name_len; =20 --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745467; cv=none; d=zohomail.com; s=zohoarc; b=ni21w4H2Y/H35P4pTpGWMcg3XLP1wFAClktX4LisZFgFg2QmsoUMyVL3uEMnKChWW+L8VWlZcQIOdmVb6l2cbAJ/mN3DQhCGVNQE6qAQxmzRu58mq20fi28zlR0hJcihgMKaXVu7dhLwUVs6quPoRBtSRO+Rvy+9kLh5yVNcMIw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651745467; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rTuyUf9hKQBvU2NQj0c8nRvpNJqnGED5I8QAsoNQvNE=; b=TxF1CGN6wpL1yzd7igGCIgfCsFgalViBGDqUJWHy4T9dAGtNf1Zlbi2siPdi3UyeDWGU+R9srx0tHNllf5Y8CtCQp66YSRd2A4t6FQ8Kyfje8lR5jEpMs5MnO8zrUuFwbxC/RHcYogC1LlcL+yGZXVb8aa72KuWWZnvkSiYhWKk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651745467840649.2270384707956; Thu, 5 May 2022 03:11:07 -0700 (PDT) Received: from localhost ([::1]:34462 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYRu-0004Bz-KM for importer@patchew.org; Thu, 05 May 2022 06:11:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38760) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWr-0005Go-7p for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:09 -0400 Received: from mail-wr1-x42c.google.com ([2a00:1450:4864:20::42c]:38616) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWo-0003Nl-R1 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:08 -0400 Received: by mail-wr1-x42c.google.com with SMTP id k2so5221493wrd.5 for ; Thu, 05 May 2022 02:12:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.04 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=rTuyUf9hKQBvU2NQj0c8nRvpNJqnGED5I8QAsoNQvNE=; b=qV0SPRLsNOH8Efiip0Gxjbn0Fi1wCDnReP/o2TQE8HWeNJVXJ90fWD1iYWY53p4S0w Kwbv43dXPQ5reswIEx54QFGSwkz4sYU9hLPBMq55/4Db2fS8lZuysl3m41Fs9WHr4aVu Lv3HHSmZ7Gp9rUUuu7DAndfgybBCTF331r7+5+VoXCS9n2C+9rfqBuIsbg1TU0LEKor+ 0RBDZdhgh8mm1mMIPPOxcbsaXS/eOprBBrWvxKxm2XFwz9riGjESIAyx6K69bn0G1rFg 7bzWhtXRR3FxMfc7gm9/lecuMT//NFaXzIYZaw8OFXbjyUp56Br5GTIMNMPfZOO8a1wu KDPQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rTuyUf9hKQBvU2NQj0c8nRvpNJqnGED5I8QAsoNQvNE=; b=itI51jp8gu0djsKbPPpSwcBEGILutrpSA/YiXwbcMuTtD3MLDnKNZ+A+GyBqUipAtI uoqECPj4g7iDHME7KKw24i98+jtdInC8sKTJJB6HX/EoALKEprmKVLXAdpW4B9YxhAzQ tP88VEUiYm3KVTBZpSoL/5z+qnT2zCp12DJMVBmw/1CZD5HFLWpGitQkgT7rgDMEtWRz ISkwX9YqVus37cmQNADr2RjB4oHDQj9vqNQ0wxzNIcb3BBuKOTAGoV52ZWUwpmr1Nsij EBBHq/SQnPsY/dt6VQD0aLRzc0Ycdow6DLPjeVMrAiLYGRNZdcjfsWGk2gEXWnHvonG8 Fvig== X-Gm-Message-State: AOAM530IQeA+ND4K0d1C/bhT3IZCe2DbT3UP0O6MFKjgCOHWINtKMtN2 8wmOQ8oFUNJTxs6x7Z6RqDSNjTONpD5D3g== X-Google-Smtp-Source: ABdhPJxmy+1hv6SRa0KZKbiPb1G4aV0IgXk3zjPc9fhheP/bCoRiI4LBRI9ltsR8HJo4VomRKkPM/A== X-Received: by 2002:a5d:6182:0:b0:20a:db93:be6d with SMTP id j2-20020a5d6182000000b0020adb93be6dmr19400775wru.597.1651741925341; Thu, 05 May 2022 02:12:05 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 17/23] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:41 +0100 Message-Id: <20220505091147.2657652-18-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::42c; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745468995100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Computing isbanked only once makes the code a bit easier to read. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-17-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index bba010d7cf5..941b777dea9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8510,6 +8510,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; + bool isbanked; size_t name_len; =20 switch (state) { @@ -8557,7 +8558,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->opaque =3D opaque; } =20 - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; + if (isbanked) { /* Register is banked (using both entries in array). * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. @@ -8566,7 +8568,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 if (state =3D=3D ARM_CP_STATE_AA32) { - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + if (isbanked) { /* If the register is banked then we don't need to migrate or * reset the 32-bit instance in certain cases: * --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651747290; cv=none; d=zohomail.com; s=zohoarc; b=RGhg73ROIaeRA+rS3USEU95eIvDMd1EYqKwFu0Nla0/77YFwEmtIHK4fVJLyKjVxybu//gXJKO0H+sEuQcI1PH5PDDS36bTQ2+nt9xSPNLG7ojF5UEmSMtQm09VvkHjpd8BxtFb7nfAbim7EprAss+YffK/e94+tLDzcnfpyMHM= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651747290; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=W8ytmsmn3zVtAhYPboUfBL7b0W6ZRe4BJqXc5Vj3xX4=; b=cbyN2N+kHQ+iqP4iMuNlD/2GwjLvJpunOdMUH4UC+pX8iK4V7DqtNeP9GT/Qi7xZcMAxlF7YmBDHi2Q6a5xILuqHLaaC14gQdJ5iiQZCcAGzKTq6iy4wXPInGVG2kJsbT9diSfoBW0hDv+dOP6C34Nm/jeupbCvWmrYQVacyOhk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651747290754198.7346597344167; Thu, 5 May 2022 03:41:30 -0700 (PDT) Received: from localhost ([::1]:55390 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYvJ-0006LC-Bt for importer@patchew.org; Thu, 05 May 2022 06:41:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38758) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWr-0005Gf-7D for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:09 -0400 Received: from mail-wr1-x436.google.com ([2a00:1450:4864:20::436]:35728) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWp-0003Hq-0O for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:08 -0400 Received: by mail-wr1-x436.google.com with SMTP id j15so5248983wrb.2 for ; Thu, 05 May 2022 02:12:06 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.05 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=W8ytmsmn3zVtAhYPboUfBL7b0W6ZRe4BJqXc5Vj3xX4=; b=zFiiWBkq8fnF8dVkVi03MYDwdZlhu92NT2zZQ328Y9Z2MZfrRePJAaua42XgFsR1pX TLqiFYyvSF8NaZmo1DkZY+IbVSjuFypydvrxHeGQYUxrd5HO+q7CYwLpGwJVkBE5RmU6 xDzvhCHhV/ymIhyxR/MNuEahjj4TvO1sdlYX3YfaGLjQa0PP+MWtbzp5JEUM/VwKRJBV Px2fdcy7ANI4bIHQ2av5c+4iLn2Axqsz5+8j+/oMHlXjAy8TY42k16FigCx2S3zDA31Z GzZHM7r5J0XM/b02zgxXpW3CQH/bUuIXmmWttz7/tFnv34vQgqffFlcra+vA0kyW+ojm y1Dg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=W8ytmsmn3zVtAhYPboUfBL7b0W6ZRe4BJqXc5Vj3xX4=; b=SzzkMANYobWaO6Ki6Kd51e7ayQNZ6hiRlzyaw008UH3lKH1DCi22gs40/pxZztf4ro /sakdTyI1sQh2rtaeQImBAXntc9DqnewWNPzZHoPbVlE1QhLGWd9IJZG0ygeXRZABe3m iaE9tI8wgtdDZ9euKLiMuUXTLev/vvvPqlk3tJrPx+2YIbDS02nVbE3YDgaf3IkqW9Z3 O+Guwjo8v6E4Ndfo/CT6mIHJubV8xT2aS36ZSiUSTDk5On8MjwymDT5iMfhgeoRPfMnM 6/EQ0FlcPwrJ1ks8BPZzvyvo5sqk1Khlm8MhhunPNs+AMt3YSKJU9slCJz7LNsn9jxo1 gSWg== X-Gm-Message-State: AOAM5319h7SnCcxqvoNDKLMPVltg4ln6wYU6uYwM+F7y8mZ4falxo9jP Lqcm9SfqaPeXgRAajKs6WhzjH/vzimmENw== X-Google-Smtp-Source: ABdhPJz2Y1bZP79X3cfrPQq2cNNehr4Ve06ysuHXc4dr6f7geQIgBj1f9pcQ59IoYp0vHvIoCimjSw== X-Received: by 2002:a5d:5960:0:b0:20c:5a12:20ed with SMTP id e32-20020a5d5960000000b0020c5a1220edmr16943406wri.303.1651741926119; Thu, 05 May 2022 02:12:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 18/23] target/arm: Perform override check early in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:42 +0100 Message-Id: <20220505091147.2657652-19-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::436; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x436.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651747291771100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Perform the override check early, so that it is still done even when we decide to discard an unreachable cpreg. Use assert not printf+abort. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-18-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 941b777dea9..fa1e7bd462c 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8538,6 +8538,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, g_assert_not_reached(); } =20 + /* Overriding of an existing definition must be explicitly requested. = */ + if (!(r->type & ARM_CP_OVERRIDE)) { + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); + if (oldreg) { + assert(oldreg->type & ARM_CP_OVERRIDE); + } + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8622,20 +8630,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, assert(!raw_accessors_invalid(r2)); } =20 - /* Overriding of an existing definition must be explicitly - * requested. - */ - if (!(r->type & ARM_CP_OVERRIDE)) { - const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { - fprintf(stderr, "Register redefined: cp=3D%d %d bit " - "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " - "was %s, now %s\n", r2->cp, 32 + 32 * is64, - r2->crn, r2->crm, r2->opc1, r2->opc2, - oldreg->name, r2->name); - g_assert_not_reached(); - } - } g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651745634; cv=none; d=zohomail.com; s=zohoarc; b=AXpZ7m8/ePuOkUHewl8tk3IVFhkKSPZ+BQ69jOrKxYQf8QaWk6feBdJ5Fiw03xvnBE+wShlXT9/R+TmiA+lV5Zj1mMz+oiork9ZUWc5ErbjfPEewvbcy75uTMdgkRj/Miq7y7q9tBGHjCGp+XKmwExVL+8Z6HAY2FVEMnV4AQZY= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651745634; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=juGYeCU9KAGWm+sx2XQ7zrm8YPa+MyJD56BKOagRgGE=; b=mVDcxtqNaXioBmm/PSESXsEyU3NFIMdRxA2uOnjSjcvxGkjZ5e94dM1OMY2BgszHsXscl6ouDIHafvagleavESCBMSASMjUSO8Lot6+VXdK3oIs/pkgE04UNBZ9v0qixiPuihr4YVZQKgrny03zPPLzQgjLJKB6ijtYjL6+GEl8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651745634702255.03329794300942; Thu, 5 May 2022 03:13:54 -0700 (PDT) Received: from localhost ([::1]:42024 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYUb-0000zY-Df for importer@patchew.org; Thu, 05 May 2022 06:13:53 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38776) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWs-0005IX-7P for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:10 -0400 Received: from mail-wr1-x430.google.com ([2a00:1450:4864:20::430]:41972) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWp-0003Dr-Rd for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:09 -0400 Received: by mail-wr1-x430.google.com with SMTP id c11so5216069wrn.8 for ; Thu, 05 May 2022 02:12:07 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.06 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=juGYeCU9KAGWm+sx2XQ7zrm8YPa+MyJD56BKOagRgGE=; b=CMQ+nGQnmb0Y0tUSUF36q4yJ8Bn4KLShAQP2aeEYkz9S23sEAri/VdwfuFTb2VtBDW hXKdN41Lx+ia6jEpkGEHMX2IwHvepJ5rbCAhOvmiIl1QkgZ/xVpp9/fbP6SIkiLPNrpU IsfDQy8ct/UrIsCpxDg5O96UQxleiQiNtXl37i7JUAU8HQ+HRPTCVX1joQi5vunM8obh RoaluQq9cdBL4TrZTWTPBe3a3gHETONI1MmsXFtrixbO5R44T4b7PRdSeTTF7Lpn9rTL expi3EZBgG8sfaJ4t+QTYwFsdsPxiZgVTetM8h3n78F9pnqFOpjDhLef72GOPr86QLvs aTYw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=juGYeCU9KAGWm+sx2XQ7zrm8YPa+MyJD56BKOagRgGE=; b=eLB3wNCWLeWnkRXmV82P5oT698k+RpAZtpP2ixywdSP5Ije6zWGLgFaI4ItLMDaorE lzGrZNQ/y6Jl7/avejbOZATrSmeYJZubTcGvm4GkakIQaOci6e5bMfMZg8rxKXhCtOlh wMk2dzIFnS15sbT9wTKc8E2+E5rx6eyUfYypwm/ULyESAHACCwMt8/frM5hkQTUmioq6 1pXsXydbwJMMtxmV4TtvVY5RW3wMHeqmlyLzmJ7fWZmsl1OYXOMZ6v7H50o1dKbdyphr v8M92jizvbF5U4q49xC1mRjXrO5+h57TycEENv48xwRf/QXe+KCaedD2XAZa7EXJiXh+ 9f5Q== X-Gm-Message-State: AOAM532628cyifQ4/thk8LugzL+U3ZeL03gMflrEOHze6C13iAPtGS9s jF48xuSTHnToS0LHiwNEECGr69tSFM4WGw== X-Google-Smtp-Source: ABdhPJzk9A9jiimTFqCZs1ipembpUEC+ThFWKoxrGGoVw7UIuNH2khbHoX29YNhtsHmUzrBZyJIkYw== X-Received: by 2002:a5d:4f05:0:b0:20a:dd25:5725 with SMTP id c5-20020a5d4f05000000b0020add255725mr19871135wru.546.1651741926926; Thu, 05 May 2022 02:12:06 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 19/23] target/arm: Reformat comments in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:43 +0100 Message-Id: <20220505091147.2657652-20-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::430; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651745635091100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Put the block comments into the current coding style. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-19-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/helper.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index fa1e7bd462c..81612952f3a 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8496,15 +8496,16 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Er= ror **errp) return cpu_list; } =20 +/* + * Private utility function for define_one_arm_cp_reg_with_opaque(): + * add a single reginfo struct to the hash table. + */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { - /* Private utility function for define_one_arm_cp_reg_with_opaque(): - * add a single reginfo struct to the hash table. - */ uint32_t key; ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; @@ -8568,7 +8569,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, =20 isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; if (isbanked) { - /* Register is banked (using both entries in array). + /* + * Register is banked (using both entries in array). * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ @@ -8577,7 +8579,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, =20 if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { - /* If the register is banked then we don't need to migrate or + /* + * If the register is banked then we don't need to migrate or * reset the 32-bit instance in certain cases: * * 1) If the register has both 32-bit and 64-bit instances the= n we @@ -8592,8 +8595,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { - /* The register is not banked so we only want to allow migrati= on of - * the non-secure instance. + /* + * The register is not banked so we only want to allow migrati= on + * of the non-secure instance. */ r2->type |=3D ARM_CP_ALIAS; } @@ -8607,7 +8611,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } } =20 - /* By convention, for wildcarded registers only the first + /* + * By convention, for wildcarded registers only the first * entry is used for migration; the others are marked as * ALIAS so we don't try to transfer the register * multiple times. Special registers (ie NOP/WFI) are @@ -8622,7 +8627,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 - /* Check that raw accesses are either forbidden or handled. Note that + /* + * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651747521; cv=none; d=zohomail.com; s=zohoarc; b=AaWxyvnPDaRuG4ldKOb/C2mj0Q/zOffBy/dRGp7gtAhKgBA6pLfofbzeY8SX+r6jBqlecEzJR4S6Vj2zQ7JdwKUeTwGm9Aic4xXtu5t4WwJfApgUUejMngFEoL2XObKIXGV6qcmM9L//U7Ur62aTi1AgMjGstI8DaHFapPJuubw= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651747521; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lUUUty35mHrdlwzzNpzWoTHLJi4hbdRcoTC6a1ASl1U=; b=a1UUVe4K8tDxc8mQ1Yh4mU7HugFllTBRIDD0ZYRO2aZVIFIxkpO2zTKwEXqVtuHMrfTZzzHZPDp1MBsgX7NXAYFccWHyICg9P6S3Lar6g/g8DDw7aWWjou2eQ7kGXwO/OAHKe9adt+JoRYHPftmC2E1IhmZAcp/jd5FA/61LVm0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651747521757978.9344319318839; Thu, 5 May 2022 03:45:21 -0700 (PDT) Received: from localhost ([::1]:33330 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYz2-0002Mg-EL for importer@patchew.org; Thu, 05 May 2022 06:45:20 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38806) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWt-0005Jg-Gw for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:11 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:37664) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWr-0003OT-Vt for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:11 -0400 Received: by mail-wr1-x435.google.com with SMTP id t6so5237009wra.4 for ; Thu, 05 May 2022 02:12:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.07 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:07 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=lUUUty35mHrdlwzzNpzWoTHLJi4hbdRcoTC6a1ASl1U=; b=CmktfocO/gJapdbi5n3Yx0H9W7/XwioywVs5X2HjhwZ0rFQvKMcX1hJiDAN+AtOyFP nTd+XBlDR3loVwIr6Jma7/xJOZdA3VR0SjRDyoXlOoIndFBFCJjGIRgYOkn37ooXRI2d hI0DmK86GwM9kD9vptoY2DB93ZaKLOqXg6Q9FwC1VmXSViN9+f7pZxD3Y+3DUzXewx6I TynS3ZRcsj6HXhtQ5mDQ1xjaqY7fFYecsPxZWYBzfbanipL/hWHc/ghBb66awX12c2IP WJuNMHoT2NvTxK7yupz8cebemGA0Ny3TdKOG4Jc9KSa19KvzfpUzRfN6mdO+h5QFBKw4 4vng== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lUUUty35mHrdlwzzNpzWoTHLJi4hbdRcoTC6a1ASl1U=; b=q4IPW+hRS6fFViOPQ3Or4X/BT3VFXzfvEHI4EYmnNIlVvcWWAXow7uaq79DCQeeQEW XfSdvQAarhMXRhYjyjpWDms1A2mpZDmseCzxIUcNWw5m1rbU9u3Do6LLs71OpbSpYWav ZWJk4EjQ/Ba5o+sOdvQ2STWgefwx3uSno3SNuU4ASGwXRYAYZoC4yNh8Fne4Z57BywOF jJMOP81HvKa6tEc6W0vj/1NbgsqYmUc7HUkOXA0R8DAXwp/DlW1DSju4qUMZGo94C4yx XsqnfXNGQhyAoCzuYBXr6XXCDyG3cG6W6GAPTa5uc7BqtJHAicfgfPa83Vxc5Wx27diA iyDQ== X-Gm-Message-State: AOAM533PsJpWn2THZlt4oq/PDZ2QscL5ZItDBBvLDiq9BzXtRgKViSH7 V2UZ9gavaiKAQjlXnWF7VNk1IQyvRgIYmQ== X-Google-Smtp-Source: ABdhPJzZ0rDT8Sxs5gLWOXWv62txKXHYLKxlsAl5dDPmqHNDdrXyytnPY+KsWUT4P9uaAlpRdo2gkA== X-Received: by 2002:a05:6000:1841:b0:20c:788b:9306 with SMTP id c1-20020a056000184100b0020c788b9306mr8265320wri.369.1651741927952; Thu, 05 May 2022 02:12:07 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 20/23] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable Date: Thu, 5 May 2022 10:11:44 +0100 Message-Id: <20220505091147.2657652-21-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651747522368100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Since e03b56863d2bc, our host endian indicator is unconditionally set, which means that we can use a normal C condition. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell Message-id: 20220501055028.646596-20-richard.henderson@linaro.org [PMM: quote correct git hash in commit message] Signed-off-by: Peter Maydell --- target/arm/helper.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 81612952f3a..14ea5caad94 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8602,12 +8602,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } =20 - if (r->state =3D=3D ARM_CP_STATE_BOTH) { -#if HOST_BIG_ENDIAN - if (r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); - } -#endif + if (HOST_BIG_ENDIAN && + r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); } } =20 --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651743114; cv=none; d=zohomail.com; s=zohoarc; b=OoLLLUs6pkGhQ8AJOf65RaMAGCpUwzas9VS3G8jNeoluMR0Rzf86jxT9HLgTm5in10gwX6L6O61ZrA0YNz9zvSS9cyrgwBKMMWxdWvc7oaIMPcnchrXZrgMW9ZOt7K/J35ZF6q9ZNSpIrlUiH5nIKtfzXFMe4yjx5UQhbml56dQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651743114; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=MaOeIv9GLNgP2YG/4viwRCAyaqZ3Xrc2Hu8qyXGGVPc=; b=c08zx1TmDE58v6wcewlvm8HWd65nlnkq41hosUhRandb1i7LNG9NIWEyFNIypJN+AHoO2z4sb5n5ofP8MYtKV0F2VKLiq/ykWARNZOu8FS2ZUdO/MabGs3Diq+tRTz8BALy+CS/3ZwBKzG8Ia2oVWj1h9wiqPRxoFj1tHP5JT9Y= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651743113996617.3168731499104; Thu, 5 May 2022 02:31:53 -0700 (PDT) Received: from localhost ([::1]:59550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmXpw-0004DI-Ri for importer@patchew.org; Thu, 05 May 2022 05:31:52 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38810) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWt-0005K8-L2 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:11 -0400 Received: from mail-wr1-x435.google.com ([2a00:1450:4864:20::435]:41980) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWs-0003Or-67 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:11 -0400 Received: by mail-wr1-x435.google.com with SMTP id c11so5216773wrn.8 for ; Thu, 05 May 2022 02:12:09 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=MaOeIv9GLNgP2YG/4viwRCAyaqZ3Xrc2Hu8qyXGGVPc=; b=cyLsUlB/lTC2YTqEFR6ZfBiOAJT0eVmAX0FLPuRSoqJCiH7GevEE7vgiOYqpbqSk2c DfPbHmRoX3Kglj4DTe/iD+XQ8IcU0rxpXYSC35/vUTfaeX5FxBNzdkFQ913a5YI808ss HiTbW/VW/UYuepH0tzjji5Iyfq3HMRZeXHHrBBIYvePDedKh68Qj4Iz1s+Nw0+m7WgIX DOywbmel2N2hS1VBf8SmGB6X/6RZB9AXv4MHD2FVruqWubn9vspJGmVEcaqJE/a/INB9 a91RKK8VTNYAus/BUe+zxV5+4kl6DHKLO2x9y4t+CDZM+Sh5Gp4j4wf/d6qtYG5dikw8 Tqlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::435; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x435.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651743115871100001 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-24-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d1b558385ce..7303103016f 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3704,6 +3704,11 @@ static inline bool isar_feature_aa32_ssbs(const ARMI= SARegisters *id) return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; +} + /* * 64-bit feature tests via id registers. */ @@ -4010,6 +4015,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; +} + static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; @@ -4093,6 +4103,11 @@ static inline bool isar_feature_any_tts2uxn(const AR= MISARegisters *id) return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); } =20 +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) +{ + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.08 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=EWdjm92nfPShmGSJgJfifu3iePdWQS75dHEQNsXsTtM=; b=SLS4Rgfy/P4dsfCSzI7yfxhDWCzxpVEd/vO9FzzP6NklYY4Px+AnACbc4HGuY0VoVO HIyHFzKcRo3sGhsRJWB0deo+0WLYdRa1KZ+/gW8mJxiUvABMIWhiazirjLM/IrqQClkK aqqoCpoN9lJTbDA5r+KonFHepmDgrEv/7HzwRoRqL+GHAMaZq41u51r0uVqjfElvjEO/ VDkSkO8cFdrIZ0vDLn9CSIPwLP+19rlYQryz2e5yM/5+JKpyXgUORR04afMcLOGfI+9B IIdfqWNDRRdH/XUnff7BaWhe3I/wsfsEM5COScwlyq2VVSdLN2RcTKkzb94PMFUWE0TN vcvg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=EWdjm92nfPShmGSJgJfifu3iePdWQS75dHEQNsXsTtM=; b=YaUXGGMRXfe548PMKreL/SL15zG2oWrkqaVK1xnd2pq8ewYxrjgxp204OuNP4TW061 wv5CWHSQU4fhL2IU/MBO39M1Kmq3uz0q5oc/HKyufW26G2AtNnn0aW+TZ50FmEt8fDnX DZnzmRSp8yKGnest8Yr0BBh8tbEw4q3HUwwniv/PHhGvY0a02Y7EvK3XmkTKyycEwXvu kiiwOefC/C5UX9ymZfJSBgBQd8n9BhIzGNo+YTz/V+WZqP23lm7vRdq2jbCDToO4Hzbl wyRSArzRKBnivdzx8axS21Dmbga/WXioEc1afTFFnwvGVJw2Sij5ZHIY7gCOQrk0VIHO dBRg== X-Gm-Message-State: AOAM5329sRgLUJ7+CUW1SiGK+UTV3KTwMZIqN7FUgw+Xp4pza1sH9IUF e0U8ySMC6/uBx0ZuuH64PK3Se4sMdCiOSQ== X-Google-Smtp-Source: ABdhPJy2+gmkchV44nfTRxA0/AxFsdY+jmphqOIrKKEyFzOEZuxqqYjSxgJCAufsq+5dvnZLmVSGPA== X-Received: by 2002:a05:600c:4f94:b0:394:6dec:7392 with SMTP id n20-20020a05600c4f9400b003946dec7392mr692040wmq.149.1651741929556; Thu, 05 May 2022 02:12:09 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 22/23] target/arm: Add isar_feature_{aa64,any}_ras Date: Thu, 5 May 2022 10:11:46 +0100 Message-Id: <20220505091147.2657652-23-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::332; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x332.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651746216646100005 Content-Type: text/plain; charset="utf-8" From: Richard Henderson Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-id: 20220501055028.646596-34-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7303103016f..ca01f909a86 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3886,6 +3886,11 @@ static inline bool isar_feature_aa64_aa32_el1(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; } =20 +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; @@ -4108,6 +4113,11 @@ static inline bool isar_feature_any_debugv8p2(const = ARMISARegisters *id) return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); } =20 +static inline bool isar_feature_any_ras(const ARMISARegisters *id) +{ + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.25.1 From nobody Sun May 19 09:08:46 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651746518; cv=none; d=zohomail.com; s=zohoarc; b=CtzUL13x+N25LSvyf7mi0qfKjwv0U8WvvKbyhJ3CgVzGmhphYqcAp7SoNvrGaQQSFdqdOvpkWnMib7iDwV6zwtiLNu9UqYypW8aWbFuki492IKBYwCzXyFFKn0Kz5QTLFHdSqIkYTwYaaB8IEBSTz1QFcsqUwVsClN92CvAcmA8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651746518; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=yn8j7cjv7DNvRTT6jmfpUT2fMRmuJEdJsUwJdEBQNPY=; b=ErJMaoUlTx9XoGfHHASy2so7Pjy2NLpvdQnaIQGuReqTaNBUeDDTegjQFWRSTianp6w/1t7OhTen/XLtxeN9K178nA5KXh0dRj7XdIY75YfE+GFEjRGh+L7+JObQafQ6KusOK6vKoJmJ2uyDbQBiC7uyseIuwHXwm8y7Wb0W/2k= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651746518765451.71505780446375; Thu, 5 May 2022 03:28:38 -0700 (PDT) Received: from localhost ([::1]:35182 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nmYin-00080Q-P6 for importer@patchew.org; Thu, 05 May 2022 06:28:36 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:38840) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nmXWx-0005ML-4R for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:15 -0400 Received: from mail-wm1-x334.google.com ([2a00:1450:4864:20::334]:39656) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nmXWt-0003PC-V9 for qemu-devel@nongnu.org; Thu, 05 May 2022 05:12:13 -0400 Received: by mail-wm1-x334.google.com with SMTP id r204-20020a1c44d5000000b003946c466c17so365954wma.4 for ; Thu, 05 May 2022 02:12:11 -0700 (PDT) Received: from orth.archaic.org.uk (orth.archaic.org.uk. [2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id j14-20020adfe50e000000b0020c6a524fd5sm841612wrm.99.2022.05.05.02.12.09 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 05 May 2022 02:12:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=yn8j7cjv7DNvRTT6jmfpUT2fMRmuJEdJsUwJdEBQNPY=; b=T1/JRvUCS7ZRbn1kMih3cKMPYI9jxSen4vPTSCIGCjADonO6E33icw3RzFKGtHdOjK 9FZuSOItJMnWY/T/p51AKlsbyyfQrteSuLyvGgo6SdvT6pdxwj3r13/yiPyCwzHoMSXz jArXVB1KVjRp2yR5LxqFH0BAViDNeyHQl4K+kqEWhg+tBnup8dh+D9+iUwwRhkTn2kZ0 neT+VmOGMxprC8aeDrJXBqkq5LNGdDJmXAc0TXn+ofJWvLrAG4y9wyqAmpQM+uKhVO6X ++pHuB8YKy55FFNlxCkyjGkys9u5EdTxLJHOZg43m2MlOKXI2xUdAyttRo223c8Tr6lV NzaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yn8j7cjv7DNvRTT6jmfpUT2fMRmuJEdJsUwJdEBQNPY=; b=WsbVm+Ui67ZEs+xonhmsvL8xtxJLqahOfKhV77082Q3c0Ku3jwMFPB/Or5CRk/5NVn 6b3SXkpnEcBSb4pnR8D7vqafxQZGkvaqbatYlq2DNdz+qcjmNQuul4j7nmNTYjOGzW28 RuYDM/6wsgc5ZQG2VDeQYKbsluk2g/sK6YZChTweuap2iZ6LYd1sCAHAnFFXXRDVUd6Q ToQx0mmr2QpbGNOMSv/+gsaXtYf2yiooTZIpkN2J1BplLt4HvQBE1AczFEFDTpqD+t2n 9JedUHZK4CQdBKm7BViqL0n9w4BsAJNaVw73XB3z8mcubvXX8axISTWQ8VWaWfZnCWfn KkFA== X-Gm-Message-State: AOAM533NqDnzl+snCVKkla9WHXlg9iDjnCkivuy/Zc1uuBYLBrxH3QWB dT7f6kK6AQZuwDq3T5F0VAA1eLOcfLqEMg== X-Google-Smtp-Source: ABdhPJwyczC8uAe/wZcPiwiGQQOupsob2O5/0LS3dcDOGHjgiR43tgfB/lEv8HCboC4R99jcZZQKIQ== X-Received: by 2002:a05:600c:35c5:b0:390:9982:7409 with SMTP id r5-20020a05600c35c500b0039099827409mr3572934wmq.127.1651741930443; Thu, 05 May 2022 02:12:10 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 23/23] target/arm: read access to performance counters from EL0 Date: Thu, 5 May 2022 10:11:47 +0100 Message-Id: <20220505091147.2657652-24-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220505091147.2657652-1-peter.maydell@linaro.org> References: <20220505091147.2657652-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=peter.maydell@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651746520117100001 Content-Type: text/plain; charset="utf-8" From: Alex Zuepke The ARMv8 manual defines that PMUSERENR_EL0.ER enables read-access to both PMXEVCNTR_EL0 and PMEVCNTR_EL0 registers, however, we only use it for PMXEVCNTR_EL0. Extend to PMEVCNTR_EL0 as well. Signed-off-by: Alex Zuepke Reviewed-by: Richard Henderson Message-id: 20220428132717.84190-1-alex.zuepke@tum.de Signed-off-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 14ea5caad94..b4daf4f0761 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6639,10 +6639,10 @@ static void define_pmu_regs(ARMCPU *cpu) .crm =3D 8 | (3 & (i >> 3)), .opc1 =3D 0, .opc2 =3D i & 7, .access =3D PL0_RW, .type =3D ARM_CP_IO | ARM_CP_ALIAS, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, - .accessfn =3D pmreg_access }, + .accessfn =3D pmreg_access_xevcntr }, { .name =3D pmevcntr_el0_name, .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 14, .crm =3D 8 | (3 & (i = >> 3)), - .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess, + .opc2 =3D i & 7, .access =3D PL0_RW, .accessfn =3D pmreg_acc= ess_xevcntr, .type =3D ARM_CP_IO, .readfn =3D pmevcntr_readfn, .writefn =3D pmevcntr_writefn, .raw_readfn =3D pmevcntr_rawread, --=20 2.25.1