From nobody Wed Feb 11 00:56:16 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651612622; cv=none; d=zohomail.com; s=zohoarc; b=TP1aWFJijBVzcYu8isokhhQ5O9fTm6SL0oGzZ+t2JSlF1QIRwycJEdRRm2ndmYRinc6sy2Ooa9hj79IueuH0yeSB/cZjkRiPCt1/W6jmunudf2B0bN4sBPka2wlxs/+0dr9VwSg1Qtp2PXOXM1R6XY/RezWugtE7bXuYhy5pzTk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651612622; h=Content-Transfer-Encoding:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=zSABYP4n5j9DpaRkrATAbL9o0CDfndEvUo9tSY+Ych0=; b=GUd+yJEwD2ZBDxVvcK7U1MIt2m+YDuWSPfFhIPrbuQVvlMpYTf0y2zC065788bQjKFFl8jhtd6nWGPcbRrL3PifM7SQUR6uUJJpTgiZWbI/vPOLcM91yyaRfJw4HQcywUQl93zbW3V/3yAOeie53QQ6gQSR8klK7PaEezBfPgmY= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651612622839262.4284033834382; Tue, 3 May 2022 14:17:02 -0700 (PDT) Received: from localhost ([::1]:48458 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nlztF-00021m-OO for importer@patchew.org; Tue, 03 May 2022 17:17:01 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:40688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nlyZz-0000ne-1v for qemu-devel@nongnu.org; Tue, 03 May 2022 15:53:03 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:44608) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nlyZw-0006Ob-KO for qemu-devel@nongnu.org; Tue, 03 May 2022 15:53:02 -0400 Received: by mail-pl1-x631.google.com with SMTP id j8so15862848pll.11 for ; Tue, 03 May 2022 12:52:58 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id fz16-20020a17090b025000b001dbe11be891sm1692286pjb.44.2022.05.03.12.52.56 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 03 May 2022 12:52:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=zSABYP4n5j9DpaRkrATAbL9o0CDfndEvUo9tSY+Ych0=; b=Ef5saaaj5hJEJ5KnBAj9hB8RkLBpZoilw0vNu9Y3kretFp+rixJqjwjb5OgVeoOZOv 95w+s4jSQy/Qf8+nS+0LqYUeujvC+33YGLo8MmvM0coZRVplTGOAnT0NlhALh3smsAl8 stiPFR4BmWm9SiUwjh3J3QVjtah/CCIv6UwZgbDkmNo7vkKL94QdDbSfOIERJAWiG8T4 v7WwQh/sEMviMyLe1/hmvBiknQzVmkzD125DPODM3Jg2MzVPBgIxo+se/8MtelNCt1HZ 76w15DFW7VFbIM0Ds/wmGNlIe2Ft7Hpvn9+Om190W78t8G1aftNJwGkLGDyHs8VpvagX 3YvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zSABYP4n5j9DpaRkrATAbL9o0CDfndEvUo9tSY+Ych0=; b=XHMDvofTFzgmf3HcHyfnXUtfSwTV3P6xnrBxekvucOleA2JDg3Zkx2FcUa9XgX5CDx by9bCge3WXFeTpBukcHuWrt9aVDKLujr5XNmUEsT+wyPbZ52tWoy1b9V1TLYsXGCHU4/ 9TUkyrbh2wbPzY9MirgJiI4owNMFLcWtFY/jdE26E/odKuL3FGE8zH7UQSuQFheX0r79 zu9v9z0HkjjCaXo82mzHmnMix1YucpyzNlLLdsc+2yio2YSP7ezJr8Sj7llZFRMcG+7Z E1lD62wkGQCrD+BK8CmJjlpWHcgVtmT536oP5kyHIiSPBDA/rPOrF7yxkEgtq2Q4g0dJ VG5A== X-Gm-Message-State: AOAM533gkQW0GFTVtNN4i9AWad5Gee7k4poPqPi+6EZbkaZe+LSy6WXY SFHVgHBj8qaBvoi70o3nPpWSLWmHO+JgHA== X-Google-Smtp-Source: ABdhPJx4XuUu8nnZmOWcu5Mto3jc5EGOKAH31za81JxszAMtZ/D+L7VQjMeIfAAcFy3IloE6OiiXUg== X-Received: by 2002:a17:90b:1c04:b0:1dc:4dfd:5a43 with SMTP id oc4-20020a17090b1c0400b001dc4dfd5a43mr6628138pjb.160.1651607577572; Tue, 03 May 2022 12:52:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v2 72/74] target/rx: Cleanup rx_cpu_do_interrupt Date: Tue, 3 May 2022 12:48:41 -0700 Message-Id: <20220503194843.1379101-73-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220503194843.1379101-1-richard.henderson@linaro.org> References: <20220503194843.1379101-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651612624928100001 Content-Type: text/plain; charset="utf-8" Introduce EXCP_IRQ and EXCP_FIRQ to remember the decision that we made in rx_cpu_exec_interrupt. Use a switch to select between exceptions; unify stacked interrupt frame creation; abort if unknown exception. Signed-off-by: Richard Henderson --- target/rx/cpu.h | 4 ++ target/rx/helper.c | 118 ++++++++++++++++++++++----------------------- 2 files changed, 61 insertions(+), 61 deletions(-) diff --git a/target/rx/cpu.h b/target/rx/cpu.h index 99e28fb70f..5b93c0dcb0 100644 --- a/target/rx/cpu.h +++ b/target/rx/cpu.h @@ -84,6 +84,10 @@ enum { */ EXCP_INTB_0 =3D 0x100, EXCP_INTB_255 =3D EXCP_INTB_0 + 255, + + /* Private to the qemu implementation. */ + EXCP_IRQ, + EXCP_FIRQ, }; =20 typedef struct CPUArchState { diff --git a/target/rx/helper.c b/target/rx/helper.c index 29a4b075fa..d12e551cc2 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -42,12 +42,13 @@ void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, i= nt rte) =20 #ifndef CONFIG_USER_ONLY =20 -#define INT_FLAGS (CPU_INTERRUPT_HARD | CPU_INTERRUPT_FIR) void rx_cpu_do_interrupt(CPUState *cs) { RXCPU *cpu =3D RX_CPU(cs); CPURXState *env =3D &cpu->env; - int do_irq =3D cs->interrupt_request & INT_FLAGS; + uint32_t vec =3D cs->exception_index; + target_ulong vec_table =3D 0xffffff80u; /* fixed vector table */ + const char *expname; uint32_t save_psw; =20 env->in_sleep =3D 0; @@ -60,69 +61,62 @@ void rx_cpu_do_interrupt(CPUState *cs) save_psw =3D rx_cpu_pack_psw(env); env->psw_pm =3D env->psw_i =3D env->psw_u =3D 0; =20 - if (do_irq) { - if (do_irq & CPU_INTERRUPT_FIR) { - env->bpc =3D env->pc; - env->bpsw =3D save_psw; - env->pc =3D env->fintv; - env->psw_ipl =3D 15; - cs->interrupt_request &=3D ~CPU_INTERRUPT_FIR; - qemu_set_irq(env->ack, env->ack_irq); - qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); - } else if (do_irq & CPU_INTERRUPT_HARD) { - env->isp -=3D 4; - cpu_stl_data(env, env->isp, save_psw); - env->isp -=3D 4; - cpu_stl_data(env, env->isp, env->pc); - env->pc =3D cpu_ldl_data(env, env->intb + env->ack_irq * 4); - env->psw_ipl =3D env->ack_ipl; - cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; - qemu_set_irq(env->ack, env->ack_irq); - qemu_log_mask(CPU_LOG_INT, - "interrupt 0x%02x raised\n", env->ack_irq); - } - } else { - uint32_t vec =3D cs->exception_index; - const char *expname; + switch (vec) { + case EXCP_FIRQ: + env->bpc =3D env->pc; + env->bpsw =3D save_psw; + env->pc =3D env->fintv; + env->psw_ipl =3D 15; + cs->interrupt_request &=3D ~CPU_INTERRUPT_FIR; + qemu_set_irq(env->ack, env->ack_irq); + qemu_log_mask(CPU_LOG_INT, "fast interrupt raised\n"); + break; =20 + case EXCP_IRQ: + env->psw_ipl =3D env->ack_ipl; + cs->interrupt_request &=3D ~CPU_INTERRUPT_HARD; + qemu_set_irq(env->ack, env->ack_irq); + expname =3D "interrupt"; + vec_table =3D env->intb; + vec =3D env->ack_ipl; + goto do_stacked; + + case EXCP_PRIVILEGED: + expname =3D "privilege violation"; + goto do_stacked; + case EXCP_ACCESS: + expname =3D "access exception"; + goto do_stacked; + case EXCP_UNDEFINED: + expname =3D "illegal instruction"; + goto do_stacked; + case EXCP_FPU: + expname =3D "fpu exception"; + goto do_stacked; + case EXCP_NMI: + expname =3D "non-maskable interrupt"; + goto do_stacked; + case EXCP_RESET: + expname =3D "reset interrupt"; + goto do_stacked; + + case EXCP_INTB_0 ... EXCP_INTB_255: + expname =3D "unconditional trap"; + vec_table =3D env->intb; + vec -=3D EXCP_INTB_0; + goto do_stacked; + + do_stacked: env->isp -=3D 4; cpu_stl_data(env, env->isp, save_psw); env->isp -=3D 4; cpu_stl_data(env, env->isp, env->pc); + env->pc =3D cpu_ldl_data(env, vec_table + vec * 4); + qemu_log_mask(CPU_LOG_INT, "%s raised (0x%02x)\n", expname, vec); + break; =20 - if (vec < EXCP_INTB_0) { - env->pc =3D cpu_ldl_data(env, 0xffffff80 + vec * 4); - } else { - env->pc =3D cpu_ldl_data(env, env->intb + (vec - EXCP_INTB_0) = * 4); - } - switch (vec) { - case EXCP_PRIVILEGED: - expname =3D "privilege violation"; - break; - case EXCP_ACCESS: - expname =3D "access exception"; - break; - case EXCP_UNDEFINED: - expname =3D "illegal instruction"; - break; - case EXCP_FPU: - expname =3D "fpu exception"; - break; - case EXCP_NMI: - expname =3D "non-maskable interrupt"; - break; - case EXCP_RESET: - expname =3D "reset interrupt"; - break; - case EXCP_INTB_0 ... EXCP_INTB_255: - expname =3D "unconditional trap"; - break; - default: - expname =3D "unknown exception"; - break; - } - qemu_log_mask(CPU_LOG_INT, "exception 0x%02x [%s] raised\n", - (vec & 0xff), expname); + default: + g_assert_not_reached(); } env->regs[0] =3D env->isp; } @@ -132,19 +126,21 @@ bool rx_cpu_exec_interrupt(CPUState *cs, int interrup= t_request) RXCPU *cpu =3D RX_CPU(cs); CPURXState *env =3D &cpu->env; int accept =3D 0; + /* hardware interrupt (Normal) */ if ((interrupt_request & CPU_INTERRUPT_HARD) && env->psw_i && (env->psw_ipl < env->req_ipl)) { env->ack_irq =3D env->req_irq; env->ack_ipl =3D env->req_ipl; - accept =3D 1; + accept =3D EXCP_IRQ; } /* hardware interrupt (FIR) */ if ((interrupt_request & CPU_INTERRUPT_FIR) && env->psw_i && (env->psw_ipl < 15)) { - accept =3D 1; + accept =3D EXCP_FIRQ; } if (accept) { + cs->exception_index =3D accept; rx_cpu_do_interrupt(cs); return true; } --=20 2.34.1