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bh=/dKFbuJv6UUirCGfdhvLgPuuwgxXwvqnFkZ+F36HIpk=; b=S7SSKBzcosOFtFZUcaBq1sO4ITaXUUCEw8FNrnrKUVdry3LHYYjYCo2WebBgLXQsSxyj J4OZ4kQlvSEMOS2rkpCN98aexKenkr+/hOg4YDWZg9xntEJV6d1vg0WxiWmiCpg17TOd dFMr3/koC3cMeO94EHifuyIxdnFt9KySThY= From: Peter Delevoryas To: CC: , , , , , Subject: [PATCH] hw/gpio/aspeed_gpio: Fix QOM pin property Date: Mon, 2 May 2022 01:08:27 -0700 Message-ID: <20220502080827.244815-1-pdel@fb.com> X-Mailer: git-send-email 2.30.2 X-FB-Internal: Safe X-Proofpoint-GUID: rjL6Fi6SJRs0d4WyZiakx16UoollJ8Aa X-Proofpoint-ORIG-GUID: rjL6Fi6SJRs0d4WyZiakx16UoollJ8Aa Content-Transfer-Encoding: quoted-printable X-Proofpoint-UnRewURL: 0 URL was un-rewritten MIME-Version: 1.0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.205,Aquarius:18.0.858,Hydra:6.0.486,FMLib:17.11.64.514 definitions=2022-05-02_02,2022-04-28_01,2022-02-23_01 Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=67.231.145.42; envelope-from=prvs=6121c6eaaf=pdel@fb.com; helo=mx0a-00082601.pphosted.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.082, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H3=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @fb.com) X-ZM-MESSAGEID: 1651479110968100001 Content-Type: text/plain; charset="utf-8" I was setting gpioV4-7 to "1110" using the QOM pin property handler and noticed that lowering gpioV7 was inadvertently lowering gpioV4-6 too. (qemu) qom-set /machine/soc/gpio gpioV4 true (qemu) qom-set /machine/soc/gpio gpioV5 true (qemu) qom-set /machine/soc/gpio gpioV6 true (qemu) qom-get /machine/soc/gpio gpioV4 true (qemu) qom-set /machine/soc/gpio gpioV7 false (qemu) qom-get /machine/soc/gpio gpioV4 false An expression in aspeed_gpio_set_pin_level was using a logical NOT operator instead of a bitwise NOT operator: value &=3D !pin_mask; The original author probably intended to make a bitwise NOT expression "~", but mistakenly used a logical NOT operator "!" instead. Some programming languages like Rust use "!" for both purposes. Fixes: 4b7f956862dc ("hw/gpio: Add basic Aspeed GPIO model for AST2400 and AST2500") Signed-off-by: Peter Delevoryas Reviewed-by: C=C3=A9dric Le Goater --- hw/gpio/aspeed_gpio.c | 2 +- tests/qtest/aspeed_gpio-test.c | 87 ++++++++++++++++++++++++++++++++++ tests/qtest/meson.build | 3 +- 3 files changed, 90 insertions(+), 2 deletions(-) create mode 100644 tests/qtest/aspeed_gpio-test.c diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c index c63634d3d3..9b736e7a9f 100644 --- a/hw/gpio/aspeed_gpio.c +++ b/hw/gpio/aspeed_gpio.c @@ -312,7 +312,7 @@ static void aspeed_gpio_set_pin_level(AspeedGPIOState *= s, uint32_t set_idx, if (level) { value |=3D pin_mask; } else { - value &=3D !pin_mask; + value &=3D ~pin_mask; } =20 aspeed_gpio_update(s, &s->sets[set_idx], value); diff --git a/tests/qtest/aspeed_gpio-test.c b/tests/qtest/aspeed_gpio-test.c new file mode 100644 index 0000000000..c1003f2d1b --- /dev/null +++ b/tests/qtest/aspeed_gpio-test.c @@ -0,0 +1,87 @@ +/* + * QTest testcase for the Aspeed GPIO Controller. + * + * Copyright (c) Meta Platforms, Inc. and affiliates. (http://www.meta.com) + * + * Permission is hereby granted, free of charge, to any person obtaining a= copy + * of this software and associated documentation files (the "Software"), t= o deal + * in the Software without restriction, including without limitation the r= ights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or se= ll + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included= in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS= OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OT= HER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING= FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS = IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "qemu/bitops.h" +#include "qemu/timer.h" +#include "qapi/qmp/qdict.h" +#include "libqtest-single.h" + +static bool qom_get_bool(QTestState *s, const char *path, const char *prop= erty) +{ + QDict *r; + bool b; + + r =3D qtest_qmp(s, "{ 'execute': 'qom-get', 'arguments': " + "{ 'path': %s, 'property': %s } }", path, property); + b =3D qdict_get_bool(r, "return"); + qobject_unref(r); + + return b; +} + +static void qom_set_bool(QTestState *s, const char *path, const char *prop= erty, + bool value) +{ + QDict *r; + + r =3D qtest_qmp(s, "{ 'execute': 'qom-set', 'arguments': " + "{ 'path': %s, 'property': %s, 'value': %i } }", + path, property, value); + qobject_unref(r); +} + +static void test_set_colocated_pins(const void *data) +{ + QTestState *s =3D (QTestState *)data; + + /* + * gpioV4-7 occupy bits within a single 32-bit value, so we want to ma= ke + * sure that modifying one doesn't affect the other. + */ + qom_set_bool(s, "/machine/soc/gpio", "gpioV4", true); + qom_set_bool(s, "/machine/soc/gpio", "gpioV5", false); + qom_set_bool(s, "/machine/soc/gpio", "gpioV6", true); + qom_set_bool(s, "/machine/soc/gpio", "gpioV7", false); + g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV4")); + g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV5")); + g_assert(qom_get_bool(s, "/machine/soc/gpio", "gpioV6")); + g_assert(!qom_get_bool(s, "/machine/soc/gpio", "gpioV7")); +} + +int main(int argc, char **argv) +{ + QTestState *s; + int r; + + g_test_init(&argc, &argv, NULL); + + s =3D qtest_init("-machine ast2600-evb"); + qtest_add_data_func("/ast2600/gpio/set_colocated_pins", s, + test_set_colocated_pins); + r =3D g_test_run(); + qtest_quit(s); + + return r; +} diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 6b9807c183..32fb8cf755 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -189,7 +189,8 @@ qtests_npcm7xx =3D \ (slirp.found() ? ['npcm7xx_emc-test'] : []) qtests_aspeed =3D \ ['aspeed_hace-test', - 'aspeed_smc-test'] + 'aspeed_smc-test', + 'aspeed_gpio-test'] qtests_arm =3D \ (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-= dualtimer-test'] : []) + \ --=20 2.30.2