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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:30 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=5H/BaCE0ZUHkWh1YC1YdaF/tLTM1CqaSymauCeSVzo0=; b=c3xNb7IDXKYO30f8OQ20ZMPCCwWHple8urqk4k0rcHwDP4/REoBRobAE8ReXoqx//k rfUHv7o1/yE8PFiOsAlfEEJjH8ffsWjqQJkybSgvQzicDZh0gvE6tgE9GnPTfOpnavmz KxrPfWZPh/K7bfIl2v0yATmsSOd5Ng7a+QfEGHJAWiHXjcVahUIbBWKJelO8Lz3o2xPq 4sjo2nnyaT7hyMmy16AwW2/4Hbypu82OhKNmUjypLBiTfdcxDsZyLMExY4y77S/jRL+Q wMpmqi8D6NVQOVmAZsX3uTZjAQlVsVdmtHIKXD9WFu4m0UG2g1/MB0Q4XMBI0jnxm6/2 gjXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=5H/BaCE0ZUHkWh1YC1YdaF/tLTM1CqaSymauCeSVzo0=; b=tLA609HfrE7RxQinvk9YtSuqZ+/Eg0FBxmi4/jh/eTBaBojr7w9vPNLwvXYKKCLUpV pR0uDkkCcMqlMcKtrd1qVSVnu5DcmWPh1fxIrozpOH1s91Ou8Paq12f/8CpbfOZIJMrn TB2Mle96fKuZ0T4jzccVA4UFv0vtOJ9IzYIkSZ5UogqpZJj3+qHprjdibJWjyTAK1D1H ZuMdmTdrSsqHOqlUUNHaqqJDaoXkGsWuAcSN9oJB1GDSAp+SHoGh6XZCI4+fPNmGT97J +G6CxhWarGDNIOpqR1s30wEPrYrIsxguUPVxEaTDiqYWxuLfFvaEiTpimJwDB6dLBakA pRCA== X-Gm-Message-State: AOAM533vTHnUCukNEY7aXLNm91IZN/1rZ3LQxI89uxvqIpzEu4DbEgoN HcavKRt02Uxs9MwOu50+ZTOvo9TtupKenw== X-Google-Smtp-Source: ABdhPJxTMkq5UtY28saIM2OAUWs/trrTQIB6xVNA7hm0R/Equ0id2HX5gqq4pgEq8Vq/tVsN9AG80Q== X-Received: by 2002:a17:902:e84f:b0:15e:8edc:dec9 with SMTP id t15-20020a170902e84f00b0015e8edcdec9mr4696608plg.78.1651384231186; Sat, 30 Apr 2022 22:50:31 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 01/45] target/arm: Split out cpregs.h Date: Sat, 30 Apr 2022 22:49:43 -0700 Message-Id: <20220501055028.646596-2-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651385100472100001 Move ARMCPRegInfo and all related declarations to a new internal header, out of the public cpu.h. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 413 +++++++++++++++++++++++++++++++++++++ target/arm/cpu.h | 368 --------------------------------- hw/arm/pxa2xx.c | 1 + hw/arm/pxa2xx_pic.c | 1 + hw/intc/arm_gicv3_cpuif.c | 1 + hw/intc/arm_gicv3_kvm.c | 2 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + target/arm/gdbstub.c | 3 +- target/arm/helper.c | 1 + target/arm/op_helper.c | 1 + target/arm/translate-a64.c | 4 +- target/arm/translate.c | 3 +- 14 files changed, 427 insertions(+), 374 deletions(-) create mode 100644 target/arm/cpregs.h diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h new file mode 100644 index 0000000000..8064c0763e --- /dev/null +++ b/target/arm/cpregs.h @@ -0,0 +1,413 @@ +/* + * QEMU ARM CP Register access and descriptions + * + * Copyright (c) 2022 Linaro Ltd + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License + * as published by the Free Software Foundation; either version 2 + * of the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, see + * + */ + +#ifndef TARGET_ARM_CPREGS_H +#define TARGET_ARM_CPREGS_H + +/* + * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a + * special-behaviour cp reg and bits [11..8] indicate what behaviour + * it has. Otherwise it is a simple cp reg, where CONST indicates that + * TCG can assume the value to be constant (ie load at translate time) + * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END + * indicates that the TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). OVERRIDE permits + * a register definition to override a previous definition for the + * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the + * old must have the OVERRIDE bit set. + * ALIAS indicates that this register is an alias view of some underlying + * state which is also visible via another register, and that the other + * register is handling migration and reset; registers marked ALIAS will n= ot be + * migrated but may have their state set by syncing of register state from= KVM. + * NO_RAW indicates that this register has no underlying state and does not + * support raw access for state saving/loading; it will not be used for ei= ther + * migration or KVM state synchronization. (Typically this is for "registe= rs" + * which are actually used as instructions for cache maintenance and so on= .) + * IO indicates that this register does I/O and therefore its accesses + * need to be marked with gen_io_start() and also end the TB. In particula= r, + * registers which implement clocks or timers require this. + * RAISES_EXC is for when the read or write hook might raise an exception; + * the generated code will synchronize the CPU state before calling the ho= ok + * so that it is safe for the hook to call raise_exception(). + * NEWEL is for writes to registers that might change the exception + * level - typically on older ARM chips. For those cases we need to + * re-read the new el when recomputing the translation flags. + */ +#define ARM_CP_SPECIAL 0x0001 +#define ARM_CP_CONST 0x0002 +#define ARM_CP_64BIT 0x0004 +#define ARM_CP_SUPPRESS_TB_END 0x0008 +#define ARM_CP_OVERRIDE 0x0010 +#define ARM_CP_ALIAS 0x0020 +#define ARM_CP_IO 0x0040 +#define ARM_CP_NO_RAW 0x0080 +#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) +#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) +#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) +#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) +#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) +#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) +#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) +#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA +#define ARM_CP_FPU 0x1000 +#define ARM_CP_SVE 0x2000 +#define ARM_CP_NO_GDB 0x4000 +#define ARM_CP_RAISES_EXC 0x8000 +#define ARM_CP_NEWEL 0x10000 +/* Used only as a terminator for ARMCPRegInfo lists */ +#define ARM_CP_SENTINEL 0xfffff +/* Mask of only the flag bits in a type field */ +#define ARM_CP_FLAG_MASK 0x1f0ff + +/* + * Valid values for ARMCPRegInfo state field, indicating which of + * the AArch32 and AArch64 execution states this register is visible in. + * If the reginfo doesn't explicitly specify then it is AArch32 only. + * If the reginfo is declared to be visible in both states then a second + * reginfo is synthesised for the AArch32 view of the AArch64 register, + * such that the AArch32 view is the lower 32 bits of the AArch64 one. + * Note that we rely on the values of these enums as we iterate through + * the various states in some places. + */ +enum { + ARM_CP_STATE_AA32 =3D 0, + ARM_CP_STATE_AA64 =3D 1, + ARM_CP_STATE_BOTH =3D 2, +}; + +/* + * ARM CP register secure state flags. These flags identify security state + * attributes for a given CP register entry. + * The existence of both or neither secure and non-secure flags indicates = that + * the register has both a secure and non-secure hash entry. A single one= of + * these flags causes the register to only be hashed for the specified + * security state. + * Although definitions may have any combination of the S/NS bits, each + * registered entry will only have one to identify whether the entry is se= cure + * or non-secure. + */ +enum { + ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ + ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ +}; + +/* + * Return true if cptype is a valid type field. This is used to try to + * catch errors where the sentinel has been accidentally left off the end + * of a list of registers. + */ +static inline bool cptype_valid(int cptype) +{ + return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) + || ((cptype & ARM_CP_SPECIAL) && + ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); +} + +/* + * Access rights: + * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM + * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and + * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 + * (ie any of the privileged modes in Secure state, or Monitor mode). + * If a register is accessible in one privilege level it's always accessib= le + * in higher privilege levels too. Since "Secure PL1" also follows this ru= le + * (ie anything visible in PL2 is visible in S-PL1, some things are only + * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the + * terminology a little and call this PL3. + * In AArch64 things are somewhat simpler as the PLx bits line up exactly + * with the ELx exception levels. + * + * If access permissions for a register are more complex than can be + * described with these bits, then use a laxer set of restrictions, and + * do the more restrictive/complex check inside a helper function. + */ +#define PL3_R 0x80 +#define PL3_W 0x40 +#define PL2_R (0x20 | PL3_R) +#define PL2_W (0x10 | PL3_W) +#define PL1_R (0x08 | PL2_R) +#define PL1_W (0x04 | PL2_W) +#define PL0_R (0x02 | PL1_R) +#define PL0_W (0x01 | PL1_W) + +/* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ +#ifdef CONFIG_USER_ONLY +#define PL0U_R PL0_R +#else +#define PL0U_R PL1_R +#endif + +#define PL3_RW (PL3_R | PL3_W) +#define PL2_RW (PL2_R | PL2_W) +#define PL1_RW (PL1_R | PL1_W) +#define PL0_RW (PL0_R | PL0_W) + +typedef enum CPAccessResult { + /* Access is permitted */ + CP_ACCESS_OK =3D 0, + /* + * Access fails due to a configurable trap or enable which would + * result in a categorized exception syndrome giving information about + * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, + * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or + * PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_TRAP =3D 1, + /* + * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). + * Note that this is not a catch-all case -- the set of cases which may + * result in this failure is specifically defined by the architecture. + */ + CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, + /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_EL2 =3D 3, + CP_ACCESS_TRAP_EL3 =3D 4, + /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, +} CPAccessResult; + +typedef struct ARMCPRegInfo ARMCPRegInfo; + +/* + * Access functions for coprocessor registers. These cannot fail and + * may not raise exceptions. + */ +typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); +typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, + uint64_t value); +/* Access permission check functions for coprocessor registers. */ +typedef CPAccessResult CPAccessFn(CPUARMState *env, + const ARMCPRegInfo *opaque, + bool isread); +/* Hook function for register reset */ +typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); + +#define CP_ANY 0xff + +/* Definition of an ARM coprocessor register */ +struct ARMCPRegInfo { + /* Name of register (useful mainly for debugging, need not be unique) = */ + const char *name; + /* + * Location of register: coprocessor number and (crn,crm,opc1,opc2) + * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a + * 'wildcard' field -- any value of that field in the MRC/MCR insn + * will be decoded to this register. The register read and write + * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 + * used by the program, so it is possible to register a wildcard and + * then behave differently on read/write if necessary. + * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 + * must both be zero. + * For AArch64-visible registers, opc0 is also used. + * Since there are no "coprocessors" in AArch64, cp is purely used as a + * way to distinguish (for KVM's benefit) guest-visible system registe= rs + * from demuxed ones provided to preserve the "no side effects on + * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest + * visible (to match KVM's encoding); cp=3D=3D0 will be converted to + * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. + */ + uint8_t cp; + uint8_t crn; + uint8_t crm; + uint8_t opc0; + uint8_t opc1; + uint8_t opc2; + /* Execution state in which this register is visible: ARM_CP_STATE_* */ + int state; + /* Register type: ARM_CP_* bits/values */ + int type; + /* Access rights: PL*_[RW] */ + int access; + /* Security state: ARM_CP_SECSTATE_* bits/values */ + int secure; + /* + * The opaque pointer passed to define_arm_cp_regs_with_opaque() when + * this register was defined: can be used to hand data through to the + * register read/write functions, since they are passed the ARMCPRegIn= fo*. + */ + void *opaque; + /* + * Value of this register, if it is ARM_CP_CONST. Otherwise, if + * fieldoffset is non-zero, the reset value of the register. + */ + uint64_t resetvalue; + /* + * Offset of the field in CPUARMState for this register. + * This is not needed if either: + * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs + * 2. both readfn and writefn are specified + */ + ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ + + /* + * Offsets of the secure and non-secure fields in CPUARMState for the + * register if it is banked. These fields are only used during the st= atic + * registration of a register. During hashing the bank associated + * with a given security state is copied to fieldoffset which is used = from + * there on out. + * + * It is expected that register definitions use either fieldoffset or + * bank_fieldoffsets in the definition but not both. It is also expec= ted + * that both bank offsets are set when defining a banked register. Th= is + * use indicates that a register is banked. + */ + ptrdiff_t bank_fieldoffsets[2]; + + /* + * Function for making any access checks for this register in addition= to + * those specified by the 'access' permissions bits. If NULL, no extra + * checks required. The access check is performed at runtime, not at + * translate time. + */ + CPAccessFn *accessfn; + /* + * Function for handling reads of this register. If NULL, then reads + * will be done by loading from the offset into CPUARMState specified + * by fieldoffset. + */ + CPReadFn *readfn; + /* + * Function for handling writes of this register. If NULL, then writes + * will be done by writing to the offset into CPUARMState specified + * by fieldoffset. + */ + CPWriteFn *writefn; + /* + * Function for doing a "raw" read; used when we need to copy + * coprocessor state to the kernel for KVM or out for + * migration. This only needs to be provided if there is also a + * readfn and it has side effects (for instance clear-on-read bits). + */ + CPReadFn *raw_readfn; + /* + * Function for doing a "raw" write; used when we need to copy KVM + * kernel coprocessor state into userspace, or for inbound + * migration. This only needs to be provided if there is also a + * writefn and it masks out "unwritable" bits or has write-one-to-clear + * or similar behaviour. + */ + CPWriteFn *raw_writefn; + /* + * Function for resetting the register. If NULL, then reset will be do= ne + * by writing resetvalue to the field specified in fieldoffset. If + * fieldoffset is 0 then no reset will be done. + */ + CPResetFn *resetfn; + + /* + * "Original" writefn and readfn. + * For ARMv8.1-VHE register aliases, we overwrite the read/write + * accessor functions of various EL1/EL0 to perform the runtime + * check for which sysreg should actually be modified, and then + * forwards the operation. Before overwriting the accessors, + * the original function is copied here, so that accesses that + * really do go to the EL1/EL0 version proceed normally. + * (The corresponding EL2 register is linked via opaque.) + */ + CPReadFn *orig_readfn; + CPWriteFn *orig_writefn; +}; + +/* + * Macros which are lvalues for the field in CPUARMState for the + * ARMCPRegInfo *ri. + */ +#define CPREG_FIELD32(env, ri) \ + (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) +#define CPREG_FIELD64(env, ri) \ + (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) + +#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } + +void define_arm_cp_regs_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opaque= ); +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, + const ARMCPRegInfo *regs, void *opa= que); +static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) +{ + define_arm_cp_regs_with_opaque(cpu, regs, 0); +} +static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) +{ + define_one_arm_cp_reg_with_opaque(cpu, regs, 0); +} +const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); + +/* + * Definition of an ARM co-processor register as viewed from + * userspace. This is used for presenting sanitised versions of + * registers to userspace when emulating the Linux AArch64 CPU + * ID/feature ABI (advertised as HWCAP_CPUID). + */ +typedef struct ARMCPRegUserSpaceInfo { + /* Name of register */ + const char *name; + + /* Is the name actually a glob pattern */ + bool is_glob; + + /* Only some bits are exported to user space */ + uint64_t exported_bits; + + /* Fixed bits are applied after the mask */ + uint64_t fixed_bits; +} ARMCPRegUserSpaceInfo; + +#define REGUSERINFO_SENTINEL { .name =3D NULL } + +void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); + +/* CPWriteFn that can be used to implement writes-ignored behaviour */ +void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, + uint64_t value); +/* CPReadFn that can be used for read-as-zero behaviour */ +uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); + +/* + * CPResetFn that does nothing, for use if no reset is required even + * if fieldoffset is non zero. + */ +void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); + +/* + * Return true if this reginfo struct's field in the cpu state struct + * is 64 bits wide. + */ +static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) +{ + return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); +} + +static inline bool cp_access_ok(int current_el, + const ARMCPRegInfo *ri, int isread) +{ + return (ri->access >> ((current_el * 2) + isread)) & 1; +} + +/* Raw read of a coprocessor register (as needed for migration, etc) */ +uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); + +#endif /* TARGET_ARM_CPREGS_H */ diff --git a/target/arm/cpu.h b/target/arm/cpu.h index db8ff04449..d1b558385c 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -2595,144 +2595,6 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpr= egid) return kvmid; } =20 -/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. - */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff - -/* Valid values for ARMCPRegInfo state field, indicating which of - * the AArch32 and AArch64 execution states this register is visible in. - * If the reginfo doesn't explicitly specify then it is AArch32 only. - * If the reginfo is declared to be visible in both states then a second - * reginfo is synthesised for the AArch32 view of the AArch64 register, - * such that the AArch32 view is the lower 32 bits of the AArch64 one. - * Note that we rely on the values of these enums as we iterate through - * the various states in some places. - */ -enum { - ARM_CP_STATE_AA32 =3D 0, - ARM_CP_STATE_AA64 =3D 1, - ARM_CP_STATE_BOTH =3D 2, -}; - -/* ARM CP register secure state flags. These flags identify security state - * attributes for a given CP register entry. - * The existence of both or neither secure and non-secure flags indicates = that - * the register has both a secure and non-secure hash entry. A single one= of - * these flags causes the register to only be hashed for the specified - * security state. - * Although definitions may have any combination of the S/NS bits, each - * registered entry will only have one to identify whether the entry is se= cure - * or non-secure. - */ -enum { - ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ - ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; - -/* Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - -/* Access rights: - * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM - * defines as PL0 (user), PL1 (fiq/irq/svc/abt/und/sys, ie privileged), and - * PL2 (hyp). The other level which has Read and Write bits is Secure PL1 - * (ie any of the privileged modes in Secure state, or Monitor mode). - * If a register is accessible in one privilege level it's always accessib= le - * in higher privilege levels too. Since "Secure PL1" also follows this ru= le - * (ie anything visible in PL2 is visible in S-PL1, some things are only - * visible in S-PL1) but "Secure PL1" is a bit of a mouthful, we bend the - * terminology a little and call this PL3. - * In AArch64 things are somewhat simpler as the PLx bits line up exactly - * with the ELx exception levels. - * - * If access permissions for a register are more complex than can be - * described with these bits, then use a laxer set of restrictions, and - * do the more restrictive/complex check inside a helper function. - */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) - -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ -#ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R -#else -#define PL0U_R PL1_R -#endif - -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) - /* Return the highest implemented Exception Level */ static inline int arm_highest_el(CPUARMState *env) { @@ -2784,236 +2646,6 @@ static inline int arm_current_el(CPUARMState *env) } } =20 -typedef struct ARMCPRegInfo ARMCPRegInfo; - -typedef enum CPAccessResult { - /* Access is permitted */ - CP_ACCESS_OK =3D 0, - /* Access fails due to a configurable trap or enable which would - * result in a categorized exception syndrome giving information about - * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). - */ - CP_ACCESS_TRAP =3D 1, - /* Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). - * Note that this is not a catch-all case -- the set of cases which may - * result in this failure is specifically defined by the architecture. - */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, -} CPAccessResult; - -/* Access functions for coprocessor registers. These cannot fail and - * may not raise exceptions. - */ -typedef uint64_t CPReadFn(CPUARMState *env, const ARMCPRegInfo *opaque); -typedef void CPWriteFn(CPUARMState *env, const ARMCPRegInfo *opaque, - uint64_t value); -/* Access permission check functions for coprocessor registers. */ -typedef CPAccessResult CPAccessFn(CPUARMState *env, - const ARMCPRegInfo *opaque, - bool isread); -/* Hook function for register reset */ -typedef void CPResetFn(CPUARMState *env, const ARMCPRegInfo *opaque); - -#define CP_ANY 0xff - -/* Definition of an ARM coprocessor register */ -struct ARMCPRegInfo { - /* Name of register (useful mainly for debugging, need not be unique) = */ - const char *name; - /* Location of register: coprocessor number and (crn,crm,opc1,opc2) - * tuple. Any of crm, opc1 and opc2 may be CP_ANY to indicate a - * 'wildcard' field -- any value of that field in the MRC/MCR insn - * will be decoded to this register. The register read and write - * callbacks will be passed an ARMCPRegInfo with the crn/crm/opc1/opc2 - * used by the program, so it is possible to register a wildcard and - * then behave differently on read/write if necessary. - * For 64 bit registers, only crm and opc1 are relevant; crn and opc2 - * must both be zero. - * For AArch64-visible registers, opc0 is also used. - * Since there are no "coprocessors" in AArch64, cp is purely used as a - * way to distinguish (for KVM's benefit) guest-visible system registe= rs - * from demuxed ones provided to preserve the "no side effects on - * KVM register read/write from QEMU" semantics. cp=3D=3D0x13 is guest - * visible (to match KVM's encoding); cp=3D=3D0 will be converted to - * cp=3D=3D0x13 when the ARMCPRegInfo is registered, for convenience. - */ - uint8_t cp; - uint8_t crn; - uint8_t crm; - uint8_t opc0; - uint8_t opc1; - uint8_t opc2; - /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; - /* Register type: ARM_CP_* bits/values */ - int type; - /* Access rights: PL*_[RW] */ - int access; - /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; - /* The opaque pointer passed to define_arm_cp_regs_with_opaque() when - * this register was defined: can be used to hand data through to the - * register read/write functions, since they are passed the ARMCPRegIn= fo*. - */ - void *opaque; - /* Value of this register, if it is ARM_CP_CONST. Otherwise, if - * fieldoffset is non-zero, the reset value of the register. - */ - uint64_t resetvalue; - /* Offset of the field in CPUARMState for this register. - * - * This is not needed if either: - * 1. type is ARM_CP_CONST or one of the ARM_CP_SPECIALs - * 2. both readfn and writefn are specified - */ - ptrdiff_t fieldoffset; /* offsetof(CPUARMState, field) */ - - /* Offsets of the secure and non-secure fields in CPUARMState for the - * register if it is banked. These fields are only used during the st= atic - * registration of a register. During hashing the bank associated - * with a given security state is copied to fieldoffset which is used = from - * there on out. - * - * It is expected that register definitions use either fieldoffset or - * bank_fieldoffsets in the definition but not both. It is also expec= ted - * that both bank offsets are set when defining a banked register. Th= is - * use indicates that a register is banked. - */ - ptrdiff_t bank_fieldoffsets[2]; - - /* Function for making any access checks for this register in addition= to - * those specified by the 'access' permissions bits. If NULL, no extra - * checks required. The access check is performed at runtime, not at - * translate time. - */ - CPAccessFn *accessfn; - /* Function for handling reads of this register. If NULL, then reads - * will be done by loading from the offset into CPUARMState specified - * by fieldoffset. - */ - CPReadFn *readfn; - /* Function for handling writes of this register. If NULL, then writes - * will be done by writing to the offset into CPUARMState specified - * by fieldoffset. - */ - CPWriteFn *writefn; - /* Function for doing a "raw" read; used when we need to copy - * coprocessor state to the kernel for KVM or out for - * migration. This only needs to be provided if there is also a - * readfn and it has side effects (for instance clear-on-read bits). - */ - CPReadFn *raw_readfn; - /* Function for doing a "raw" write; used when we need to copy KVM - * kernel coprocessor state into userspace, or for inbound - * migration. This only needs to be provided if there is also a - * writefn and it masks out "unwritable" bits or has write-one-to-clear - * or similar behaviour. - */ - CPWriteFn *raw_writefn; - /* Function for resetting the register. If NULL, then reset will be do= ne - * by writing resetvalue to the field specified in fieldoffset. If - * fieldoffset is 0 then no reset will be done. - */ - CPResetFn *resetfn; - - /* - * "Original" writefn and readfn. - * For ARMv8.1-VHE register aliases, we overwrite the read/write - * accessor functions of various EL1/EL0 to perform the runtime - * check for which sysreg should actually be modified, and then - * forwards the operation. Before overwriting the accessors, - * the original function is copied here, so that accesses that - * really do go to the EL1/EL0 version proceed normally. - * (The corresponding EL2 register is linked via opaque.) - */ - CPReadFn *orig_readfn; - CPWriteFn *orig_writefn; -}; - -/* Macros which are lvalues for the field in CPUARMState for the - * ARMCPRegInfo *ri. - */ -#define CPREG_FIELD32(env, ri) \ - (*(uint32_t *)((char *)(env) + (ri)->fieldoffset)) -#define CPREG_FIELD64(env, ri) \ - (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) - -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } - -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} -static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) -{ - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); -} -const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); - -/* - * Definition of an ARM co-processor register as viewed from - * userspace. This is used for presenting sanitised versions of - * registers to userspace when emulating the Linux AArch64 CPU - * ID/feature ABI (advertised as HWCAP_CPUID). - */ -typedef struct ARMCPRegUserSpaceInfo { - /* Name of register */ - const char *name; - - /* Is the name actually a glob pattern */ - bool is_glob; - - /* Only some bits are exported to user space */ - uint64_t exported_bits; - - /* Fixed bits are applied after the mask */ - uint64_t fixed_bits; -} ARMCPRegUserSpaceInfo; - -#define REGUSERINFO_SENTINEL { .name =3D NULL } - -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); - -/* CPWriteFn that can be used to implement writes-ignored behaviour */ -void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, - uint64_t value); -/* CPReadFn that can be used for read-as-zero behaviour */ -uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri); - -/* CPResetFn that does nothing, for use if no reset is required even - * if fieldoffset is non zero. - */ -void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque); - -/* Return true if this reginfo struct's field in the cpu state struct - * is 64 bits wide. - */ -static inline bool cpreg_field_is_64bit(const ARMCPRegInfo *ri) -{ - return (ri->state =3D=3D ARM_CP_STATE_AA64) || (ri->type & ARM_CP_64BI= T); -} - -static inline bool cp_access_ok(int current_el, - const ARMCPRegInfo *ri, int isread) -{ - return (ri->access >> ((current_el * 2) + isread)) & 1; -} - -/* Raw read of a coprocessor register (as needed for migration, etc) */ -uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri); - /** * write_list_to_cpustate * @cpu: ARMCPU diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index a6f938f115..0683714733 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -30,6 +30,7 @@ #include "qemu/cutils.h" #include "qemu/log.h" #include "qom/object.h" +#include "target/arm/cpregs.h" =20 static struct { hwaddr io_base; diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index ed032fed54..b80d75d839 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -17,6 +17,7 @@ #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qom/object.h" +#include "target/arm/cpregs.h" =20 #define ICIP 0x00 /* Interrupt Controller IRQ Pending register */ #define ICMR 0x04 /* Interrupt Controller Mask register */ diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 8404f46ee0..2d5959db94 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -20,6 +20,7 @@ #include "gicv3_internal.h" #include "hw/irq.h" #include "cpu.h" +#include "target/arm/cpregs.h" =20 /* * Special case return value from hppvi_index(); must be larger than diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 06f5aceee5..611085e98d 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -31,6 +31,8 @@ #include "vgic_common.h" #include "migration/blocker.h" #include "qom/object.h" +#include "target/arm/cpregs.h" + =20 #ifdef DEBUG_GICV3_KVM #define DPRINTF(fmt, ...) \ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e46a766d77..815add74fa 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -43,6 +43,7 @@ #include "kvm_arm.h" #include "disas/capstone.h" #include "fpu/softfloat.h" +#include "cpregs.h" =20 static void arm_cpu_set_pc(CPUState *cs, vaddr value) { diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 2974cbc0d3..af5ba1d0b3 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,6 +34,7 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" +#include "cpregs.h" =20 =20 #ifndef CONFIG_USER_ONLY diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 13d0e9b195..0e693b182e 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -18,6 +18,7 @@ #if !defined(CONFIG_USER_ONLY) #include "hw/boards.h" #endif +#include "cpregs.h" =20 /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index ca1de47511..f01a126108 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -19,8 +19,9 @@ */ #include "qemu/osdep.h" #include "cpu.h" -#include "internals.h" #include "exec/gdbstub.h" +#include "internals.h" +#include "cpregs.h" =20 typedef struct RegisterSysregXmlParam { CPUState *cs; diff --git a/target/arm/helper.c b/target/arm/helper.c index 5a244c3ed9..3f2e555d6f 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -36,6 +36,7 @@ #include "exec/cpu_ldst.h" #include "semihosting/common-semi.h" #endif +#include "cpregs.h" =20 #define ARM_CPU_FREQ 1000000000 /* FIXME: 1 GHz, should be configurable */ #define PMCR_NUM_COUNTERS 4 /* QEMU IMPDEF choice */ diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 2b87e8808b..67be91c732 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -23,6 +23,7 @@ #include "internals.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" +#include "cpregs.h" =20 #define SIGNBIT (uint32_t)0x80000000 #define SIGNBIT64 ((uint64_t)1 << 63) diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a869d57309..348a638c5c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -27,14 +27,12 @@ #include "translate.h" #include "internals.h" #include "qemu/host-utils.h" - #include "semihosting/semihost.h" #include "exec/gen-icount.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" - +#include "cpregs.h" #include "translate-a64.h" #include "qemu/atomic128.h" =20 diff --git a/target/arm/translate.c b/target/arm/translate.c index 37fb17cdaa..fc7917cdf4 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -30,11 +30,10 @@ #include "qemu/bitops.h" #include "arm_ldst.h" #include "semihosting/semihost.h" - #include "exec/helper-proto.h" #include "exec/helper-gen.h" - #include "exec/log.h" +#include "cpregs.h" =20 =20 #define ENABLE_ARCH_4T arm_dc_feature(s, ARM_FEATURE_V4T) --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651384588510546.0257175854829; Sat, 30 Apr 2022 22:56:28 -0700 (PDT) Received: from localhost ([::1]:46930 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2ZH-0002Lk-Gr for importer@patchew.org; Sun, 01 May 2022 01:56:27 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:42984) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tb-0006jz-Fh for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:35 -0400 Received: from mail-pj1-x1034.google.com ([2607:f8b0:4864:20::1034]:52769) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2TZ-0001E9-Id for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:35 -0400 Received: by mail-pj1-x1034.google.com with SMTP id e24so10350950pjt.2 for ; Sat, 30 Apr 2022 22:50:33 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:31 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dx5oiRJc+noH6sVw0rqRTwoMiOy0KFwAAYpCE0cKydI=; b=FXv2Ap61Mj45dxmTRg+AU2WAE94b6Gx//d7KHUC4Lk7dGyPJoJ7WUGijvyxj0QJYeH Hv2NPLZnjSCShg30ydlkFAr8LwcYyR0JiOvj35osagvgWVX3PkcRS5/980ZKtM5vNl4O pRBF1rKuzVrWTYTZgtRsFU6WAjJH27EEcXtw+Tc1S5bsLebaOcjWMAOVEF6+7a+dstVd nb/DqCUikBQG9XHvPohbGSOCrjooSiMvM70/SfD+Omqsi05ICYPexOm0QuxUhSZJPJHj ItzGNptlNu6YALGyyhd8j5ZwrlrMe+dpAE1hnBNNkhW4PCDJO3Gq3fxZhPuCYAhh6te4 Jkhg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dx5oiRJc+noH6sVw0rqRTwoMiOy0KFwAAYpCE0cKydI=; b=J2ZAeIDfpYG0tXCiS0mSpe/k6TzuiWhVWbINjLNjFtY3DYxyREBdfrq005lizXh9C0 hH9hmow0EsQGgxR+kcghvsB1SbZCnBrbGq0eJqj0okJ33AZsRGPX11KsiZA+SHBAMPPU AzJIB7LZnkG8ACqfJbtk3O1Z9+sYyBe6j+Zov1RZm1N7k9c5b3MuyXKEWOxj1gymxxoF cCNyQaqs2Sz/P8/L4vWn9ZNS+wvtXH3J8etjBQ7A83mj7+ZEy3ouYM387bMAtg/lvQLf XLL5sUYeGRmXlZ1zMh0WbECckOvd3t6bw5Tza28RTB636+lzQ5SQPkoKwSb9L/AiwQiX qRlw== X-Gm-Message-State: AOAM5322tl+JwCZ1aPkFIsItbX15KXTgJz7yU6hiXIUM5awO55PWYNSQ 88B17yEj33OnocZXPhohK6V75jZuPPgNkw== X-Google-Smtp-Source: ABdhPJwZaIgaJEjlKPGaKR1BuBhYfQdIrnXmE+nQLtm1Hc2lo0L05F+FizhZKcif1EdLEvy4l7MnpA== X-Received: by 2002:a17:90a:e7c1:b0:1d2:b8f8:ecc1 with SMTP id kb1-20020a17090ae7c100b001d2b8f8ecc1mr12002875pjb.176.1651384232254; Sat, 30 Apr 2022 22:50:32 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 02/45] target/arm: Reorg CPAccessResult and access_check_cp_reg Date: Sat, 30 Apr 2022 22:49:44 -0700 Message-Id: <20220501055028.646596-3-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1034; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1034.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651384589189100001 Rearrange the values of the enumerators of CPAccessResult so that we may directly extract the target el. For the two special cases in access_check_cp_reg, use CPAccessResult. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 26 ++++++++++++-------- target/arm/op_helper.c | 56 +++++++++++++++++++++--------------------- 2 files changed, 44 insertions(+), 38 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 8064c0763e..7f2c30eab1 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -167,26 +167,32 @@ static inline bool cptype_valid(int cptype) typedef enum CPAccessResult { /* Access is permitted */ CP_ACCESS_OK =3D 0, + + /* + * Combined with one of the following, the low 2 bits indicate the + * target exception level. If 0, the exception is taken to the usual + * target EL (EL1 or PL1 if in EL0, otherwise to the current EL). + */ + CP_ACCESS_EL_MASK =3D 3, + /* * Access fails due to a configurable trap or enable which would * result in a categorized exception syndrome giving information about * the failing instruction (ie syndrome category 0x3, 0x4, 0x5, 0x6, - * 0xc or 0x18). The exception is taken to the usual target EL (EL1 or - * PL1 if in EL0, otherwise to the current EL). + * 0xc or 0x18). */ - CP_ACCESS_TRAP =3D 1, + CP_ACCESS_TRAP =3D (1 << 2), + CP_ACCESS_TRAP_EL2 =3D CP_ACCESS_TRAP | 2, + CP_ACCESS_TRAP_EL3 =3D CP_ACCESS_TRAP | 3, + /* * Access fails and results in an exception syndrome 0x0 ("uncategoriz= ed"). * Note that this is not a catch-all case -- the set of cases which may * result in this failure is specifically defined by the architecture. */ - CP_ACCESS_TRAP_UNCATEGORIZED =3D 2, - /* As CP_ACCESS_TRAP, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_EL2 =3D 3, - CP_ACCESS_TRAP_EL3 =3D 4, - /* As CP_ACCESS_UNCATEGORIZED, but for traps directly to EL2 or EL3 */ - CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D 5, - CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D 6, + CP_ACCESS_TRAP_UNCATEGORIZED =3D (2 << 2), + CP_ACCESS_TRAP_UNCATEGORIZED_EL2 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 2, + CP_ACCESS_TRAP_UNCATEGORIZED_EL3 =3D CP_ACCESS_TRAP_UNCATEGORIZED | 3, } CPAccessResult; =20 typedef struct ARMCPRegInfo ARMCPRegInfo; diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 67be91c732..76499ffa14 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -632,11 +632,13 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, uint32_t isread) { const ARMCPRegInfo *ri =3D rip; + CPAccessResult res =3D CP_ACCESS_OK; int target_el; =20 if (arm_feature(env, ARM_FEATURE_XSCALE) && ri->cp < 14 && extract32(env->cp15.c15_cpar, ri->cp, 1) =3D=3D 0) { - raise_exception(env, EXCP_UDEF, syndrome, exception_target_el(env)= ); + res =3D CP_ACCESS_TRAP; + goto fail; } =20 /* @@ -655,48 +657,46 @@ void HELPER(access_check_cp_reg)(CPUARMState *env, vo= id *rip, uint32_t syndrome, mask &=3D ~((1 << 4) | (1 << 14)); =20 if (env->cp15.hstr_el2 & mask) { - target_el =3D 2; - goto exept; + res =3D CP_ACCESS_TRAP_EL2; + goto fail; } } =20 - if (!ri->accessfn) { + if (ri->accessfn) { + res =3D ri->accessfn(env, ri, isread); + } + if (likely(res =3D=3D CP_ACCESS_OK)) { return; } =20 - switch (ri->accessfn(env, ri, isread)) { - case CP_ACCESS_OK: - return; + fail: + switch (res & ~CP_ACCESS_EL_MASK) { case CP_ACCESS_TRAP: - target_el =3D exception_target_el(env); - break; - case CP_ACCESS_TRAP_EL2: - /* Requesting a trap to EL2 when we're in EL3 is - * a bug in the access function. - */ - assert(arm_current_el(env) !=3D 3); - target_el =3D 2; - break; - case CP_ACCESS_TRAP_EL3: - target_el =3D 3; break; case CP_ACCESS_TRAP_UNCATEGORIZED: - target_el =3D exception_target_el(env); - syndrome =3D syn_uncategorized(); - break; - case CP_ACCESS_TRAP_UNCATEGORIZED_EL2: - target_el =3D 2; - syndrome =3D syn_uncategorized(); - break; - case CP_ACCESS_TRAP_UNCATEGORIZED_EL3: - target_el =3D 3; syndrome =3D syn_uncategorized(); break; default: g_assert_not_reached(); } =20 -exept: + target_el =3D res & CP_ACCESS_EL_MASK; + switch (target_el) { + case 0: + target_el =3D exception_target_el(env); + break; + case 2: + assert(arm_current_el(env) !=3D 3); + assert(arm_is_el2_enabled(env)); + break; + case 3: + assert(arm_feature(env, ARM_FEATURE_EL3)); + break; + default: + /* No "direct" traps to EL1 */ + g_assert_not_reached(); + } + raise_exception(env, EXCP_UDEF, syndrome, target_el); } =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165138507632141.42553576857415; Sat, 30 Apr 2022 23:04:36 -0700 (PDT) Received: from localhost ([::1]:55852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2h8-00009i-Us for importer@patchew.org; Sun, 01 May 2022 02:04:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43098) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Te-0006o9-MQ for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:38 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:38581) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Ta-0001EW-PP for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:38 -0400 Received: by mail-pl1-x62d.google.com with SMTP id n18so10282833plg.5 for ; Sat, 30 Apr 2022 22:50:34 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:32 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=wV+QCHMFrqB6itk4REdnMai7JMqQfYR/Z9HiCHLOVwA=; b=y6TlpK01BrqpYxMw3u0ve2oNY5166uq6zVNamVq6EWVk4tFblKb5FQW3Iepb5DxjP5 Wf1JAUF0/QAbITee2DbCmRWivbiXbwGclGP+pMJsO9/j5+eF3bCInXSJZkY87drhKA/R 9SJjK3+Re0UMnFE5TZTPp7VBMn28iL754bjRyS1ffdVfOA1xzpg3vTzgnLe3LbogO3np pGww8f8CMZjtpE4ME/z6eAMzTSuBLzMoAo0HQNQZcjrUsNfuXHwyrdIhV9yPHwkEEUHT DosOIeL7FqsaqdCxzpbJowgeDKIJnpuqDBqzeAZVmWfrzxWEg8C2b2vZC6G7JE2ap3uV LP5w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=wV+QCHMFrqB6itk4REdnMai7JMqQfYR/Z9HiCHLOVwA=; b=aauxn3DVgA2z10rOBMVztqsasTDZKZZ5sy+QUjk6HCCJjBXiFoFss98OquNwNYRtDT TGsay0O8h6Dut2ox77BWZalzHoqBRadNNKBRR/+GVOTkuEMUHPC+qpgvktiUQFRmOP/Z EviYypB/kd2L9enrceLiuKL0gV4lyiNyJPZfXWCa8yJEjHO0/cO1ez5nUSlOvXq00Pix RXneWs7s5WBDXJ63oGtpsVRs+rEtICb2/xApcjTi0TasH6n9Cc6heIVmiY4Vdmf6De3T 7Gh7JPzp6BPH78J5z7F3bIiPhRmOE0HqSUNkM5A5OxmhtuF/CM3Teg9Oo+SePjq0GFyP snAA== X-Gm-Message-State: AOAM530pZohMqGSVwXgouYB6jcABGzciGoaTAfzNHDeuxVfDbe3mwMny VOb4xpvw91Hh/VZxZUmv/vFiFhpnXzaEMg== X-Google-Smtp-Source: ABdhPJxi9xT1Chf+HDK7bDQaUdW4SMkdzrlhHu+N3I93PA8bJuPFgp0K8hHypiIDOL7yn4wtxcw3EQ== X-Received: by 2002:a17:90b:124c:b0:1bc:369b:7db5 with SMTP id gx12-20020a17090b124c00b001bc369b7db5mr11885956pjb.179.1651384233188; Sat, 30 Apr 2022 22:50:33 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 03/45] target/arm: Replace sentinels with ARRAY_SIZE in cpregs.h Date: Sat, 30 Apr 2022 22:49:45 -0700 Message-Id: <20220501055028.646596-4-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651385078358100001 Remove a possible source of error by removing REGINFO_SENTINEL and using ARRAY_SIZE (convinently hidden inside a macro) to find the end of the set of regs being registered or modified. The space saved by not having the extra array element reduces the executable's .data.rel.ro section by about 9k. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v4: Drop special case for array size 1. --- target/arm/cpregs.h | 53 +++++++++--------- hw/arm/pxa2xx.c | 1 - hw/arm/pxa2xx_pic.c | 1 - hw/intc/arm_gicv3_cpuif.c | 5 -- hw/intc/arm_gicv3_kvm.c | 1 - target/arm/cpu64.c | 1 - target/arm/cpu_tcg.c | 4 -- target/arm/helper.c | 111 ++++++++------------------------------ 8 files changed, 48 insertions(+), 129 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 7f2c30eab1..a5231504d5 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -71,8 +71,6 @@ #define ARM_CP_NO_GDB 0x4000 #define ARM_CP_RAISES_EXC 0x8000 #define ARM_CP_NEWEL 0x10000 -/* Used only as a terminator for ARMCPRegInfo lists */ -#define ARM_CP_SENTINEL 0xfffff /* Mask of only the flag bits in a type field */ #define ARM_CP_FLAG_MASK 0x1f0ff =20 @@ -108,18 +106,6 @@ enum { ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ }; =20 -/* - * Return true if cptype is a valid type field. This is used to try to - * catch errors where the sentinel has been accidentally left off the end - * of a list of registers. - */ -static inline bool cptype_valid(int cptype) -{ - return ((cptype & ~ARM_CP_FLAG_MASK) =3D=3D 0) - || ((cptype & ARM_CP_SPECIAL) && - ((cptype & ~ARM_CP_FLAG_MASK) <=3D ARM_LAST_SPECIAL)); -} - /* * Access rights: * We define bits for Read and Write access for what rev C of the v7-AR AR= M ARM @@ -346,20 +332,27 @@ struct ARMCPRegInfo { #define CPREG_FIELD64(env, ri) \ (*(uint64_t *)((char *)(env) + (ri)->fieldoffset)) =20 -#define REGINFO_SENTINEL { .type =3D ARM_CP_SENTINEL } +void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, const ARMCPRegInfo *re= g, + void *opaque); =20 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque= ); -void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opa= que); -static inline void define_arm_cp_regs(ARMCPU *cpu, const ARMCPRegInfo *reg= s) -{ - define_arm_cp_regs_with_opaque(cpu, regs, 0); -} static inline void define_one_arm_cp_reg(ARMCPU *cpu, const ARMCPRegInfo *= regs) { - define_one_arm_cp_reg_with_opaque(cpu, regs, 0); + define_one_arm_cp_reg_with_opaque(cpu, regs, NULL); } + +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, + void *opaque, size_t len); + +#define define_arm_cp_regs_with_opaque(CPU, REGS, OPAQUE) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ + define_arm_cp_regs_with_opaque_len(CPU, REGS, OPAQUE, \ + ARRAY_SIZE(REGS)); \ + } while (0) + +#define define_arm_cp_regs(CPU, REGS) \ + define_arm_cp_regs_with_opaque(CPU, REGS, NULL) + const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp); =20 /* @@ -382,9 +375,17 @@ typedef struct ARMCPRegUserSpaceInfo { uint64_t fixed_bits; } ARMCPRegUserSpaceInfo; =20 -#define REGUSERINFO_SENTINEL { .name =3D NULL } +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, + const ARMCPRegUserSpaceInfo *mods, + size_t mods_len); =20 -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods); +#define modify_arm_cp_regs(REGS, MODS) \ + do { \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(REGS) =3D=3D 0); = \ + QEMU_BUILD_BUG_ON(ARRAY_SIZE(MODS) =3D=3D 0); = \ + modify_arm_cp_regs_with_len(REGS, ARRAY_SIZE(REGS), \ + MODS, ARRAY_SIZE(MODS)); \ + } while (0) =20 /* CPWriteFn that can be used to implement writes-ignored behaviour */ void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 0683714733..f4f687df68 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -384,7 +384,6 @@ static const ARMCPRegInfo pxa_cp_reginfo[] =3D { { .name =3D "PWRMODE", .cp =3D 14, .crn =3D 7, .crm =3D 0, .opc1 =3D 0= , .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_IO, .readfn =3D arm_cp_read_zero, .writefn =3D pxa2xx_pwrmode_write }, - REGINFO_SENTINEL }; =20 static void pxa2xx_setup_cp14(PXA2xxState *s) diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index b80d75d839..47132ab982 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -257,7 +257,6 @@ static const ARMCPRegInfo pxa_pic_cp_reginfo[] =3D { REGINFO_FOR_PIC_CP("ICLR2", 8), REGINFO_FOR_PIC_CP("ICFP2", 9), REGINFO_FOR_PIC_CP("ICPR2", 0xa), - REGINFO_SENTINEL }; =20 static const MemoryRegionOps pxa2xx_pic_ops =3D { diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c index 2d5959db94..9efba798f8 100644 --- a/hw/intc/arm_gicv3_cpuif.c +++ b/hw/intc/arm_gicv3_cpuif.c @@ -2428,7 +2428,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { .readfn =3D icc_igrpen1_el3_read, .writefn =3D icc_igrpen1_el3_write, }, - REGINFO_SENTINEL }; =20 static uint64_t ich_ap_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -2682,7 +2681,6 @@ static const ARMCPRegInfo gicv3_cpuif_hcr_reginfo[] = =3D { .readfn =3D ich_vmcr_read, .writefn =3D ich_vmcr_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_reginfo[] =3D { @@ -2700,7 +2698,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr1_regin= fo[] =3D { .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_reginfo[] =3D { @@ -2732,7 +2729,6 @@ static const ARMCPRegInfo gicv3_cpuif_ich_apxr23_regi= nfo[] =3D { .readfn =3D ich_ap_read, .writefn =3D ich_ap_write, }, - REGINFO_SENTINEL }; =20 static void gicv3_cpuif_el_change_hook(ARMCPU *cpu, void *opaque) @@ -2807,7 +2803,6 @@ void gicv3_init_cpuif(GICv3State *s) .readfn =3D ich_lr_read, .writefn =3D ich_lr_write, }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, lr_regset); } diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 611085e98d..2922c516e5 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -735,7 +735,6 @@ static const ARMCPRegInfo gicv3_cpuif_reginfo[] =3D { */ .resetfn =3D arm_gicv3_icc_reset, }, - REGINFO_SENTINEL }; =20 /** diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index af5ba1d0b3..c841d55d0e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -91,7 +91,6 @@ static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[]= =3D { { .name =3D "L2MERRSR", .cp =3D 15, .opc1 =3D 3, .crm =3D 15, .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - REGINFO_SENTINEL }; =20 static void aarch64_a57_initfn(Object *obj) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 0e693b182e..9338088b22 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -264,7 +264,6 @@ static const ARMCPRegInfo cortexa8_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, { .name =3D "L2AUXCR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 2, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void cortex_a8_initfn(Object *obj) @@ -332,7 +331,6 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] =3D { .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, { .name =3D "TLB_ATTR", .cp =3D 15, .crn =3D 15, .crm =3D 7, .opc1 =3D= 5, .opc2 =3D 2, .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST }, - REGINFO_SENTINEL }; =20 static void cortex_a9_initfn(Object *obj) @@ -398,7 +396,6 @@ static const ARMCPRegInfo cortexa15_cp_reginfo[] =3D { #endif { .name =3D "L2ECTLR", .cp =3D 15, .crn =3D 9, .crm =3D 0, .opc1 =3D 1= , .opc2 =3D 3, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void cortex_a7_initfn(Object *obj) @@ -686,7 +683,6 @@ static const ARMCPRegInfo cortexr5_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST }, { .name =3D "DCACHE_INVAL", .cp =3D 15, .opc1 =3D 0, .crn =3D 15, .crm= =3D 5, .opc2 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static void cortex_r5_initfn(Object *obj) diff --git a/target/arm/helper.c b/target/arm/helper.c index 3f2e555d6f..a68f14fe8e 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -673,7 +673,6 @@ static const ARMCPRegInfo cp_reginfo[] =3D { .secure =3D ARM_CP_SECSTATE_S, .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_s), .resetvalue =3D 0, .writefn =3D contextidr_write, .raw_writefn =3D r= aw_write, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { @@ -702,7 +701,6 @@ static const ARMCPRegInfo not_v8_cp_reginfo[] =3D { { .name =3D "CACHEMAINT", .cp =3D 15, .crn =3D 7, .crm =3D CP_ANY, .opc1 =3D 0, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { @@ -711,7 +709,6 @@ static const ARMCPRegInfo not_v6_cp_reginfo[] =3D { */ { .name =3D "WFI_v5", .cp =3D 15, .crn =3D 7, .crm =3D 8, .opc1 =3D 0,= .opc2 =3D 2, .access =3D PL1_W, .type =3D ARM_CP_WFI }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { @@ -760,7 +757,6 @@ static const ARMCPRegInfo not_v7_cp_reginfo[] =3D { .opc1 =3D 0, .opc2 =3D 0, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, { .name =3D "NMRR", .cp =3D 15, .crn =3D 10, .crm =3D 2, .opc1 =3D 0, .opc2 =3D 1, .access =3D PL1_RW, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -889,7 +885,6 @@ static const ARMCPRegInfo v6_cp_reginfo[] =3D { .crn =3D 1, .crm =3D 0, .opc1 =3D 0, .opc2 =3D 2, .accessfn =3D cpac= r_access, .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.cpac= r_el1), .resetfn =3D cpacr_reset, .writefn =3D cpacr_write, .readfn =3D cpac= r_read }, - REGINFO_SENTINEL }; =20 typedef struct pm_event { @@ -2135,7 +2130,6 @@ static const ARMCPRegInfo v7_cp_reginfo[] =3D { { .name =3D "TLBIMVAA", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm =3D = 7, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { @@ -2152,7 +2146,6 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] =3D { { .name =3D "TLBIMVAAIS", .cp =3D 15, .opc1 =3D 0, .crn =3D 8, .crm = =3D 3, .opc2 =3D 3, .type =3D ARM_CP_NO_RAW, .access =3D PL1_W, .accessfn =3D access_ttl= b, .writefn =3D tlbimvaa_is_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { @@ -2170,7 +2163,6 @@ static const ARMCPRegInfo pmovsset_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c9_pmovsr), .writefn =3D pmovsset_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; =20 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -2211,7 +2203,6 @@ static const ARMCPRegInfo t2ee_cp_reginfo[] =3D { { .name =3D "TEEHBR", .cp =3D 14, .crn =3D 1, .crm =3D 0, .opc1 =3D 6,= .opc2 =3D 0, .access =3D PL0_RW, .fieldoffset =3D offsetof(CPUARMState, teehbr), .accessfn =3D teehbr_access, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo v6k_cp_reginfo[] =3D { @@ -2243,7 +2234,6 @@ static const ARMCPRegInfo v6k_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetoflow32(CPUARMState, cp15.tpidrprw_s), offsetoflow32(CPUARMState, cp15.tpidrprw_ns) = }, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -3091,7 +3081,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .fieldoffset =3D offsetof(CPUARMState, cp15.c14_timer[GTIMER_SEC].cv= al), .writefn =3D gt_sec_cval_write, .raw_writefn =3D raw_write, }, - REGINFO_SENTINEL }; =20 static CPAccessResult e2h_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3132,7 +3121,6 @@ static const ARMCPRegInfo generic_timer_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_NO_RAW | ARM_CP_IO, .readfn =3D gt_virt_cnt_read, }, - REGINFO_SENTINEL }; =20 #endif @@ -3496,7 +3484,6 @@ static const ARMCPRegInfo vapa_cp_reginfo[] =3D { .access =3D PL1_W, .accessfn =3D ats_access, .writefn =3D ats_write, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC = }, #endif - REGINFO_SENTINEL }; =20 /* Return basic MPU access permission bits. */ @@ -3619,7 +3606,6 @@ static const ARMCPRegInfo pmsav7_cp_reginfo[] =3D { .fieldoffset =3D offsetof(CPUARMState, pmsav7.rnr[M_REG_NS]), .writefn =3D pmsav7_rgnr_write, .resetfn =3D arm_cp_reset_ignore }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { @@ -3670,7 +3656,6 @@ static const ARMCPRegInfo pmsav5_cp_reginfo[] =3D { { .name =3D "946_PRBS7", .cp =3D 15, .crn =3D 6, .crm =3D 7, .opc1 =3D= 0, .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, .fieldoffset =3D offsetof(CPUARMState, cp15.c6_region[7]) }, - REGINFO_SENTINEL }; =20 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3824,7 +3809,6 @@ static const ARMCPRegInfo vmsa_pmsa_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_tvm_trvm, .fieldoffset =3D offsetof(CPUARMState, cp15.far_el[1]), .resetvalue =3D 0, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { @@ -3857,7 +3841,6 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] =3D { /* No offsetoflow32 -- pass the entire TCR to writefn/raw_writefn. */ .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.tcr_el[3]), offsetof(CPUARMState, cp15.tcr_el[1])} }, - REGINFO_SENTINEL }; =20 /* Note that unlike TTBCR, writing to TTBCR2 does not require flushing @@ -3942,7 +3925,6 @@ static const ARMCPRegInfo omap_cp_reginfo[] =3D { { .name =3D "C9", .cp =3D 15, .crn =3D 9, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1= _RW, .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri, @@ -3975,7 +3957,6 @@ static const ARMCPRegInfo xscale_cp_reginfo[] =3D { { .name =3D "XSCALE_UNLOCK_DCACHE", .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 2, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { @@ -3989,7 +3970,6 @@ static const ARMCPRegInfo dummy_c15_cp_reginfo[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW | ARM_CP_OVERRIDE, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] =3D { @@ -3997,7 +3977,6 @@ static const ARMCPRegInfo cache_dirty_status_cp_regin= fo[] =3D { { .name =3D "CDSR", .cp =3D 15, .crn =3D 7, .crm =3D 10, .opc1 =3D 0, = .opc2 =3D 6, .access =3D PL1_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] =3D { @@ -4018,7 +3997,6 @@ static const ARMCPRegInfo cache_block_ops_cp_reginfo[= ] =3D { .access =3D PL0_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, { .name =3D "CIDCR", .cp =3D 15, .crm =3D 14, .opc1 =3D 0, .access =3D PL1_W, .type =3D ARM_CP_NOP|ARM_CP_64BIT }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] =3D { @@ -4031,7 +4009,6 @@ static const ARMCPRegInfo cache_test_clean_cp_reginfo= [] =3D { { .name =3D "TCI_DCACHE", .cp =3D 15, .crn =3D 7, .crm =3D 14, .opc1 = =3D 0, .opc2 =3D 3, .access =3D PL0_R, .type =3D ARM_CP_CONST | ARM_CP_NO_RAW, .resetvalue =3D (1 << 30) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { @@ -4040,7 +4017,6 @@ static const ARMCPRegInfo strongarm_cp_reginfo[] =3D { .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_RW, .resetvalue =3D 0, .type =3D ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_RAW }, - REGINFO_SENTINEL }; =20 static uint64_t midr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -4107,7 +4083,6 @@ static const ARMCPRegInfo lpae_cp_reginfo[] =3D { .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.ttbr1_s), offsetof(CPUARMState, cp15.ttbr1_ns) }, .writefn =3D vmsa_ttbr_write, }, - REGINFO_SENTINEL }; =20 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -5126,7 +5101,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .accessfn =3D access_trap_aa32s_el1, .writefn =3D sdcr_write, .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, - REGINFO_SENTINEL }; =20 /* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ @@ -5237,7 +5211,6 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D= { .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, .access =3D PL2_RW, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 /* Ditto, but for registers which exist in ARMv8 but not v7 */ @@ -5246,7 +5219,6 @@ static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) @@ -5679,7 +5651,6 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .cp =3D 15, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 = =3D 3, .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.hstr_el2) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { @@ -5689,7 +5660,6 @@ static const ARMCPRegInfo el2_v8_cp_reginfo[] =3D { .access =3D PL2_RW, .fieldoffset =3D offsetofhigh32(CPUARMState, cp15.hcr_el2), .writefn =3D hcr_writehigh }, - REGINFO_SENTINEL }; =20 static CPAccessResult sel2_access(CPUARMState *env, const ARMCPRegInfo *ri, @@ -5710,7 +5680,6 @@ static const ARMCPRegInfo el2_sec_cp_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 6, .opc2 =3D 2, .access =3D PL2_RW, .accessfn =3D sel2_access, .fieldoffset =3D offsetof(CPUARMState, cp15.vstcr_el2) }, - REGINFO_SENTINEL }; =20 static CPAccessResult nsacr_access(CPUARMState *env, const ARMCPRegInfo *r= i, @@ -5836,7 +5805,6 @@ static const ARMCPRegInfo el3_cp_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae3_write }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -6122,7 +6090,6 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { .cp =3D 14, .opc0 =3D 2, .opc1 =3D 0, .crn =3D 0, .crm =3D 2, .opc2 = =3D 0, .access =3D PL1_RW, .accessfn =3D access_tda, .type =3D ARM_CP_NOP }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D { @@ -6131,7 +6098,6 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] =3D= { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, { .name =3D "DBGDSAR", .cp =3D 14, .crm =3D 2, .opc1 =3D 0, .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, - REGINFO_SENTINEL }; =20 /* Return the exception level to which exceptions should be taken @@ -6617,7 +6583,6 @@ static void define_debug_regs(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.dbgbcr[i]), .writefn =3D dbgbcr_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, dbgregs); } @@ -6636,7 +6601,6 @@ static void define_debug_regs(ARMCPU *cpu) .fieldoffset =3D offsetof(CPUARMState, cp15.dbgwcr[i]), .writefn =3D dbgwcr_write, .raw_writefn =3D raw_write }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, dbgregs); } @@ -6699,7 +6663,6 @@ static void define_pmu_regs(ARMCPU *cpu) .type =3D ARM_CP_IO, .readfn =3D pmevtyper_readfn, .writefn =3D pmevtyper_writefn, .raw_writefn =3D pmevtyper_rawwrite }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, pmev_regs); g_free(pmevcntr_name); @@ -6717,7 +6680,6 @@ static void define_pmu_regs(ARMCPU *cpu) .cp =3D 15, .opc1 =3D 0, .crn =3D 9, .crm =3D 14, .opc2 =3D = 5, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .resetvalue =3D extract64(cpu->pmceid1, 32, 32) }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v81_pmu_regs); } @@ -6814,7 +6776,6 @@ static const ARMCPRegInfo lor_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 10, .crm =3D 4, .opc2 =3D 7, .access =3D PL1_R, .accessfn =3D access_lor_ns, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 #ifdef TARGET_AARCH64 @@ -6877,7 +6838,6 @@ static const ARMCPRegInfo pauth_reginfo[] =3D { .opc0 =3D 3, .opc1 =3D 0, .crn =3D 2, .crm =3D 1, .opc2 =3D 3, .access =3D PL1_RW, .accessfn =3D access_pauth, .fieldoffset =3D offsetof(CPUARMState, keys.apib.hi) }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo tlbirange_reginfo[] =3D { @@ -6989,7 +6949,6 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_rvae3_write }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo tlbios_reginfo[] =3D { @@ -7061,7 +7020,6 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, .access =3D PL3_W, .type =3D ARM_CP_NO_RAW, .writefn =3D tlbi_aa64_vae3is_write }, - REGINFO_SENTINEL }; =20 static uint64_t rndr_readfn(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7100,7 +7058,6 @@ static const ARMCPRegInfo rndr_reginfo[] =3D { .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END | ARM_CP_IO, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 2, .crm =3D 4, .opc2 =3D 1, .access =3D PL0_R, .readfn =3D rndr_readfn }, - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -7136,7 +7093,6 @@ static const ARMCPRegInfo dcpop_reg[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 12, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo dcpodp_reg[] =3D { @@ -7144,7 +7100,6 @@ static const ARMCPRegInfo dcpodp_reg[] =3D { .opc0 =3D 1, .opc1 =3D 3, .crn =3D 7, .crm =3D 13, .opc2 =3D 1, .access =3D PL0_W, .type =3D ARM_CP_NO_RAW | ARM_CP_SUPPRESS_TB_END, .accessfn =3D aa64_cacheop_poc_access, .writefn =3D dccvap_writefn }, - REGINFO_SENTINEL }; #endif /*CONFIG_USER_ONLY*/ =20 @@ -7246,14 +7201,12 @@ static const ARMCPRegInfo mte_reginfo[] =3D { { .name =3D "DC_CIGDSW", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 14, .opc2 =3D 6, .type =3D ARM_CP_NOP, .access =3D PL1_W, .accessfn =3D access_tsw }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo mte_tco_ro_reginfo[] =3D { { .name =3D "TCO", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 3, .crn =3D 4, .crm =3D 2, .opc2 =3D 7, .type =3D ARM_CP_CONST, .access =3D PL0_RW, }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo mte_el0_cacheop_reginfo[] =3D { @@ -7305,7 +7258,6 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { .accessfn =3D aa64_zva_access, #endif }, - REGINFO_SENTINEL }; =20 #endif @@ -7351,7 +7303,6 @@ static const ARMCPRegInfo predinv_reginfo[] =3D { { .name =3D "CPPRCTX", .state =3D ARM_CP_STATE_AA32, .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 3, .opc2 =3D 7, .type =3D ARM_CP_NOP, .access =3D PL0_W, .accessfn =3D access_predin= v }, - REGINFO_SENTINEL }; =20 static uint64_t ccsidr2_read(CPUARMState *env, const ARMCPRegInfo *ri) @@ -7366,7 +7317,6 @@ static const ARMCPRegInfo ccsidr2_reginfo[] =3D { .access =3D PL1_R, .accessfn =3D access_aa64_tid2, .readfn =3D ccsidr2_read, .type =3D ARM_CP_NO_RAW }, - REGINFO_SENTINEL }; =20 static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInf= o *ri, @@ -7427,7 +7377,6 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .cp =3D 14, .crn =3D 2, .crm =3D 0, .opc1 =3D 7, .opc2 =3D 0, .accessfn =3D access_joscr_jmcr, .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo vhe_reginfo[] =3D { @@ -7492,7 +7441,6 @@ static const ARMCPRegInfo vhe_reginfo[] =3D { .access =3D PL2_RW, .accessfn =3D e2h_access, .writefn =3D gt_virt_cval_write, .raw_writefn =3D raw_write }, #endif - REGINFO_SENTINEL }; =20 #ifndef CONFIG_USER_ONLY @@ -7505,7 +7453,6 @@ static const ARMCPRegInfo ats1e1_reginfo[] =3D { .opc0 =3D 1, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write64 }, - REGINFO_SENTINEL }; =20 static const ARMCPRegInfo ats1cp_reginfo[] =3D { @@ -7517,7 +7464,6 @@ static const ARMCPRegInfo ats1cp_reginfo[] =3D { .cp =3D 15, .opc1 =3D 0, .crn =3D 7, .crm =3D 9, .opc2 =3D 1, .access =3D PL1_W, .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write }, - REGINFO_SENTINEL }; #endif =20 @@ -7539,7 +7485,6 @@ static const ARMCPRegInfo actlr2_hactlr2_reginfo[] = =3D { .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 3, .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; =20 void register_cp_regs_for_features(ARMCPU *cpu) @@ -7646,7 +7591,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .accessfn =3D access_aa32_tid3, .resetvalue =3D cpu->isar.id_isar6 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, v6_idregs); define_arm_cp_regs(cpu, v6_cp_reginfo); @@ -7914,7 +7858,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 3, .crn =3D 9, .crm =3D 12, .opc2 =3D= 7, .access =3D PL0_R, .accessfn =3D pmreg_access, .type =3D ARM= _CP_CONST, .resetvalue =3D cpu->pmceid1 }, - REGINFO_SENTINEL }; #ifdef CONFIG_USER_ONLY ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { @@ -7944,7 +7887,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .exported_bits =3D 0x000000f0ffffffff }, { .name =3D "ID_AA64ISAR*_EL1_RESERVED", .is_glob =3D true }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(v8_idregs, v8_user_idregs); #endif @@ -7984,7 +7926,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL2_RW, .resetvalue =3D vmpidr_def, .fieldoffset =3D offsetof(CPUARMState, cp15.vmpidr_el2) }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el2_cp_reginfo); @@ -8023,7 +7964,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, .type =3D ARM_CP_NO_RAW, .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vpidr_regs); define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); @@ -8046,7 +7986,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .raw_writefn =3D raw_write, .writefn =3D sctlr_write, .fieldoffset =3D offsetof(CPUARMState, cp15.sctlr_el[3]), .resetvalue =3D cpu->reset_sctlr }, - REGINFO_SENTINEL }; =20 define_arm_cp_regs(cpu, el3_regs); @@ -8181,7 +8120,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "DUMMY", .cp =3D 15, .crn =3D 0, .crm =3D 7, .opc1 =3D 0, .opc2 =3D C= P_ANY, .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D 0= }, - REGINFO_SENTINEL }; ARMCPRegInfo id_v8_midr_cp_reginfo[] =3D { { .name =3D "MIDR_EL1", .state =3D ARM_CP_STATE_BOTH, @@ -8201,7 +8139,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_aa64_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->revidr }, - REGINFO_SENTINEL }; ARMCPRegInfo id_cp_reginfo[] =3D { /* These are common to v8 and pre-v8 */ @@ -8219,7 +8156,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .accessfn =3D access_aa32_tid1, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; /* TLBTR is specific to VMSA */ ARMCPRegInfo id_tlbtr_reginfo =3D { @@ -8246,25 +8182,23 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MIDR_EL1", .exported_bits =3D 0x00000000ffffffff }, { .name =3D "REVIDR_EL1" }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(id_v8_midr_cp_reginfo, id_v8_user_midr_cp_regin= fo); #endif if (arm_feature(env, ARM_FEATURE_OMAPCP) || arm_feature(env, ARM_FEATURE_STRONGARM)) { - ARMCPRegInfo *r; + size_t i; /* Register the blanket "writes ignored" value first to cover = the * whole space. Then update the specific ID registers to allow= write * access, so that they ignore writes rather than causing them= to * UNDEF. */ define_one_arm_cp_reg(cpu, &crn0_wi_reginfo); - for (r =3D id_pre_v8_midr_cp_reginfo; - r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; + for (i =3D 0; i < ARRAY_SIZE(id_pre_v8_midr_cp_reginfo); ++i) { + id_pre_v8_midr_cp_reginfo[i].access =3D PL1_RW; } - for (r =3D id_cp_reginfo; r->type !=3D ARM_CP_SENTINEL; r++) { - r->access =3D PL1_RW; + for (i =3D 0; i < ARRAY_SIZE(id_cp_reginfo); ++i) { + id_cp_reginfo[i].access =3D PL1_RW; } id_mpuir_reginfo.access =3D PL1_RW; id_tlbtr_reginfo.access =3D PL1_RW; @@ -8287,13 +8221,11 @@ void register_cp_regs_for_features(ARMCPU *cpu) { .name =3D "MPIDR_EL1", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 0, .crm =3D 0, .opc1 =3D 0, .opc2 =3D = 5, .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, - REGINFO_SENTINEL }; #ifdef CONFIG_USER_ONLY ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .fixed_bits =3D 0x0000000080000000 }, - REGUSERINFO_SENTINEL }; modify_arm_cp_regs(mpidr_cp_reginfo, mpidr_user_cp_reginfo); #endif @@ -8314,7 +8246,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 0, .opc2 =3D = 1, .access =3D PL3_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, auxcr_reginfo); if (cpu_isar_feature(aa32_ac2, cpu)) { @@ -8349,7 +8280,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .type =3D ARM_CP_CONST, .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 3, .opc2= =3D 0, .access =3D PL1_R, .resetvalue =3D cpu->reset_cbar }, - REGINFO_SENTINEL }; /* We don't implement a r/w 64 bit CBAR currently */ assert(arm_feature(env, ARM_FEATURE_CBAR_RO)); @@ -8379,7 +8309,6 @@ void register_cp_regs_for_features(ARMCPU *cpu) .bank_fieldoffsets =3D { offsetof(CPUARMState, cp15.vbar_s), offsetof(CPUARMState, cp15.vbar_ns) }, .resetvalue =3D 0 }, - REGINFO_SENTINEL }; define_arm_cp_regs(cpu, vbar_cp_reginfo); } @@ -8833,8 +8762,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->writefn); } } - /* Bad type field probably means missing sentinel at end of reg list */ - assert(cptype_valid(r->type)); + for (crm =3D crmmin; crm <=3D crmmax; crm++) { for (opc1 =3D opc1min; opc1 <=3D opc1max; opc1++) { for (opc2 =3D opc2min; opc2 <=3D opc2max; opc2++) { @@ -8880,13 +8808,13 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, } } =20 -void define_arm_cp_regs_with_opaque(ARMCPU *cpu, - const ARMCPRegInfo *regs, void *opaque) +/* Define a whole list of registers */ +void define_arm_cp_regs_with_opaque_len(ARMCPU *cpu, const ARMCPRegInfo *r= egs, + void *opaque, size_t len) { - /* Define a whole list of registers */ - const ARMCPRegInfo *r; - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { - define_one_arm_cp_reg_with_opaque(cpu, r, opaque); + size_t i; + for (i =3D 0; i < len; ++i) { + define_one_arm_cp_reg_with_opaque(cpu, regs + i, opaque); } } =20 @@ -8898,17 +8826,20 @@ void define_arm_cp_regs_with_opaque(ARMCPU *cpu, * user-space cannot alter any values and dynamic values pertaining to * execution state are hidden from user space view anyway. */ -void modify_arm_cp_regs(ARMCPRegInfo *regs, const ARMCPRegUserSpaceInfo *m= ods) +void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, size_t regs_len, + const ARMCPRegUserSpaceInfo *mods, + size_t mods_len) { - const ARMCPRegUserSpaceInfo *m; - ARMCPRegInfo *r; - - for (m =3D mods; m->name; m++) { + for (size_t mi =3D 0; mi < mods_len; ++mi) { + const ARMCPRegUserSpaceInfo *m =3D mods + mi; GPatternSpec *pat =3D NULL; + if (m->is_glob) { pat =3D g_pattern_spec_new(m->name); } - for (r =3D regs; r->type !=3D ARM_CP_SENTINEL; r++) { + for (size_t ri =3D 0; ri < regs_len; ++ri) { + ARMCPRegInfo *r =3D regs + ri; + if (pat && g_pattern_match_string(pat, r->name)) { r->type =3D ARM_CP_CONST; r->access =3D PL0U_R; --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651384520470263.76788643806594; Sat, 30 Apr 2022 22:55:20 -0700 (PDT) Received: from localhost ([::1]:45892 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2YB-0001gH-DL for importer@patchew.org; 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Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index a68f14fe8e..ca6ba9bd82 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7860,7 +7860,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .resetvalue =3D cpu->pmceid1 }, }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { + static const ARMCPRegUserSpaceInfo v8_user_idregs[] =3D { { .name =3D "ID_AA64PFR0_EL1", .exported_bits =3D 0x000f000f00ff0000, .fixed_bits =3D 0x0000000000000011 }, @@ -8000,7 +8000,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) */ if (arm_feature(env, ARM_FEATURE_EL3)) { if (arm_feature(env, ARM_FEATURE_AARCH64)) { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL1_RW, .accessfn =3D nsacr_access, @@ -8008,7 +8008,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &nsacr); } else { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL3_RW | PL1_R, @@ -8019,7 +8019,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } } else { if (arm_feature(env, ARM_FEATURE_V8)) { - ARMCPRegInfo nsacr =3D { + static const ARMCPRegInfo nsacr =3D { .name =3D "NSACR", .type =3D ARM_CP_CONST, .cp =3D 15, .opc1 =3D 0, .crn =3D 1, .crm =3D 1, .opc2 =3D= 2, .access =3D PL1_R, @@ -8172,13 +8172,13 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .type =3D ARM_CP_CONST, .resetvalue =3D cpu->pmsav7_dregion << 8 }; - ARMCPRegInfo crn0_wi_reginfo =3D { + static const ARMCPRegInfo crn0_wi_reginfo =3D { .name =3D "CRN0_WI", .cp =3D 15, .crn =3D 0, .crm =3D CP_ANY, .opc1 =3D CP_ANY, .opc2 =3D CP_ANY, .access =3D PL1_W, .type =3D ARM_CP_NOP | ARM_CP_OVERRIDE }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] =3D { + static const ARMCPRegUserSpaceInfo id_v8_user_midr_cp_reginfo[] = =3D { { .name =3D "MIDR_EL1", .exported_bits =3D 0x00000000ffffffff }, { .name =3D "REVIDR_EL1" }, @@ -8223,7 +8223,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) .access =3D PL1_R, .readfn =3D mpidr_read, .type =3D ARM_CP_= NO_RAW }, }; #ifdef CONFIG_USER_ONLY - ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { + static const ARMCPRegUserSpaceInfo mpidr_user_cp_reginfo[] =3D { { .name =3D "MPIDR_EL1", .fixed_bits =3D 0x0000000080000000 }, }; @@ -8302,7 +8302,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (arm_feature(env, ARM_FEATURE_VBAR)) { - ARMCPRegInfo vbar_cp_reginfo[] =3D { + static const ARMCPRegInfo vbar_cp_reginfo[] =3D { { .name =3D "VBAR", .state =3D ARM_CP_STATE_BOTH, .opc0 =3D 3, .crn =3D 12, .crm =3D 0, .opc1 =3D 0, .opc2 =3D= 0, .access =3D PL1_RW, .writefn =3D vbar_write, --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385068; cv=none; d=zohomail.com; s=zohoarc; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:34 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0Jy4lKNsi/GmAwKF8EkIwL7sXr4vu9r6V+LNjfDB8TI=; b=Tp+hSzokrxeKUmHFrVkD+SLzuiST0fHFv46BCR3ibeqZK07xyemlNk5+rfS1Cd4G22 TCr382uzoQmsqi7K2R1wU+Xf8EMYue7soOP57b/vajWdjRvewb47kp6oLb0t+lt9DetL UlxZO86xFmFTcd8hkaZmL7dRm7LZRGT8JR3hpbaSRLvI/DCVnw7z7Y9U8rPMXX2L5IPh T55Gs7zI5cwn1cmYvJ1hX7wCl+cLYJ+Rm6TSXVqTCyliADd7vD5dFKKn+Anxf44N6GRB 5sqDwakl1Zhw50cwwSto52LETuxQ6/7kvYVQEW7htAj3wkxHtrttdvsaw+BxSiH9unr2 J5Jw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0Jy4lKNsi/GmAwKF8EkIwL7sXr4vu9r6V+LNjfDB8TI=; b=UxcII0efG8aH9nbC62hcuqKhKBxxBHKKEXWpoK4v1+X0WivyUSQuTSklcjqHMr+sSt fimx1+G3rLcYa9yqtAOjeOc/IeCGnJhCN76teNK92wJFwm4flb0oFV2wo6bEoCyCRaL6 Ze7Dvz3AmP7OWcrwEA0ROudNd07/Dyy/jzhROcouaL9wBd49Wg4ENL7d0kw6KFYn9zTs FpBKR40nCdn5v3cbtN40gU4wS5jZhx5JjoF/jQ2p0Mwc27HTPz+R0+1a1wgXVE+K27+v f82TUOpDNRbOnnbEuk1BAQ3IeNdGOzRrOGtZV5NtmevqNQcq08XUek8x0or8H9rBQURu X2/w== X-Gm-Message-State: AOAM531hMsUR5qn8945K8YVUJsAhBvLUwWOPdz4+EUPrkPDQ0cVW5FKo W9x7/wqzZrwZpuSQRk+njNq7MxmkZ6DxAQ== X-Google-Smtp-Source: ABdhPJzF6xrxM63g1wza8+eovLAOOGwhVKhp2dpSEQYMaecsOMONjc/V1Lh0iExIzAbCulAScJ2ViA== X-Received: by 2002:a05:6a00:2310:b0:505:a8ac:40e7 with SMTP id h16-20020a056a00231000b00505a8ac40e7mr6291405pfh.11.1651384235168; Sat, 30 Apr 2022 22:50:35 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 05/45] target/arm: Reorg ARMCPRegInfo type field bits Date: Sat, 30 Apr 2022 22:49:47 -0700 Message-Id: <20220501055028.646596-6-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::429; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x429.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385070504100001 Content-Type: text/plain; charset="utf-8" Instead of defining ARM_CP_FLAG_MASK to remove flags, define ARM_CP_SPECIAL_MASK to isolate special cases. Sort the specials to the low bits. Use an enum. Split the large comment block so as to document each value separately. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4: Revert merge of ARM_CP_CONST with ARM_CP_NOP. --- target/arm/cpregs.h | 130 +++++++++++++++++++++++-------------- target/arm/cpu.c | 4 +- target/arm/helper.c | 4 +- target/arm/translate-a64.c | 6 +- target/arm/translate.c | 6 +- 5 files changed, 92 insertions(+), 58 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index a5231504d5..ff3817decb 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -22,57 +22,87 @@ #define TARGET_ARM_CPREGS_H =20 /* - * ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a - * special-behaviour cp reg and bits [11..8] indicate what behaviour - * it has. Otherwise it is a simple cp reg, where CONST indicates that - * TCG can assume the value to be constant (ie load at translate time) - * and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END - * indicates that the TB should not be ended after a write to this register - * (the default is that the TB ends after cp writes). OVERRIDE permits - * a register definition to override a previous definition for the - * same (cp, is64, crn, crm, opc1, opc2) tuple: either the new or the - * old must have the OVERRIDE bit set. - * ALIAS indicates that this register is an alias view of some underlying - * state which is also visible via another register, and that the other - * register is handling migration and reset; registers marked ALIAS will n= ot be - * migrated but may have their state set by syncing of register state from= KVM. - * NO_RAW indicates that this register has no underlying state and does not - * support raw access for state saving/loading; it will not be used for ei= ther - * migration or KVM state synchronization. (Typically this is for "registe= rs" - * which are actually used as instructions for cache maintenance and so on= .) - * IO indicates that this register does I/O and therefore its accesses - * need to be marked with gen_io_start() and also end the TB. In particula= r, - * registers which implement clocks or timers require this. - * RAISES_EXC is for when the read or write hook might raise an exception; - * the generated code will synchronize the CPU state before calling the ho= ok - * so that it is safe for the hook to call raise_exception(). - * NEWEL is for writes to registers that might change the exception - * level - typically on older ARM chips. For those cases we need to - * re-read the new el when recomputing the translation flags. + * ARMCPRegInfo type field bits: */ -#define ARM_CP_SPECIAL 0x0001 -#define ARM_CP_CONST 0x0002 -#define ARM_CP_64BIT 0x0004 -#define ARM_CP_SUPPRESS_TB_END 0x0008 -#define ARM_CP_OVERRIDE 0x0010 -#define ARM_CP_ALIAS 0x0020 -#define ARM_CP_IO 0x0040 -#define ARM_CP_NO_RAW 0x0080 -#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100) -#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200) -#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300) -#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400) -#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500) -#define ARM_CP_DC_GVA (ARM_CP_SPECIAL | 0x0600) -#define ARM_CP_DC_GZVA (ARM_CP_SPECIAL | 0x0700) -#define ARM_LAST_SPECIAL ARM_CP_DC_GZVA -#define ARM_CP_FPU 0x1000 -#define ARM_CP_SVE 0x2000 -#define ARM_CP_NO_GDB 0x4000 -#define ARM_CP_RAISES_EXC 0x8000 -#define ARM_CP_NEWEL 0x10000 -/* Mask of only the flag bits in a type field */ -#define ARM_CP_FLAG_MASK 0x1f0ff +enum { + /* + * Register must be handled specially during translation. + * The method is one of the values below: + */ + ARM_CP_SPECIAL_MASK =3D 0x000f, + /* Special: no change to PE state: writes ignored, reads ignored. */ + ARM_CP_NOP =3D 0x0001, + /* Special: sysreg is WFI, for v5 and v6. */ + ARM_CP_WFI =3D 0x0002, + /* Special: sysreg is NZCV. */ + ARM_CP_NZCV =3D 0x0003, + /* Special: sysreg is CURRENTEL. */ + ARM_CP_CURRENTEL =3D 0x0004, + /* Special: sysreg is DC ZVA or similar. */ + ARM_CP_DC_ZVA =3D 0x0005, + ARM_CP_DC_GVA =3D 0x0006, + ARM_CP_DC_GZVA =3D 0x0007, + + /* Flag: reads produce resetvalue; writes ignored. */ + ARM_CP_CONST =3D 1 << 4, + /* Flag: For ARM_CP_STATE_AA32, sysreg is 64-bit. */ + ARM_CP_64BIT =3D 1 << 5, + /* + * Flag: TB should not be ended after a write to this register + * (the default is that the TB ends after cp writes). + */ + ARM_CP_SUPPRESS_TB_END =3D 1 << 6, + /* + * Flag: Permit a register definition to override a previous definition + * for the same (cp, is64, crn, crm, opc1, opc2) tuple: either the new + * or the old must have the ARM_CP_OVERRIDE bit set. + */ + ARM_CP_OVERRIDE =3D 1 << 7, + /* + * Flag: Register is an alias view of some underlying state which is a= lso + * visible via another register, and that the other register is handli= ng + * migration and reset; registers marked ARM_CP_ALIAS will not be migr= ated + * but may have their state set by syncing of register state from KVM. + */ + ARM_CP_ALIAS =3D 1 << 8, + /* + * Flag: Register does I/O and therefore its accesses need to be marked + * with gen_io_start() and also end the TB. In particular, registers w= hich + * implement clocks or timers require this. + */ + ARM_CP_IO =3D 1 << 9, + /* + * Flag: Register has no underlying state and does not support raw acc= ess + * for state saving/loading; it will not be used for either migration = or + * KVM state synchronization. Typically this is for "registers" which = are + * actually used as instructions for cache maintenance and so on. + */ + ARM_CP_NO_RAW =3D 1 << 10, + /* + * Flag: The read or write hook might raise an exception; the generated + * code will synchronize the CPU state before calling the hook so that= it + * is safe for the hook to call raise_exception(). + */ + ARM_CP_RAISES_EXC =3D 1 << 11, + /* + * Flag: Writes to the sysreg might change the exception level - typic= ally + * on older ARM chips. For those cases we need to re-read the new el w= hen + * recomputing the translation flags. + */ + ARM_CP_NEWEL =3D 1 << 12, + /* + * Flag: Access check for this sysreg is identical to accessing FPU st= ate + * from an instruction: use translation fp_access_check(). + */ + ARM_CP_FPU =3D 1 << 13, + /* + * Flag: Access check for this sysreg is identical to accessing SVE st= ate + * from an instruction: use translation sve_access_check(). + */ + ARM_CP_SVE =3D 1 << 14, + /* Flag: Do not expose in gdb sysreg xml. */ + ARM_CP_NO_GDB =3D 1 << 15, +}; =20 /* * Valid values for ARMCPRegInfo state field, indicating which of diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 815add74fa..268274ce89 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -117,7 +117,7 @@ static void cp_reg_reset(gpointer key, gpointer value, = gpointer opaque) ARMCPRegInfo *ri =3D value; ARMCPU *cpu =3D opaque; =20 - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS)) { return; } =20 @@ -153,7 +153,7 @@ static void cp_reg_check_reset(gpointer key, gpointer v= alue, gpointer opaque) ARMCPU *cpu =3D opaque; uint64_t oldvalue, newvalue; =20 - if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { + if (ri->type & (ARM_CP_SPECIAL_MASK | ARM_CP_ALIAS | ARM_CP_NO_RAW)) { return; } =20 diff --git a/target/arm/helper.c b/target/arm/helper.c index ca6ba9bd82..f84377babe 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8600,7 +8600,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if ((r->type & ARM_CP_SPECIAL)) { + if (r->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || @@ -8750,7 +8750,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, /* Check that the register definition has enough info to handle * reads and writes if they are permitted. */ - if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) { + if (!(r->type & (ARM_CP_SPECIAL_MASK | ARM_CP_CONST))) { if (r->access & PL3_R) { assert((r->fieldoffset || (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1])) || diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 348a638c5c..a82f5d5984 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1833,7 +1833,9 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } =20 /* Handle special cases first */ - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { + switch (ri->type & ARM_CP_SPECIAL_MASK) { + case 0: + break; case ARM_CP_NOP: return; case ARM_CP_NZCV: @@ -1908,7 +1910,7 @@ static void handle_sys(DisasContext *s, uint32_t insn= , bool isread, } return; default: - break; + g_assert_not_reached(); } if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) { return; diff --git a/target/arm/translate.c b/target/arm/translate.c index fc7917cdf4..050c237b07 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -4744,7 +4744,9 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, } =20 /* Handle special cases first */ - switch (ri->type & ~(ARM_CP_FLAG_MASK & ~ARM_CP_SPECIAL)) { + switch (ri->type & ARM_CP_SPECIAL_MASK) { + case 0: + break; case ARM_CP_NOP: return; case ARM_CP_WFI: @@ -4756,7 +4758,7 @@ static void do_coproc_insn(DisasContext *s, int cpnum= , int is64, s->base.is_jmp =3D DISAS_WFI; return; default: - break; + g_assert_not_reached(); } =20 if ((tb_cflags(s->base.tb) & CF_USE_ICOUNT) && (ri->type & ARM_CP_= IO)) { --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385416; cv=none; d=zohomail.com; s=zohoarc; b=h/9VbtaPNXSZDFeGUtOKDPXQ0Gg+MAcjNwPRhvKbyyg6APy1aVvnMGsxyeYQo6++eJnSXVU5MG+c4a4kvK+Y8OQ1kOqbig/JgN++fN4BH2x44L9/m6ZrRn1FfG/Zgh3oQ3zLwSiqF1KtgnHOwJuHM6UqQYsOq+D12Mkj6pySDCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385416; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=8BvhoITH3FbicdDtJZOWptl87d3wC+1SbojQuSuWgZM=; b=IFIMe+UmLU/7Ilh27L8soUYcy46gMR/JAIlwcDBl6T5xxUtktQmYX7qZdJGA0A6GoOgkfLKOWWYAQWJZs7FmVTK6FCm3U9UfSmxyDo0xfONoeKaYimXsUGwaFUkcThrulv2qT+dYnNf/Czgpmv7SK9c5tva2FR8LfMpbDTLotbw= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385416689834.9797041133563; Sat, 30 Apr 2022 23:10:16 -0700 (PDT) Received: from localhost ([::1]:38658 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2mc-0007jR-2D for importer@patchew.org; Sun, 01 May 2022 02:10:15 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43128) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tf-0006p9-F8 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:39 -0400 Received: from mail-pf1-x432.google.com ([2607:f8b0:4864:20::432]:41765) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Td-0001FB-Gu for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:39 -0400 Received: by mail-pf1-x432.google.com with SMTP id p8so10064502pfh.8 for ; Sat, 30 Apr 2022 22:50:37 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:35 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=8BvhoITH3FbicdDtJZOWptl87d3wC+1SbojQuSuWgZM=; b=rmjRGSv++zQZftdfZDjSEoY8KklB3Mj94/CJHnu1OYhT/pD6bAK1NpzE3x9qmkbGIT yHiWs2ccDuAsj7XpmJc+L+6n1gGB0Ft2NTkmqG4M75AKjfVkEFiwVumypxe9l5MRtifZ BzLBWrA/Ui67fhWC6m9ksJo6i0bkxbYRRyp47zgQEhcS1R0QiqJcbAgK/rv2kRZLdgx8 HgXcVyPXDKye7TqL+vUaF8oyoRwZwuJpolg6CS8H8oGqmTr6LKjn7CgWk1O4Eb7c9q8p BYXIY4VTUWLRLjncC0F100wXJjrFAo1Qxy99m8syLmAO2nmpQbeOfeyujleOV/ibJmsQ BnTw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=8BvhoITH3FbicdDtJZOWptl87d3wC+1SbojQuSuWgZM=; b=sxTxfIUdA3I6BVMVDYAA97jfOr0Y46HDU/HcLc7mcpzkH3Z8HO2KhwyUkhWmjtv5+z Bxa4OFgt2a+jJ/6typNVb9acpel7psxGARXiwVzDf/7l4bOYrzP2QAeq21MZw5LTy/Cj L/eClIzRI3P3G363OASD0AUuRAjgvpZ/oc+z6n4Bb5MEDNYedgmjQOUsroZOU523nBGs sojxl3ehBGy+NZR5YOHUCjMkWPorDCvvwzoLkjQRqikbXoiJSQ0KL9w3anOGJWPXR0aL MQnICVxN8fCzZM00b93M895VH6OEuEkGDeXJu/39uFuwdy4s0ACjgKagWsLMU/uFzyUG OReA== X-Gm-Message-State: AOAM533VfIQfvY4Qp0uObX0IAZxq8bOKFnjjX4wRfpx5xtGJK3Hl1L3R UFFsh9sjwAXbBJcK63UAHRLa3DtDKpY7UQ== X-Google-Smtp-Source: ABdhPJwh4mvAxwDlssIFrNuywuOe84L926xBtANlSRqX5MddtUWC52hyu+lOt/Q20QvzRLYqtTBglA== X-Received: by 2002:a05:6a00:23d3:b0:50d:9044:4297 with SMTP id g19-20020a056a0023d300b0050d90444297mr5957148pfc.43.1651384236157; Sat, 30 Apr 2022 22:50:36 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 06/45] target/arm: Avoid bare abort() or assert(0) Date: Sat, 30 Apr 2022 22:49:48 -0700 Message-Id: <20220501055028.646596-7-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::432; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x432.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385418106100001 Content-Type: text/plain; charset="utf-8" Standardize on g_assert_not_reached() for "should not happen". Retain abort() when preceeded by fprintf or error_report. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4: new. --- target/arm/helper.c | 7 +++---- target/arm/hvf/hvf.c | 2 +- target/arm/kvm-stub.c | 4 ++-- target/arm/kvm.c | 4 ++-- target/arm/machine.c | 4 ++-- target/arm/translate-a64.c | 4 ++-- target/arm/translate-neon.c | 2 +- target/arm/translate.c | 4 ++-- 8 files changed, 15 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f84377babe..06f8864c77 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8740,8 +8740,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, break; default: /* broken reginfo with out-of-range opc1 */ - assert(false); - break; + g_assert_not_reached(); } /* assert our permissions are not too lax (stricter is fine) */ assert((r->access & ~mask) =3D=3D 0); @@ -10823,7 +10822,7 @@ static bool get_phys_addr_v5(CPUARMState *env, uint= 32_t address, break; default: /* Never happens, but compiler isn't smart enough to tell. */ - abort(); + g_assert_not_reached(); } } *prot =3D ap_to_rw_prot(env, mmu_idx, ap, domain_prot); @@ -10944,7 +10943,7 @@ static bool get_phys_addr_v6(CPUARMState *env, uint= 32_t address, break; default: /* Never happens, but compiler isn't smart enough to tell. */ - abort(); + g_assert_not_reached(); } } if (domain_prot =3D=3D 3) { diff --git a/target/arm/hvf/hvf.c b/target/arm/hvf/hvf.c index b11a8b9a18..86710509d2 100644 --- a/target/arm/hvf/hvf.c +++ b/target/arm/hvf/hvf.c @@ -1200,7 +1200,7 @@ int hvf_vcpu_exec(CPUState *cpu) /* we got kicked, no exit to process */ return 0; default: - assert(0); + g_assert_not_reached(); } =20 hvf_sync_vtimer(cpu); diff --git a/target/arm/kvm-stub.c b/target/arm/kvm-stub.c index 56a7099e6b..965a486b32 100644 --- a/target/arm/kvm-stub.c +++ b/target/arm/kvm-stub.c @@ -15,10 +15,10 @@ =20 bool write_kvmstate_to_list(ARMCPU *cpu) { - abort(); + g_assert_not_reached(); } =20 bool write_list_to_kvmstate(ARMCPU *cpu, int level) { - abort(); + g_assert_not_reached(); } diff --git a/target/arm/kvm.c b/target/arm/kvm.c index 5fc37ac10a..4339e1cd6e 100644 --- a/target/arm/kvm.c +++ b/target/arm/kvm.c @@ -540,7 +540,7 @@ bool write_kvmstate_to_list(ARMCPU *cpu) ret =3D kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); break; default: - abort(); + g_assert_not_reached(); } if (ret) { ok =3D false; @@ -575,7 +575,7 @@ bool write_list_to_kvmstate(ARMCPU *cpu, int level) r.addr =3D (uintptr_t)(cpu->cpreg_values + i); break; default: - abort(); + g_assert_not_reached(); } ret =3D kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { diff --git a/target/arm/machine.c b/target/arm/machine.c index 135d2420b5..285e387d2c 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -661,7 +661,7 @@ static int cpu_pre_save(void *opaque) if (kvm_enabled()) { if (!write_kvmstate_to_list(cpu)) { /* This should never fail */ - abort(); + g_assert_not_reached(); } =20 /* @@ -672,7 +672,7 @@ static int cpu_pre_save(void *opaque) } else { if (!write_cpustate_to_list(cpu, false)) { /* This should never fail. */ - abort(); + g_assert_not_reached(); } } =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index a82f5d5984..b80313670f 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -6151,7 +6151,7 @@ static void handle_fp_1src_half(DisasContext *s, int = opcode, int rd, int rn) gen_helper_advsimd_rinth(tcg_res, tcg_op, fpst); break; default: - abort(); + g_assert_not_reached(); } =20 write_fp_sreg(s, rd, tcg_res); @@ -6392,7 +6392,7 @@ static void handle_fp_fcvt(DisasContext *s, int opcod= e, break; } default: - abort(); + g_assert_not_reached(); } } =20 diff --git a/target/arm/translate-neon.c b/target/arm/translate-neon.c index 2e4d1ec87d..321c17e2c7 100644 --- a/target/arm/translate-neon.c +++ b/target/arm/translate-neon.c @@ -679,7 +679,7 @@ static bool trans_VLDST_single(DisasContext *s, arg_VLD= ST_single *a) } break; default: - abort(); + g_assert_not_reached(); } if ((vd + a->stride * (nregs - 1)) > 31) { /* diff --git a/target/arm/translate.c b/target/arm/translate.c index 050c237b07..4e19191ed5 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -5156,7 +5156,7 @@ static void gen_srs(DisasContext *s, offset =3D 4; break; default: - abort(); + g_assert_not_reached(); } tcg_gen_addi_i32(addr, addr, offset); tmp =3D load_reg(s, 14); @@ -5181,7 +5181,7 @@ static void gen_srs(DisasContext *s, offset =3D 0; break; default: - abort(); + g_assert_not_reached(); } tcg_gen_addi_i32(addr, addr, offset); gen_helper_set_r13_banked(cpu_env, tcg_constant_i32(mode), addr); --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651384598109419.6292926072199; Sat, 30 Apr 2022 22:56:38 -0700 (PDT) Received: from localhost ([::1]:47280 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2ZR-0002ZW-1w for importer@patchew.org; Sun, 01 May 2022 01:56:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43192) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tg-0006r9-Ms for qemu-devel@nongnu.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:36 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=l24vNO9OZYnbJW/GHWCEkkxLEwARIGf3x7c7vn+v7Fw=; b=ISbG847TZ1rPqQENG/Qv7gHm/A4fVxCK5MmpYFB1xIJ8hPU7K69IlHdaF9mikgY2x6 Eqzm732cAhyLMy7Rrr31TdI91E7waB7t2jEP4/cv7iW7oUx9XCfT3x4bj/zoFx+oRPbl FqAGEgwvhNS2O6ViuRxEWG0Jk0WYCDwNGt/UvFrvKxzOoYhJ4bXbmyREgeCa33enadvt anqbnevNwqES3cqy8t+Ecfq6V2j6mXMZqSSu5ZDyjeHRZhFevpkTuUi03wBH9OIaOMF8 bz3llUVIwiNyyQ0vUqtrCH1ki67eVPxwn3noExbIA3pNXz+YocdcdfBC21Dr4/ep+qPv vfLA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=l24vNO9OZYnbJW/GHWCEkkxLEwARIGf3x7c7vn+v7Fw=; b=Ov41L5QRql0Qr9Fh76IexcaT1Fa4QRkcRo5OZ9x/prp8ujF/kQAUesLJ5t3qn+XlXn n7MSa51/kwkrvObziZin4WBeQb6u+wUaxPScK3w0Stt5Uwgt3/didxNb6uQKRRl9RGX0 fbyqy0XwHK52LVQ1+h7Qra7mVUBDr8Oky0Wx0DtFjuMYjS4fXF3H2kFj4khvCW3Rh7ML QnUoIfz+vxPmFq+kHoJK988IzN/rOkVSHkDx2Zmy2MXrrjPTvOHxU6yrO6K01fIDAyjn u9BVd6jKhBlRlC6sDAwlSVpigAaHoDi78/og9pGQteD49+0tkmFeKWPPEz5/padlMGm0 jpRQ== X-Gm-Message-State: AOAM533G/Y+c71sq1dcpINXj6hRolltzhLbQf+e3Cxzp1RrMY+GO0wX2 8jRB2MBIluvLbYNsNTqk+wO8UxJrgR9+zw== X-Google-Smtp-Source: ABdhPJz93Bx7Y5+HmBMRBz0zEmA/TJKFa7TpApDqk53xEyDXRNvj4mmp7cr5uRs5w3Do2Ij44cdpSQ== X-Received: by 2002:a05:6a00:114e:b0:4c8:55f7:faad with SMTP id b14-20020a056a00114e00b004c855f7faadmr6009567pfm.86.1651384237229; Sat, 30 Apr 2022 22:50:37 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 07/45] target/arm: Change cpreg access permissions to enum Date: Sat, 30 Apr 2022 22:49:49 -0700 Message-Id: <20220501055028.646596-8-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::535; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x535.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651384599290100001 Content-Type: text/plain; charset="utf-8" Create a typedef as well, and use it in ARMCPRegInfo. This won't be perfect for debugging, but it'll nicely display the most common cases. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 44 +++++++++++++++++++++++--------------------- target/arm/helper.c | 2 +- 2 files changed, 24 insertions(+), 22 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index ff3817decb..858c5da57d 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -154,31 +154,33 @@ enum { * described with these bits, then use a laxer set of restrictions, and * do the more restrictive/complex check inside a helper function. */ -#define PL3_R 0x80 -#define PL3_W 0x40 -#define PL2_R (0x20 | PL3_R) -#define PL2_W (0x10 | PL3_W) -#define PL1_R (0x08 | PL2_R) -#define PL1_W (0x04 | PL2_W) -#define PL0_R (0x02 | PL1_R) -#define PL0_W (0x01 | PL1_W) +typedef enum { + PL3_R =3D 0x80, + PL3_W =3D 0x40, + PL2_R =3D 0x20 | PL3_R, + PL2_W =3D 0x10 | PL3_W, + PL1_R =3D 0x08 | PL2_R, + PL1_W =3D 0x04 | PL2_W, + PL0_R =3D 0x02 | PL1_R, + PL0_W =3D 0x01 | PL1_W, =20 -/* - * For user-mode some registers are accessible to EL0 via a kernel - * trap-and-emulate ABI. In this case we define the read permissions - * as actually being PL0_R. However some bits of any given register - * may still be masked. - */ + /* + * For user-mode some registers are accessible to EL0 via a kernel + * trap-and-emulate ABI. In this case we define the read permissions + * as actually being PL0_R. However some bits of any given register + * may still be masked. + */ #ifdef CONFIG_USER_ONLY -#define PL0U_R PL0_R + PL0U_R =3D PL0_R, #else -#define PL0U_R PL1_R + PL0U_R =3D PL1_R, #endif =20 -#define PL3_RW (PL3_R | PL3_W) -#define PL2_RW (PL2_R | PL2_W) -#define PL1_RW (PL1_R | PL1_W) -#define PL0_RW (PL0_R | PL0_W) + PL3_RW =3D PL3_R | PL3_W, + PL2_RW =3D PL2_R | PL2_W, + PL1_RW =3D PL1_R | PL1_W, + PL0_RW =3D PL0_R | PL0_W, +} CPAccessRights; =20 typedef enum CPAccessResult { /* Access is permitted */ @@ -262,7 +264,7 @@ struct ARMCPRegInfo { /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ - int access; + CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ int secure; /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 06f8864c77..a19e04bb0b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8711,7 +8711,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * to encompass the generic architectural permission check. */ if (r->state !=3D ARM_CP_STATE_AA32) { - int mask =3D 0; + CPAccessRights mask; switch (r->opc1) { case 0: /* min_EL EL1, but some accessible to EL0 via kernel ABI */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385768456326.79467512011513; Sat, 30 Apr 2022 23:16:08 -0700 (PDT) Received: from localhost ([::1]:45554 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2sI-00044F-RQ for importer@patchew.org; Sun, 01 May 2022 02:16:06 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43274) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tl-0006sD-Q0 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:51 -0400 Received: from mail-pf1-x434.google.com ([2607:f8b0:4864:20::434]:33475) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tf-0001Fu-I2 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:41 -0400 Received: by mail-pf1-x434.google.com with SMTP id p12so10115747pfn.0 for ; Sat, 30 Apr 2022 22:50:39 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:37 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=M9JbA/4mJJzCg1BoSjOe8spAl/jM5dv9tZGOFooq9Lk=; b=GDlZxwmsilH0VCieHvbKqLSaZdinDddfExXGJxEUWq5g7Zr/2y+r80sk/zwG8pKSqS OyaX+S1i9GhnPI6EZgGiDQCIe24Ufy5AINb+xHSEyGYy6d7W3jRRGnQknmfYnEZScOio oxBGonrBLlItUZaNqJ+7a6GVvTHrsW4bKjIycYzp2LLnYSIHoWNbIvdY91Zau38fOXcH KWi94hGD4aebMckYUodO54+FTlK5KaJ1mke2fEAPjRepyghWxeDD+Kv0MmATkE2iVDqp yus36Ubs6Vmelm5WRlHRg7swomitCn0BwA+B5kL8EI2SJgoNIpOSn+u6VSfwOaj0qkVE a9kA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=M9JbA/4mJJzCg1BoSjOe8spAl/jM5dv9tZGOFooq9Lk=; b=Ti+PfGGjQcS96H50cQsPnqs/74isCkWpcEIf8w7p8l4X3gK+VH8wMo0tLmTNsAlsLU XuAUI1YmHW1lL1Hm42w3I3PYDWUFhaqMyfY6FhyIImVrhmPp3nKDgj0Xv2vtQtYKMDI/ SiGJWzL7wGNwATb9vfvRLqlmtZR8Od0qTZF4MmSYtwPH2oSzv1l0D3xT4g30WhU7al6g dMsiBUxiVEhXaY+R9zx74brpjWeVCr3xtwIgi+CA9r3aHhtV1ogSEIXGIZu4eIDYtSR0 8udmlKrr1N7V9ImofMSo/Kk9gSDDiiPlDN8NpGWe5KcDgFfxiB5pjWF/pTcdhGe5dRc8 OqzQ== X-Gm-Message-State: AOAM533hxHkwHMfntD/8n91siZ/JY5gO4pszHLzpLiA46Ws7HMRx/clm s+CC67/CsPULLc8aX5PNFZEI6TtiZKhcrQ== X-Google-Smtp-Source: ABdhPJy7MaCH11IthoWLLviubSAZWgFmmvf+NeSA3psJdYNqkfnfWfYK7q0WCYspGtPsRAwnoYfohQ== X-Received: by 2002:a05:6a00:21c8:b0:4c4:4bd:dc17 with SMTP id t8-20020a056a0021c800b004c404bddc17mr6117099pfj.57.1651384238220; Sat, 30 Apr 2022 22:50:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 08/45] target/arm: Name CPState type Date: Sat, 30 Apr 2022 22:49:50 -0700 Message-Id: <20220501055028.646596-9-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::434; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org, =?UTF-8?q?Alex=20Benn=C3=A9e?= Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651385770063100001 Give this enum a name and use in ARMCPRegInfo, add_cpreg_to_hashtable and define_one_arm_cp_reg_with_opaque. Reviewed-by: Alex Benn=C3=A9e Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 6 +++--- target/arm/helper.c | 6 ++++-- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 858c5da57d..4179a8cdd5 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -114,11 +114,11 @@ enum { * Note that we rely on the values of these enums as we iterate through * the various states in some places. */ -enum { +typedef enum { ARM_CP_STATE_AA32 =3D 0, ARM_CP_STATE_AA64 =3D 1, ARM_CP_STATE_BOTH =3D 2, -}; +} CPState; =20 /* * ARM CP register secure state flags. These flags identify security state @@ -260,7 +260,7 @@ struct ARMCPRegInfo { uint8_t opc1; uint8_t opc2; /* Execution state in which this register is visible: ARM_CP_STATE_* */ - int state; + CPState state; /* Register type: ARM_CP_* bits/values */ int type; /* Access rights: PL*_[RW] */ diff --git a/target/arm/helper.c b/target/arm/helper.c index a19e04bb0b..d560a6a6a9 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8502,7 +8502,7 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) } =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, int state, int secstate, + void *opaque, CPState state, int secsta= te, int crm, int opc1, int opc2, const char *name) { @@ -8662,13 +8662,15 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of * the register, if any. */ - int crm, opc1, opc2, state; + int crm, opc1, opc2; int crmmin =3D (r->crm =3D=3D CP_ANY) ? 0 : r->crm; int crmmax =3D (r->crm =3D=3D CP_ANY) ? 15 : r->crm; int opc1min =3D (r->opc1 =3D=3D CP_ANY) ? 0 : r->opc1; int opc1max =3D (r->opc1 =3D=3D CP_ANY) ? 7 : r->opc1; int opc2min =3D (r->opc2 =3D=3D CP_ANY) ? 0 : r->opc2; int opc2max =3D (r->opc2 =3D=3D CP_ANY) ? 7 : r->opc2; + CPState state; + /* 64 bit registers have only CRm and Opc1 fields */ assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn))); /* op0 only exists in the AArch64 encodings */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385372357744.9315777157926; Sat, 30 Apr 2022 23:09:32 -0700 (PDT) Received: from localhost ([::1]:36994 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2lv-0006cY-0p for importer@patchew.org; Sun, 01 May 2022 02:09:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43272) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tl-0006sC-PD for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:51 -0400 Received: from mail-pj1-x102e.google.com ([2607:f8b0:4864:20::102e]:39599) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tg-0001GI-Ak for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:41 -0400 Received: by mail-pj1-x102e.google.com with SMTP id a15-20020a17090ad80f00b001dc2e23ad84so1790516pjv.4 for ; Sat, 30 Apr 2022 22:50:39 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=dbDAxfca3xZASncYMUEB6IYFJ1wRcOw6UIc41wY+Pts=; b=sixa/PNE0Pd/Ljrk7clbzAS59HwI667ULaeHCHspi3kLPq+//Pe2IGm8vKgK4vVRVw 2HPuRYiHQqHKLqzTp2b72NOvQp3DDUk/BCDHf8pgcy1c4P8OSi6jowQCdTa4QJYYWr2J 1n6Q4RTnjt6/wviTRsDFenKoQk2bRYxzOB2d1PmqFvvmkUtTvFby4VCuajPCqQ47s8dC +n+AYvaVthw18HmeCNOHbO6sUvTT67BqLCl3kWeuGO49IhKgd1fGIEWbfkgVJc0eYxgM xWYcP1DX/Dza55eXq37FdCRPiE3SeM2jcZp4eoZg+vZgQiNTyoNIbNwsySdWgVKkqXdX 0qCw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=dbDAxfca3xZASncYMUEB6IYFJ1wRcOw6UIc41wY+Pts=; b=rngSp26HN1TpFz858QwE3f0ZPJMxJdHUV6hjhyYo00nAsKTVtAXlJ1PeWDs4QAncy1 LLzYcL/vbU28BCnnctW4knZANniyYIWyHL1TjckjDGimRnFtS/J+zPceNvPWQXjXOzxN a50J5unETx9pG6gkjIKvxiLGgcoqmVWh2T5idEpklSDaQS27HeNF2ZyFgo/icQ4cGsRd pIiVlrFSwaLyzXw6DNcGc/weOY/JD4lLgk9u4/bvVW3pJAvXSCohC1SHeQAT1tmg+DE1 bQGx9g7vEhT0wamhWkBsxGGxqfUrjWD6+KYTHlmXLYV81PM3dIBIcktM1nT2fHEk9T6m o18g== X-Gm-Message-State: AOAM531MUdQnQOrm8G8HEj0cpP0fYl/kZDdRDYXknfYOvmnWL4+g51cd XS0ZRLl9AFRUJ1f1yqLghBUu+SwnIgANzQ== X-Google-Smtp-Source: ABdhPJzaLvwFsHho/TG9qcm7x0UxDP3TkteFPDmc4EqOw7OGAarlf4y8PL9GmTwe4mKqYeqaKgg/Xg== X-Received: by 2002:a17:90b:4b12:b0:1d2:8bda:ef7 with SMTP id lx18-20020a17090b4b1200b001d28bda0ef7mr12089731pjb.174.1651384238982; Sat, 30 Apr 2022 22:50:38 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 09/45] target/arm: Name CPSecureState type Date: Sat, 30 Apr 2022 22:49:51 -0700 Message-Id: <20220501055028.646596-10-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102e; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651385374016100002 Content-Type: text/plain; charset="utf-8" Give this enum a name and use in ARMCPRegInfo and add_cpreg_to_hashtable. Add the enumerator ARM_CP_SECSTATE_BOTH to clarify how 0 is handled in define_one_arm_cp_reg_with_opaque. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpregs.h | 7 ++++--- target/arm/helper.c | 7 +++++-- 2 files changed, 9 insertions(+), 5 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 4179a8cdd5..73984549d2 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -131,10 +131,11 @@ typedef enum { * registered entry will only have one to identify whether the entry is se= cure * or non-secure. */ -enum { +typedef enum { + ARM_CP_SECSTATE_BOTH =3D 0, /* define one cpreg for each secstat= e */ ARM_CP_SECSTATE_S =3D (1 << 0), /* bit[0]: Secure state register */ ARM_CP_SECSTATE_NS =3D (1 << 1), /* bit[1]: Non-secure state register= */ -}; +} CPSecureState; =20 /* * Access rights: @@ -266,7 +267,7 @@ struct ARMCPRegInfo { /* Access rights: PL*_[RW] */ CPAccessRights access; /* Security state: ARM_CP_SECSTATE_* bits/values */ - int secure; + CPSecureState secure; /* * The opaque pointer passed to define_arm_cp_regs_with_opaque() when * this register was defined: can be used to hand data through to the diff --git a/target/arm/helper.c b/target/arm/helper.c index d560a6a6a9..50ad2e3e37 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8502,7 +8502,8 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Erro= r **errp) } =20 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, - void *opaque, CPState state, int secsta= te, + void *opaque, CPState state, + CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { @@ -8785,7 +8786,7 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, r->secure, crm, opc1, o= pc2, r->name); break; - default: + case ARM_CP_SECSTATE_BOTH: name =3D g_strdup_printf("%s_S", r->name); add_cpreg_to_hashtable(cpu, r, opaque, state, ARM_CP_SECSTATE_S, @@ -8795,6 +8796,8 @@ void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu, ARM_CP_SECSTATE_NS, crm, opc1, opc2, r->nam= e); break; + default: + g_assert_not_reached(); } } else { /* AArch64 registers get mapped to non-secure inst= ance --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385372; cv=none; d=zohomail.com; s=zohoarc; b=HRxY3mr2/KzGuHH21uVQSdW1X8sE8hoMRhNe1PSyk7IhoIMnni9G+FF750cHjUOcEoBUqckqf5pFFmywx3MQ1d5f40ITje6sMKMruZmkTPPmZOMc8EIayicikw5xE/7kRTUqyoYlLa5YysKR0290lpGIW/knti1xXQOOTO61W/o= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385372; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=7dAjLdTZkl7TID6iGw+1xQMd9kdTMVThmu014u7vMDQ=; b=Bfg18pJ4Zo0qp2pdXoFkz6/Y2KjldWh8D1iQbUKWxo9WBFYhEXXTssZPGQdl1cnMFTNDHzzMmd8Nen9FS59s1z9kqWcHJ4ozXs2Bq+yzeyjN7+5Ys1hOG402figuTvne+7kij4K7xfO35R9fOsBJowPExlc93YNfASZZFBG5zKg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385372313668.2573315607999; Sat, 30 Apr 2022 23:09:32 -0700 (PDT) Received: from localhost ([::1]:37114 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2lv-0006hc-9H for importer@patchew.org; Sun, 01 May 2022 02:09:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43328) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tn-0006t1-CY for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:52 -0400 Received: from mail-pj1-x1029.google.com ([2607:f8b0:4864:20::1029]:44849) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tk-0001Gd-Cw for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:46 -0400 Received: by mail-pj1-x1029.google.com with SMTP id m14-20020a17090a34ce00b001d5fe250e23so10458799pjf.3 for ; Sat, 30 Apr 2022 22:50:40 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:39 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=7dAjLdTZkl7TID6iGw+1xQMd9kdTMVThmu014u7vMDQ=; b=n75sJf5xK2h9Le32WX0ruVufYI4OSQykxtXdUuSwrd8SppuA7gbZukcNvwjaHf01tJ keE0i9JkY3nABySd09/+eWfMl0vzrmtDjveiSCX7boRJ8+v6VuL1yrKjxY3ylc011grM ShjXaOEFlgRX7flwNlwwCCupZiWakLQwEW51MHejex09fLYnucPKTW3FejlBsScTuJ2u hXKYwB8t4Xe1O6wM5p/zV02xyLzDVdBbldy7+QAlNVjogZ9WNrAxYQvJjR327mhj0Fv9 NdQhkWU8+IcNJBsgNw9DdtT5ELqDxv4zDW4X85lgVv7iecFBn4NERLnqvm2+92XWW6sD XSfA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=7dAjLdTZkl7TID6iGw+1xQMd9kdTMVThmu014u7vMDQ=; b=TWPWhU1AUtXlfNkEW7Z1VH6+IXM+MzukAjQPJ7d8Bp82bgq4vt1zGGW7/CrQ/T0nYL MJU5FSVdhtKSucBLwg8jKPSy2NVaGHqvM0QF6C7JmXxTLEfNmELzVrBN78drIriyv+R5 RTBu1vWlvQExMLCPEiR+dQwgxbC2uzzA/4BMXkjwt4sFY5JSZ/LUsXfGeZHKgibkoLmI mfv+ln+/oC+NTc/sgbtB9Ou96xZV9TPSOtX13kWegAkBRbssGj4ISQLrojccwhINgBx5 Tx19wfZZfOEiVCmJ0Kpd8Exm8fMOzM5sY+i0tU14IRxraKfMhXa8xcClHiLLa6JNbMgq ddfQ== X-Gm-Message-State: AOAM532tK1S90m4XqHMBRdOaLFqQS6foCqBvpgH5amZr4H1twtDBzSnJ JAHrgt9CkEwTrI9QkHKKisXUSgVRKJxsGw== X-Google-Smtp-Source: ABdhPJzCOw9tnF2A35WONfn9Y0yxo7LiNeW1T/s8IDdMHa7L4UnjCtaOpKyN16pPO+WXR4MQdV311g== X-Received: by 2002:a17:90b:3851:b0:1dc:4f70:1cb with SMTP id nl17-20020a17090b385100b001dc4f7001cbmr1366825pjb.167.1651384239772; Sat, 30 Apr 2022 22:50:39 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 10/45] target/arm: Drop always-true test in define_arm_vh_e2h_redirects_aliases Date: Sat, 30 Apr 2022 22:49:52 -0700 Message-Id: <20220501055028.646596-11-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385374008100001 Content-Type: text/plain; charset="utf-8" The new_key field is always non-zero -- drop the if. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4: Drop change to crn et al. --- target/arm/helper.c | 23 +++++++++++------------ 1 file changed, 11 insertions(+), 12 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 50ad2e3e37..e5fc22bb69 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5914,7 +5914,9 @@ static void define_arm_vh_e2h_redirects_aliases(ARMCP= U *cpu) =20 for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; - ARMCPRegInfo *src_reg, *dst_reg; + ARMCPRegInfo *src_reg, *dst_reg, *new_reg; + uint32_t *new_key; + bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; @@ -5933,19 +5935,16 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) g_assert(src_reg->opaque =3D=3D NULL); =20 /* Create alias before redirection so we dup the right data. */ - if (a->new_key) { - ARMCPRegInfo *new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInf= o)); - uint32_t *new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); - bool ok; + new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); + new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 - new_reg->name =3D a->new_name; - new_reg->type |=3D ARM_CP_ALIAS; - /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ - new_reg->access &=3D PL2_RW | PL3_RW; + new_reg->name =3D a->new_name; + new_reg->type |=3D ARM_CP_ALIAS; + /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ + new_reg->access &=3D PL2_RW; =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); - g_assert(ok); - } + ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + g_assert(ok); =20 src_reg->opaque =3D dst_reg; src_reg->orig_readfn =3D src_reg->readfn ?: raw_read; --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385095; cv=none; d=zohomail.com; s=zohoarc; b=SZDZ45wQbUSbcSm9KSO1kjYf43ldGGjz3jQl5utozItBZNzaUUzxWjg56g5ebnsZmmBRn1Xaj7xZOXvqWp/FfS/efw1GbeQuUBNespAl2mRvEWKiUo2VVqZw0lyaTipxYDxMiQxgym0UHH+J6m3KIc6Pjt/5UpIYEjvyZa/Ajoo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385095; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=GMeRjC5hzPb2SDKOi3vpc43SA/xcWIkbPZ4jmzf3DP8=; b=fBx5UrcHUTZead6RJd0+inqYkCzZ8Z/dSuzQBlEOpwLuBGrUxuzSXQ/E11p84ii4vlwkiIMY+3UZX29p7ExglIXGhYNgZnCQ8UYWW0d766wNYMmG3IMuHmn4kq1TCc0l9KWTR9rmD/ICgi5dPPOWOBIGaEVeaQZaSAL/JgqDwIU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385095491874.2748126866223; Sat, 30 Apr 2022 23:04:55 -0700 (PDT) Received: from localhost ([::1]:56876 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2hS-0000vL-Ew for importer@patchew.org; Sun, 01 May 2022 02:04:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43334) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tn-0006t2-FY for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:52 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:35489) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tl-0001H5-H9 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:47 -0400 Received: by mail-pj1-x1036.google.com with SMTP id w5-20020a17090aaf8500b001d74c754128so13803574pjq.0 for ; Sat, 30 Apr 2022 22:50:41 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.39 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:40 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GMeRjC5hzPb2SDKOi3vpc43SA/xcWIkbPZ4jmzf3DP8=; b=TpQd7CmX3CeYn/Tdmv1/iDXvrFz1SE26KymdhHUwfEB0c7XYHiOtkOjL5zq6vx12Fd azDnMV4yWyq5wLEqDxpghITGarghnN3JgtfKAoTXEfR3KEIECiWpKogNQbCqCO6eMkPl MYBOrjgI0qv1PHuWKbzq3fu1oUlx21bqdZx6iPLqi6gXWdbOxND8bvjgJ4UxcE5h1FfW PI2BT/wN6UFWndc8oScOK9DsCzIIvSCaE/w0WY+tw2FXvc8J1Z6DrQveEyFfK7FOLBEI tGY59J+Zq+Pm0mK/vtuhVciNCnfHlhL7mLphYVepZTIHUexZ7k73CN+vzALEOH2Cfos8 HkSA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GMeRjC5hzPb2SDKOi3vpc43SA/xcWIkbPZ4jmzf3DP8=; b=RmSJyKWxbHd72+YJYLmKyb70IrpbihpqbdijQSAM/SJsYONRQ5HNEJ4S1K8oqah/BS rDfDHIH917Fpu0JbnNlVqEU1r5PzCR4ij7+uBXyRm1wZTk2BbxfADqrtofXMcQrvCE9v nogC6oFjqBL5DES2eSl0OczTt0bWQAunbTyZ0TxyCHPfU+kGIEwOL7Eb7XH2/3ucDy3w cE69amAYhzxaiqAXxzP7zHPXHWhN2J8aYLVFTetDyjvJf68Relmqj/D63GN5QjkarsW2 danT9s3IKv5LU63cyYLHMXj0+1UgmTqHx6cbUF7wxElvSI/MwX0mChBEbiepyX4nd9Yk 11qA== X-Gm-Message-State: AOAM530eDlQuWu6zue/TsrebSKjue7PVdb5/Hf1AMO5JFEO9QM4X2PaW oKoaP3c9pCrdl3AgSdTbeJl+BiApqwn7rQ== X-Google-Smtp-Source: ABdhPJzPjEVRymFenagZR6JGOHSs6k9/ze+0V6lBEnNghqxR1K8DIcBttj3nbX/93c3BWkx98TJIsw== X-Received: by 2002:a17:90a:d083:b0:1c9:94bb:732d with SMTP id k3-20020a17090ad08300b001c994bb732dmr7144225pju.106.1651384240653; Sat, 30 Apr 2022 22:50:40 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 11/45] target/arm: Store cpregs key in the hash table directly Date: Sat, 30 Apr 2022 22:49:53 -0700 Message-Id: <20220501055028.646596-12-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385096362100001 Content-Type: text/plain; charset="utf-8" Cast the uint32_t key into a gpointer directly, which allows us to avoid allocating storage for each key. Use g_hash_table_lookup when we already have a gpointer (e.g. for callbacks like count_cpreg), or when using get_arm_cp_reginfo would require casting away const. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v4: Adjust usage of functions to match new note above. --- target/arm/cpu.c | 4 ++-- target/arm/gdbstub.c | 2 +- target/arm/helper.c | 41 ++++++++++++++++++----------------------- 3 files changed, 21 insertions(+), 26 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 268274ce89..e81d96c3c1 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1088,8 +1088,8 @@ static void arm_cpu_initfn(Object *obj) ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); - cpu->cp_regs =3D g_hash_table_new_full(g_int_hash, g_int_equal, - g_free, cpreg_hashtable_data_dest= roy); + cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, + NULL, cpreg_hashtable_data_destro= y); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/gdbstub.c b/target/arm/gdbstub.c index f01a126108..f5b35cd55f 100644 --- a/target/arm/gdbstub.c +++ b/target/arm/gdbstub.c @@ -273,7 +273,7 @@ static void arm_gen_one_xml_sysreg_tag(GString *s, Dyna= micGDBXMLInfo *dyn_xml, static void arm_register_sysreg_for_xml(gpointer key, gpointer value, gpointer p) { - uint32_t ri_key =3D *(uint32_t *)key; + uint32_t ri_key =3D (uintptr_t)key; ARMCPRegInfo *ri =3D value; RegisterSysregXmlParam *param =3D (RegisterSysregXmlParam *)p; GString *s =3D param->s; diff --git a/target/arm/helper.c b/target/arm/helper.c index e5fc22bb69..edfb5c3d38 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -214,11 +214,8 @@ bool write_list_to_cpustate(ARMCPU *cpu) static void add_cpreg_to_list(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; - const ARMCPRegInfo *ri; - - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + uint32_t regidx =3D (uintptr_t)key; + const ARMCPRegInfo *ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_indexes[cpu->cpreg_array_len] =3D cpreg_to_kvm_id(regid= x); @@ -230,11 +227,9 @@ static void add_cpreg_to_list(gpointer key, gpointer o= paque) static void count_cpreg(gpointer key, gpointer opaque) { ARMCPU *cpu =3D opaque; - uint64_t regidx; const ARMCPRegInfo *ri; =20 - regidx =3D *(uint32_t *)key; - ri =3D get_arm_cp_reginfo(cpu->cp_regs, regidx); + ri =3D g_hash_table_lookup(cpu->cp_regs, key); =20 if (!(ri->type & (ARM_CP_NO_RAW|ARM_CP_ALIAS))) { cpu->cpreg_array_len++; @@ -243,8 +238,8 @@ static void count_cpreg(gpointer key, gpointer opaque) =20 static gint cpreg_key_compare(gconstpointer a, gconstpointer b) { - uint64_t aidx =3D cpreg_to_kvm_id(*(uint32_t *)a); - uint64_t bidx =3D cpreg_to_kvm_id(*(uint32_t *)b); + uint64_t aidx =3D cpreg_to_kvm_id((uintptr_t)a); + uint64_t bidx =3D cpreg_to_kvm_id((uintptr_t)b); =20 if (aidx > bidx) { return 1; @@ -5915,15 +5910,16 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) for (i =3D 0; i < ARRAY_SIZE(aliases); i++) { const struct E2HAlias *a =3D &aliases[i]; ARMCPRegInfo *src_reg, *dst_reg, *new_reg; - uint32_t *new_key; bool ok; =20 if (a->feature && !a->feature(&cpu->isar)) { continue; } =20 - src_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->src_key); - dst_reg =3D g_hash_table_lookup(cpu->cp_regs, &a->dst_key); + src_reg =3D g_hash_table_lookup(cpu->cp_regs, + (gpointer)(uintptr_t)a->src_key); + dst_reg =3D g_hash_table_lookup(cpu->cp_regs, + (gpointer)(uintptr_t)a->dst_key); g_assert(src_reg !=3D NULL); g_assert(dst_reg !=3D NULL); =20 @@ -5936,14 +5932,14 @@ static void define_arm_vh_e2h_redirects_aliases(ARM= CPU *cpu) =20 /* Create alias before redirection so we dup the right data. */ new_reg =3D g_memdup(src_reg, sizeof(ARMCPRegInfo)); - new_key =3D g_memdup(&a->new_key, sizeof(uint32_t)); =20 new_reg->name =3D a->new_name; new_reg->type |=3D ARM_CP_ALIAS; /* Remove PL1/PL0 access, leaving PL2/PL3 R/W in place. */ new_reg->access &=3D PL2_RW; =20 - ok =3D g_hash_table_insert(cpu->cp_regs, new_key, new_reg); + ok =3D g_hash_table_insert(cpu->cp_regs, + (gpointer)(uintptr_t)a->new_key, new_reg); g_assert(ok); =20 src_reg->opaque =3D dst_reg; @@ -8509,7 +8505,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, /* Private utility function for define_one_arm_cp_reg_with_opaque(): * add a single reginfo struct to the hash table. */ - uint32_t *key =3D g_new(uint32_t, 1); + uint32_t key; ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; @@ -8576,10 +8572,10 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { r2->cp =3D CP_REG_ARM64_SYSREG_CP; } - *key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); + key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, + r2->opc0, opc1, opc2); } else { - *key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); + key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); } if (opaque) { r2->opaque =3D opaque; @@ -8621,8 +8617,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * requested. */ if (!(r->type & ARM_CP_OVERRIDE)) { - ARMCPRegInfo *oldreg; - oldreg =3D g_hash_table_lookup(cpu->cp_regs, key); + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { fprintf(stderr, "Register redefined: cp=3D%d %d bit " "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " @@ -8632,7 +8627,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, g_assert_not_reached(); } } - g_hash_table_insert(cpu->cp_regs, key, r2); + g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 =20 @@ -8864,7 +8859,7 @@ void modify_arm_cp_regs_with_len(ARMCPRegInfo *regs, = size_t regs_len, =20 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encode= d_cp) { - return g_hash_table_lookup(cpregs, &encoded_cp); + return g_hash_table_lookup(cpregs, (gpointer)(uintptr_t)encoded_cp); } =20 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri, --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385826; cv=none; d=zohomail.com; s=zohoarc; b=kePdWUy7MKFhDe2EaBvHzbYTywZ+HNjXZ97rOdL6jiT1BUDKErnDtSo+PHvhGJAWNO9+k3wlLoai/05ig6Hj3BnC5c5PTBXeclgLSjZ70NdKDuqUa1hrT7YGZqf1fjvTL7sO1TELDqG8teqau99jB/JgvwSeXvL6ww4Tz9hoPyE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385826; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=qhhRxFmH56xTpD71QaIiTZcsW/xl8vNYPr7Quyst7dg=; b=MvJerpMz1n9TCjbhxsp9p08TEmizedeWD8NXRroIMG+y9hFGH3uxEYB4V3em79xWaJvw8n5l8BG+mpeo4s4gQk4tr/TH2PIVxJwDDHuoBDrub7H4zpL+dPvaQ5p4e/+WZNS7NhaFjqHTk6wTUTqSSawl5+PUfDF3Qe4aN/dmAMg= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385826943194.5869001738214; Sat, 30 Apr 2022 23:17:06 -0700 (PDT) Received: from localhost ([::1]:47774 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2tF-0005g6-MM for importer@patchew.org; Sun, 01 May 2022 02:17:05 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43456) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tp-0006tD-NH for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:57 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:34439) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tl-0001HG-Jm for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:49 -0400 Received: by mail-pj1-x1033.google.com with SMTP id qe3-20020a17090b4f8300b001dc24e4da73so1999133pjb.1 for ; Sat, 30 Apr 2022 22:50:42 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:41 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qhhRxFmH56xTpD71QaIiTZcsW/xl8vNYPr7Quyst7dg=; b=IoidiJAVjpYHJYpaNmM5dyMHt5gkkPKXVdHzo69NCflhxgswKv3i67XXX/DmQY/gE3 5MhCKKxUDnhCzctCkPmRIoBvXIpccfTNme5A3NrkGtMQBBExe7y4APc/v4ydL9j6Mdj7 f7R8GSp3f0aksfxHILCIQ6dMhC5sRR4Ug98PfTzlH1Aj9dwUWHsSPLS1ywzb4EG2QAwq UOp/DqZhOjUWEzRZA9MRk28JEI48o2sH8TKVT/yW9Z5VuvyYq65VZG0l8/yUasK5SbUk ENnrLkzcVp4fZDgHp4SZUUKVZlIJQrahipnsqc6Vy1M5gnSDoItjIJpTMQyBsXsmj/qw tJ9A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qhhRxFmH56xTpD71QaIiTZcsW/xl8vNYPr7Quyst7dg=; b=UolBCxiMjYQ31yuSWErdybpxmarGalSw7HtaRarAz029fRx6xNKFxeNsY6LuKfGQM7 eT8dsUG4JpOUlLkeeG+2Lea2cjM5qb1mg4J8qQgrNkPtRq1MT6kgEH/IhmGggJosJR3d vA6v7sk7Rq/39+SDa+u+rXnTfRsVVOunWZkz3RoEQcNh38AtQNpHysUiU81/ajsTBter vATxeNmsQokqUosPSA5y8JQ7wUcN3TIUKCpca0N1010t1SRDCSsvCjKzYmm5//Reye9x 5QYW6GelLLslgAK2lCM1ceMvLbGixEVEwOduAH3faS+zK43gNBZRts+GTtZIdGK+j1f2 kNoQ== X-Gm-Message-State: AOAM530dQBY9W5SrQLnVMZ96HqgbvhCERRZvhTZpGzgYHOjLeryLKTio d3iz8CzBKgFClfeFGqATgYYVzk4EfeJLKA== X-Google-Smtp-Source: ABdhPJwlTc4jdXYI65zxfDAc3dMFRmq8uChaXImOxlVPEs6X52tBsqjGhqezdXbHitZrRK1Gfqni6Q== X-Received: by 2002:a17:90b:3510:b0:1dc:bac:64f3 with SMTP id ls16-20020a17090b351000b001dc0bac64f3mr10422532pjb.137.1651384241444; Sat, 30 Apr 2022 22:50:41 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 12/45] target/arm: Merge allocation of the cpreg and its name Date: Sat, 30 Apr 2022 22:49:54 -0700 Message-Id: <20220501055028.646596-13-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385828153100001 Content-Type: text/plain; charset="utf-8" Simplify freeing cp_regs hash table entries by using a single allocation for the entire value. This fixes a theoretical bug if we were to ever free the entire hash table, because we've been installing string literal constants into the cpreg structure in define_arm_vh_e2h_redirects_aliases. However, at present we only free entries created for AArch32 wildcard cpregs which get overwritten by more specific cpregs, so this bug is never exposed. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/cpu.c | 16 +--------------- target/arm/helper.c | 10 ++++++++-- 2 files changed, 9 insertions(+), 17 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e81d96c3c1..6e8b39dc9e 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1069,27 +1069,13 @@ uint64_t arm_cpu_mp_affinity(int idx, uint8_t clust= ersz) return (Aff1 << ARM_AFF1_SHIFT) | Aff0; } =20 -static void cpreg_hashtable_data_destroy(gpointer data) -{ - /* - * Destroy function for cpu->cp_regs hashtable data entries. - * We must free the name string because it was g_strdup()ed in - * add_cpreg_to_hashtable(). It's OK to cast away the 'const' - * from r->name because we know we definitely allocated it. - */ - ARMCPRegInfo *r =3D data; - - g_free((void *)r->name); - g_free(r); -} - static void arm_cpu_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); =20 cpu_set_cpustate_pointers(cpu); cpu->cp_regs =3D g_hash_table_new_full(g_direct_hash, g_direct_equal, - NULL, cpreg_hashtable_data_destro= y); + NULL, g_free); =20 QLIST_INIT(&cpu->pre_el_change_hooks); QLIST_INIT(&cpu->el_change_hooks); diff --git a/target/arm/helper.c b/target/arm/helper.c index edfb5c3d38..44c05deb5b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8506,11 +8506,17 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, * add a single reginfo struct to the hash table. */ uint32_t key; - ARMCPRegInfo *r2 =3D g_memdup(r, sizeof(ARMCPRegInfo)); + ARMCPRegInfo *r2; int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + size_t name_len; + + /* Combine cpreg and name into one allocation. */ + name_len =3D strlen(name) + 1; + r2 =3D g_malloc(sizeof(*r2) + name_len); + *r2 =3D *r; + r2->name =3D memcpy(r2 + 1, name, name_len); =20 - r2->name =3D g_strdup(name); /* Reset the secure state to the specific incoming state. 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:42 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=quTC6tTsjrVSG7RTQMFQxNix8MmA7vsc1c94ro1M6BU=; b=GAaMlrPsCUAKgd4ifuF74NLDzajJdiMSssMgoXVuxe/PhIqvNkznvXLkzcgSb4zIfS TeJbN30lQ2SEyg1HbpDIcTskbRUl0WXEA053PCs9ROdHLNm6btDswIXIThYYYSgdNAta qx3IgFdVR2lOd5wu6keMsZCiAhdIBpVfvl6e681283mImO7Dvo4PaANbaxpC/WnE57RI HXx9+66u6ZdDq8iJD2Ghfnjtmv1g4iykmK9vlIITE53NwY/ni5cGT6zLlYws9ve58UjC nxdgdeC4eX+qIDfZ8NO5bcHtK4UTwKaRVEtmHYwWRr8AzVvdECTVXIkx/F8/QS/cZehb s78w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=quTC6tTsjrVSG7RTQMFQxNix8MmA7vsc1c94ro1M6BU=; b=gQex4dQkqPzaXJEqdHQAMeMG6e1RKd2/ZftsRC/Irx/eeflg1+w/Kzb2pG1TgXVNaA DqNNFRmt1vpI2HjtxJpvEQwP47QA2RNb3fiJr5sam0ETV0KcCuz8rYycDLuq6eQcr8ZK HBSjiCU2jjIi+leEwyzlTLCvyFyJneFTC2ikyjMEKy8vpHNGg8KHJoC+fLd+74bJgoB5 mRg+gwaMG3mGMrb+guOJF2T4xIJxkWBxM+80zyUZF72B4c2XKHl1eygJ1xP36ruGVe7H 4nnLur0R4v8bdG/s2TSwqWbXKndYQqwr+DJrbv0LIlD9VUChv2YZ2t4MA3BwPhJG054a FGGQ== X-Gm-Message-State: AOAM530IeKeYFM0765N+nwNK3MeYzF62AyI9LJTjSqz7/lykGiOZtqvd 9ODA92I7zZ/gCrlrfgcpDUdF3Db4Fzosyg== X-Google-Smtp-Source: ABdhPJzrdAK/vBu3YruimULYIbmC3Ijz1FRo0BQs6l7dMMIHiHbdf1O9V+tKg0f2aMe7tMc1b4izbQ== X-Received: by 2002:a17:90a:fac:b0:1ca:5eb8:f3b2 with SMTP id 41-20020a17090a0fac00b001ca5eb8f3b2mr7145887pjz.37.1651384242469; Sat, 30 Apr 2022 22:50:42 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 13/45] target/arm: Hoist computation of key in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:49:55 -0700 Message-Id: <20220501055028.646596-14-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102a; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651386121804100001 Content-Type: text/plain; charset="utf-8" Move the computation of key to the top of the function. Hoist the resolution of cp as well, as an input to the computation of key. This will be required by a subsequent patch. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 49 +++++++++++++++++++++++++-------------------- 1 file changed, 27 insertions(+), 22 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 44c05deb5b..118422d672 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8509,8 +8509,34 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, ARMCPRegInfo *r2; int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + int cp =3D r->cp; size_t name_len; =20 + switch (state) { + case ARM_CP_STATE_AA32: + /* We assume it is a cp15 register if the .cp field is left unset.= */ + if (cp =3D=3D 0 && r->state =3D=3D ARM_CP_STATE_BOTH) { + cp =3D 15; + } + key =3D ENCODE_CP_REG(cp, is64, ns, r->crn, crm, opc1, opc2); + break; + case ARM_CP_STATE_AA64: + /* + * To allow abbreviation of ARMCPRegInfo definitions, we treat + * cp =3D=3D 0 as equivalent to the value for "standard guest-visi= ble + * sysreg". STATE_BOTH definitions are also always "standard sysr= eg" + * in their AArch64 view (the .cp value may be non-zero for the + * benefit of the AArch32 view). + */ + if (cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { + cp =3D CP_REG_ARM64_SYSREG_CP; + } + key =3D ENCODE_AA64_CP_REG(cp, r->crn, crm, r->opc0, opc1, opc2); + break; + default: + g_assert_not_reached(); + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8554,12 +8580,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } =20 if (r->state =3D=3D ARM_CP_STATE_BOTH) { - /* We assume it is a cp15 register if the .cp field is left un= set. - */ - if (r2->cp =3D=3D 0) { - r2->cp =3D 15; - } - #if HOST_BIG_ENDIAN if (r2->fieldoffset) { r2->fieldoffset +=3D sizeof(uint32_t); @@ -8567,22 +8587,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, #endif } } - if (state =3D=3D ARM_CP_STATE_AA64) { - /* To allow abbreviation of ARMCPRegInfo - * definitions, we treat cp =3D=3D 0 as equivalent to - * the value for "standard guest-visible sysreg". - * STATE_BOTH definitions are also always "standard - * sysreg" in their AArch64 view (the .cp value may - * be non-zero for the benefit of the AArch32 view). - */ - if (r->cp =3D=3D 0 || r->state =3D=3D ARM_CP_STATE_BOTH) { - r2->cp =3D CP_REG_ARM64_SYSREG_CP; - } - key =3D ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm, - r2->opc0, opc1, opc2); - } else { - key =3D ENCODE_CP_REG(r2->cp, is64, ns, r2->crn, crm, opc1, opc2); - } if (opaque) { r2->opaque =3D opaque; } @@ -8593,6 +8597,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, /* Make sure reginfo passed to helpers for wildcarded regs * has the correct crm/opc1/opc2 for this reg, not CP_ANY: */ + r2->cp =3D cp; r2->crm =3D crm; r2->opc1 =3D opc1; r2->opc2 =3D opc2; --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651386360; cv=none; d=zohomail.com; s=zohoarc; b=IMXWmmG4qP4UmKloLR0sZzSi/gkfeGMFHBCnTp9iJl11zHXuS88hnjAgi/ttCBWLAoZyxoIYDznWJtsnG8bAGZFiHNljYwyVGcyuq/LM8t+O0tiuKWbkXBPgmoqU50fRciKo0zIDDjv12UDSVFZ4Cfc9zXuoqnUaTOLHhojGji8= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651386360; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=q2ExgRJeW51vJ/LQ9D7kCX+GyJ0sPJY/PZJuyp2uAOM=; b=mnldXRHiRHHrR7pGG403CqYOxCRrFIE/B4+PtFtjnPesVDdn5Z2JGtUa4JZoF32bo3h+6pH6q0A1T9DTKPRyZ2yIazsSkIc8jsFQCIyhvyqy417MTJhPFcTeNSJjtDbAjEYdntbZBHeGzAFpFJmBCwH6r0MRb0vyTE+ajZA/A4M= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651386360945121.2720406698595; Sat, 30 Apr 2022 23:26:00 -0700 (PDT) Received: from localhost ([::1]:33334 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl31r-0006Zj-7k for importer@patchew.org; Sun, 01 May 2022 02:25:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43382) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2To-0006t4-9J for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:57 -0400 Received: from mail-pj1-x1031.google.com ([2607:f8b0:4864:20::1031]:56114) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tl-0001HX-Hd for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:48 -0400 Received: by mail-pj1-x1031.google.com with SMTP id r9so10320663pjo.5 for ; Sat, 30 Apr 2022 22:50:44 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=q2ExgRJeW51vJ/LQ9D7kCX+GyJ0sPJY/PZJuyp2uAOM=; b=cF7Ik4j1QClewU0d3USpi9rFwhvj7mid+0aJBmWrnyQS5cqrLqb/rjWgWFmlulc+OD PwQao7NCZYcf0JNFT1YXuwKKPpBhGha/2AaSyGHEKaeDovGBeHPBf+xGeRlbZrs45OnG MSP86MiQFKp8P3iB2bLfuzdtwUDCMkhHB0aNLqyA3IFkVGTrMi8/XXk8rc884GTHfELq bDB9JaH7DoCDlHcNfgS+EPturReN3FwN5pEBVBdD/HNVTNkOq5Eo5MK+gjx8zyzfqgLO fjoX20WNw36TdvJx/nFd8tQYSmmXJYv6ACNNN+NaJ/DcODhzK+8LXDFrfvrX9Jl/vMlk GobA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=q2ExgRJeW51vJ/LQ9D7kCX+GyJ0sPJY/PZJuyp2uAOM=; b=aAVv59ivsjjxX0cON0mr1qyNYgHZnkmIBWYbecH/w9JH0mPnCKPekNq7EXjimBMxJZ ANNHaLsjbNf/wkcgnwhCuHDctCfLyJIyvdxjTxMPimUInv/PuClWgFFxlGmpu+zPE9uV Er19RfhiEBfXhnouAYbmx+ffv+lrCsEVwnehEr0OiOVP88lsC54B84paOsbssnHzwtA5 /6RkWUPwXaN3StaMOmpGyFT22rWEfQzbeLr9aq9CmjegWeCoKuL0hy0QVgOzy834l2HB /D3Mb1F+sspKE2lG3rij8qQtwO81jkmaSn0t6U2xh85vnnpysT3tiTX0dZfY1JX00odN 2cvg== X-Gm-Message-State: AOAM530DyThhyiTsD5erwG6kZyWuBPjmoo7UABwMfPj05KXdEl23rtEz IC/qDvsko4N8Z8eD1SgFh2N4Aco2HlI3NQ== X-Google-Smtp-Source: ABdhPJx8CHRTUYeTdEs3NT/R3KC/cqJWDB3mIv4nCmY6pz9lQ9uwy5/7a4wcsKWCcFuagn8gKSA2XA== X-Received: by 2002:a17:90a:784b:b0:1db:dfe6:5d54 with SMTP id y11-20020a17090a784b00b001dbdfe65d54mr6973732pjl.112.1651384243486; Sat, 30 Apr 2022 22:50:43 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 14/45] target/arm: Consolidate cpreg updates in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:49:56 -0700 Message-Id: <20220501055028.646596-15-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1031; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1031.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651386362975100001 Content-Type: text/plain; charset="utf-8" Put most of the value writeback to the same place, and improve the comment that goes with them. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 28 ++++++++++++---------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 118422d672..b2887d63b6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8543,10 +8543,19 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, *r2 =3D *r; r2->name =3D memcpy(r2 + 1, name, name_len); =20 - /* Reset the secure state to the specific incoming state. This is - * necessary as the register may have been defined with both states. + /* + * Update fields to match the instantiation, overwiting wildcards + * such as CP_ANY, ARM_CP_STATE_BOTH, or ARM_CP_SECSTATE_BOTH. */ + r2->cp =3D cp; + r2->crm =3D crm; + r2->opc1 =3D opc1; + r2->opc2 =3D opc2; + r2->state =3D state; r2->secure =3D secstate; + if (opaque) { + r2->opaque =3D opaque; + } =20 if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { /* Register is banked (using both entries in array). @@ -8587,20 +8596,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, #endif } } - if (opaque) { - r2->opaque =3D opaque; - } - /* reginfo passed to helpers is correct for the actual access, - * and is never ARM_CP_STATE_BOTH: - */ - r2->state =3D state; - /* Make sure reginfo passed to helpers for wildcarded regs - * has the correct crm/opc1/opc2 for this reg, not CP_ANY: - */ - r2->cp =3D cp; - r2->crm =3D crm; - r2->opc1 =3D opc1; - r2->opc2 =3D opc2; + /* By convention, for wildcarded registers only the first * entry is used for migration; the others are marked as * ALIAS so we don't try to transfer the register --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385429; cv=none; d=zohomail.com; s=zohoarc; b=ZAOJ2auPlc6AxJw7Aa4iDOVBnobRwz2ZNG09/zx9IgN1mPq/hXuE2YU5OmfaOhbURPOlbXFAqi+jM/hOyx8NIkWHZ0/n4dH4VDKKYOPqJQTGOC7SfG1Z++aPJz0LvzmJxddOo76PDbAjPP39kNH1DyxSKQrm7XYXNlSwpf33UCQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385429; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=rRPI4KJ0o1Fv91uZt/otSHqIpd9AAG960yShsiZDMcA=; b=TqTZhvPiFEINnSe6hcJwf61m1Lpq6NpTMxr+ywVKoTgTHXh/bskdK5D1XLsfpyvOmu3U6W78b5PQ2heRhXi1e3OcMaOBUDEXA6bnjx8lBLw3HbUJlC4piYScBKqh4VGB0sIgIWc3GzkIY6XNoHZ15cjtK5OrUdrj8COkn4Kwc+0= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385429689951.266195448499; Sat, 30 Apr 2022 23:10:29 -0700 (PDT) Received: from localhost ([::1]:39004 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2mq-0007xO-Hd for importer@patchew.org; Sun, 01 May 2022 02:10:28 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43464) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tp-0006tH-Sj for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:57 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:39603) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tl-0001Hg-OS for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:49 -0400 Received: by mail-pj1-x1032.google.com with SMTP id a15-20020a17090ad80f00b001dc2e23ad84so1790622pjv.4 for ; Sat, 30 Apr 2022 22:50:45 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.43 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:43 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=rRPI4KJ0o1Fv91uZt/otSHqIpd9AAG960yShsiZDMcA=; b=VXBv9P939g9C4OEJMGRrmFAvYvASQ0wUfXQmljDA8+v9MR2+Osk5nvI9/Bsq1EM5el HuzYM/zgFgGga4j7uzIPwP+6IexjMAp6AnK/HI0lzcf97lzjbItZ3DrQ0dKvWdS8N1n8 epEwp6m+zJdGNk9BwcYtweVGp5IY8F0UtL/ydiAbh6oCI/I7DoQBxPSw4ebkJRy1n4jB b3XVoXoXfh1rmj7zoSMlL2W7e/aUqdNWmQgPQK8PDFwlw0qRmMxmlJN3oIU7bvTMeBCX cFuqojq2jBC9OzYD0U5qcOTouhWfcxSMn1c+lXiSL2IyjfuaVJLxKjmGZ/115ykDQSpA hKaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=rRPI4KJ0o1Fv91uZt/otSHqIpd9AAG960yShsiZDMcA=; b=tk9hBbxzEM+MU4byXfm95uAd6BDVQePS+zdVuTZC+kI5HtG0CAWFzwUKWL1EB/cz7/ DGOOzajX6y8JPauIfh92VXXZclaf+xaKWLQHSnzuy4nNz5La1nsuon9cTsnuQa60qexA ttqkWNYTUiQFutMXmI5/Euz27DumqqeqYWpJ4ddP1ep7kA6iHNVdTOMbU4jGLvp/UIqW KdT8EcUtFvJSO6K4aYwbWgS1GeV4jbOPY2NXpfXtCPl3amQ3tPg9h131dsTu50WQT8+p Y4GyLU+UNPYh+EQGddmvkCx37rhlmBcst1hPaJM3vLODE1gnDNRm/jds2Dh10ZTWEEBa 3HhA== X-Gm-Message-State: AOAM5306tvbwl65GGAnzS7T9QdVyYGyfb61VN7gno/FpCLIUiS+Zc/5P o5r6bYmKaxvU7Y/NUJCRxvdccPOyW9QTiA== X-Google-Smtp-Source: ABdhPJwTHwnWh2y7cR5nMRIuaAS8l2tOvtVaJruJg5bgOtNW9tm8vS+ROsRCZOErjG7RWctfqkXwjw== X-Received: by 2002:a17:90a:94c2:b0:1d9:3fbd:bbe1 with SMTP id j2-20020a17090a94c200b001d93fbdbbe1mr7066350pjw.59.1651384244416; Sat, 30 Apr 2022 22:50:44 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 15/45] target/arm: Use bool for is64 and ns in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:49:57 -0700 Message-Id: <20220501055028.646596-16-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385430056100001 Content-Type: text/plain; charset="utf-8" Bool is a more appropriate type for these variables. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b2887d63b6..c6d407f93b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8507,8 +8507,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, */ uint32_t key; ARMCPRegInfo *r2; - int is64 =3D (r->type & ARM_CP_64BIT) ? 1 : 0; - int ns =3D (secstate & ARM_CP_SECSTATE_NS) ? 1 : 0; + bool is64 =3D r->type & ARM_CP_64BIT; + bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; size_t name_len; =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651386200; cv=none; d=zohomail.com; s=zohoarc; b=ZjxFNeSr7z2F8Yqs9XXw+lGk5vXUUEZAdRnPc+7hqQjs8cWZl/deDCYsfCaikFtJu7Y47RC32LaS9sSExk+s+kROEsaIZOkdJPtyIninKMNPHihuRmxyDaaAI3QspLFHv91zp7bFk9uEITcamsZSbUqs8nU6hDxArdA+WoXSSG4= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651386200; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=D07lm6rtFq06JeLlfPndO5hnYOCiVf7FRykTHAAXauo=; b=G1NUFOYs2+5Xx3983Ekk1nWc0GCczSFk82+O43CFvbafJkOnTNUrCY54orL8uEcCam6YogJ8bw3cYNBClmlo7Qaj1D07eUUtYzxXMnuQCKgR1ArMXk/pOrHFomGI2Ffkp7tHX28PxEWEOTU+B3F0g22WXvHaJaC8E21zjW5e+3Q= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651386200578685.5647230747976; Sat, 30 Apr 2022 23:23:20 -0700 (PDT) Received: from localhost ([::1]:57550 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2zH-0003pJ-I5 for importer@patchew.org; Sun, 01 May 2022 02:23:19 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tq-0006tI-0E for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:57 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:56116) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tm-0001Hz-EI for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:49 -0400 Received: by mail-pj1-x1033.google.com with SMTP id r9so10320680pjo.5 for ; Sat, 30 Apr 2022 22:50:46 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:44 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=D07lm6rtFq06JeLlfPndO5hnYOCiVf7FRykTHAAXauo=; b=EkLz5NHtSDHVvYrw2QQUPY3DgAvLq5Rgq44v3ZLNslDl9/HLL9zx5Z0dDPym9mOupM XnSkb1vDKfM6jgX0ttmyJvh5PbTAAK4a+BfFMqGyg77KDKb9zlZsbQ1ecS6LspKR6Af/ 0K8IiVFazW8MZ/678Qu2JPjTzti+YoIRn8g71qRU6uqlCUvjlJFZQgscWn7XV4u+mSZO 3Fvma2OmX1zpRZ+jVRTfpjGZnX8nNvHPO7KaJhFhNaAY48CQKa3KK+GGGw+y7ZO8sr7j Kq6r9MvNbJI8ZasMX59f2IQG/26wd8ICzC50tcZNsQmrSRrh56V8aq+72lTJEsFdg6Mh S9gA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=D07lm6rtFq06JeLlfPndO5hnYOCiVf7FRykTHAAXauo=; b=Lv3J9fP19bEh8jbByFI+EU+LDLzhcjwGJUkWUmC7eJfVQ3VFDoKQ1g+nUwqRBYjOQt 0FFZpN39sAvDyvHcF96ukWZL/OE/wsuefn+ytMbIFIoHThHaa4wJpED3jBUrZYiVpAxy jH7/q20qeN3YKoDg8iK9HxMa99JxAk/aEN0RD/DPonUZ5jFBhWVzTVWjRmyu2W9kApkf V0++sKcuyBAVAJ9ETiJIbOkGoLb8me6yk0EzioSVvWDJGsFWqnh8tClf8lqgAUdn0S2+ Qt4SptBmyOKzlULJdM0GBKN1TRbUBmotd0w7lCbie2u0aKcAeEtOYE/uLYtRetHfkKR1 Hjrw== X-Gm-Message-State: AOAM532JEOBwfF/RsnseBvLHoAEOQSluosPAEwKJkrU8FiVywnl15Y69 WP/3O91y5MDEwFW/AnCMV7DadGlP6UNREA== X-Google-Smtp-Source: ABdhPJw9zsXMLiRskoLBpJ+WwvfEph7mdF4Lix7zUOXIHOiDieVXxdMVVDRjIlimskTx/aQvAWGnHQ== X-Received: by 2002:a17:902:854c:b0:158:35ce:9739 with SMTP id d12-20020a170902854c00b0015835ce9739mr6157164plo.150.1651384245251; Sat, 30 Apr 2022 22:50:45 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 16/45] target/arm: Hoist isbanked computation in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:49:58 -0700 Message-Id: <20220501055028.646596-17-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651386202208100001 Content-Type: text/plain; charset="utf-8" Computing isbanked only once makes the code a bit easier to read. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index c6d407f93b..f1fbbdb9e0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8510,6 +8510,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; + bool isbanked; size_t name_len; =20 switch (state) { @@ -8557,7 +8558,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->opaque =3D opaque; } =20 - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; + if (isbanked) { /* Register is banked (using both entries in array). * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. @@ -8566,7 +8568,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } =20 if (state =3D=3D ARM_CP_STATE_AA32) { - if (r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]) { + if (isbanked) { /* If the register is banked then we don't need to migrate or * reset the 32-bit instance in certain cases: * --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651387479; cv=none; d=zohomail.com; s=zohoarc; b=GkSnZGylvnbeh13H2OX626ywvza/FRwB39ol1SwWHcoVXdWPpn4x4GPJEQBnVmvp6LiOj9SBHEc+SA3Xkof0CNTxJKegrJaAEWbUpjRmZf0UDRWhEH1mNn/OMv5npz5/YeiEJ8H3c6NdgB9z/fOhCcccyVz5ctY+gDL1NA/WzJQ= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651387479; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=CHRhI+bX86VA6q/w81eljR54J64KB5RR2ukIj4TlNII=; b=cOZwnG6WL+bPAlKf7iyHEM0qDH7/b0Z+6GZporzPC9U9NzBA4Zdy2L1LaPJkQsLZ9QjODRc6uJPCwOcyjSnWPVgiN3povI7M18pofq8sNQqHnqbWrVszyexNa/r+7aMypUK2FSWI1eSuGWsf52FaaKAM84X9xMexh4RYqhJhGJ4= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387479184594.9611168352351; Sat, 30 Apr 2022 23:44:39 -0700 (PDT) Received: from localhost ([::1]:52388 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3Jt-0003Mt-RX for importer@patchew.org; Sun, 01 May 2022 02:44:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43542) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tr-0006tK-9i for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:58 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:35800) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tn-0001IH-AK for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:50 -0400 Received: by mail-pl1-x631.google.com with SMTP id d15so10293993plh.2 for ; Sat, 30 Apr 2022 22:50:46 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:45 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=CHRhI+bX86VA6q/w81eljR54J64KB5RR2ukIj4TlNII=; b=E3Q64BpJDClA1H8nu5PtO0JbHilCY7GI4jNJie9eQs+c/PrJJHeBS4i2I9r8jnA23p KCTDp6gtpQUMFgmiDKpw4ktXBSERU4Pj2uBQj1jIRAufEygmbP9PGLbFhxaFBKf1AWLa sIL5Y0/wv/05ZG4EihItT71vVJd7uRfojwaIgg+avLjYmGzmksioD9vY6nthGRdiBw68 0y5X5mz1x4LnsWi8aA7SjxGJ4XS+ZZn7S3BArF2Z2Ut7Oy1RPk/VFVm5yE0Er/TBuE+z J96zR94OqoJX5Z6g22GMXO7qHTjnty14/r3qia857tOjU/W6IVvt1H4x7mZAVlXevXl/ 0CMw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=CHRhI+bX86VA6q/w81eljR54J64KB5RR2ukIj4TlNII=; b=jzoe0k6QQRtsI4+I54R5+XmjW9KVOnUwV84zweTpXTx8ysjLLcvu7YysEvXpStoIdq MtqJmMgD5O7eohmGQzfD7cgmW+umoFEo2NkUhnDo7QJog7awIhDgEhREXwlWATCGWNTJ 59PwJKduCw2rxwO2w4qBnmOdsQl8Xbs+9BKjh98dq7NdQhLPIpgc8go+2oqHuEO3kn/8 1E/uDNUhdNHCW4vJWENFPfi1sBtQuCe+9Xioxgm+KAnmp5Y5GSukw7p/CVXCiB8gf5Gn MnoEMYtD1dE28zf8vUFX0jUFCeclxkiMlAlTWp+0dvNkxyYevTpS+fYs2/zPC4QuLoA0 062Q== X-Gm-Message-State: AOAM531QNF4WR7W+JdQBvwEK//+5Jka+JJq2qAog70zwglXuwiA0z9rm H93DujgrW+c2V5uvhYcu0ds2YpNJg00WZQ== X-Google-Smtp-Source: ABdhPJzMka2M7D61gijqgR+1HgYpN1l3ftsL0RkEPpc0q91s6J9SvnDpsg4OAJ/TyUCnWI4M0mWwIQ== X-Received: by 2002:a17:90a:6501:b0:1ca:a7df:695c with SMTP id i1-20020a17090a650100b001caa7df695cmr7183277pjj.152.1651384246027; Sat, 30 Apr 2022 22:50:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 17/45] target/arm: Perform override check early in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:49:59 -0700 Message-Id: <20220501055028.646596-18-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651387480804100002 Content-Type: text/plain; charset="utf-8" Perform the override check early, so that it is still done even when we decide to discard an unreachable cpreg. Use assert not printf+abort. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 22 ++++++++-------------- 1 file changed, 8 insertions(+), 14 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index f1fbbdb9e0..2ed07795d8 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8538,6 +8538,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, g_assert_not_reached(); } =20 + /* Overriding of an existing definition must be explicitly requested. = */ + if (!(r->type & ARM_CP_OVERRIDE)) { + const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); + if (oldreg) { + assert(oldreg->type & ARM_CP_OVERRIDE); + } + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8622,20 +8630,6 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, assert(!raw_accessors_invalid(r2)); } =20 - /* Overriding of an existing definition must be explicitly - * requested. - */ - if (!(r->type & ARM_CP_OVERRIDE)) { - const ARMCPRegInfo *oldreg =3D get_arm_cp_reginfo(cpu->cp_regs, ke= y); - if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) { - fprintf(stderr, "Register redefined: cp=3D%d %d bit " - "crn=3D%d crm=3D%d opc1=3D%d opc2=3D%d, " - "was %s, now %s\n", r2->cp, 32 + 32 * is64, - r2->crn, r2->crm, r2->opc1, r2->opc2, - oldreg->name, r2->name); - g_assert_not_reached(); - } - } g_hash_table_insert(cpu->cp_regs, (gpointer)(uintptr_t)key, r2); } =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385769; cv=none; d=zohomail.com; s=zohoarc; b=QJn8dUD0V3kNuQTK1lnIRu9/PWD3ubyYicb/vaOezX9o65hk50dvuRtNCBTBjNejDPMTRqedtkiuwkxGxaSeB7N7Yz6I8yZRgz4pWfu98xOlAVHR7hhe8YM4Vud/uNSy6NRdhriZCP/rXVrHFxyWrui3WAP0l0x4ku5Jbz2KWkc= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385769; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=pOb3rzseCiR8Xy7i8OaLSJuA44LGmp0qA1p0J8E5viY=; b=JeFP6f9/TSTa36LGSaEDFv2qFIvjPNb51waxyWKJxm9NNPWJuWleG8kXYAwfjKonwBhdB8V0eoLeLbJulRlM2b4UaUxmE+/YcUEAepvEh+SGYXZ6CeGKGejMvXSIMx8S6dV4/nw5PcKRQSbtZ7z7VoL2yuD44e/yRQLAY+GktU8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385769597486.27253447311614; Sat, 30 Apr 2022 23:16:09 -0700 (PDT) Received: from localhost ([::1]:45642 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2sJ-00047W-Ty for importer@patchew.org; Sun, 01 May 2022 02:16:07 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43560) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tr-0006tO-UJ for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:58 -0400 Received: from mail-pl1-x634.google.com ([2607:f8b0:4864:20::634]:34731) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2To-0001Ib-6E for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:51 -0400 Received: by mail-pl1-x634.google.com with SMTP id n8so10288409plh.1 for ; Sat, 30 Apr 2022 22:50:47 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=pOb3rzseCiR8Xy7i8OaLSJuA44LGmp0qA1p0J8E5viY=; b=KoNsez0QrTAorjU71pNnpYh8w4Cw+zyHW5aOJxqQiqrx0yIIWiIPJHa9fWUGfrOiPu AKu+8r0doEdpeG8tQTOfknfBeIEnfSIBU/edvb+yR6yYj0tq/9H8IbE9rD/W93VpXoS/ HRI4Lfm9wZ9yIX+IGkvtZxHEpCZrET7kgTDZj89k3OYxBxwdtUV+3Qa61/dRv/W8fbBI ogl0Tmo6kzbt6kO7UJ5WRuecuAZ8VwcaHz1PqcgZCnH6gMvS0lBGOv8NWr1Tiw0Wa9Iq WfU04Jvu8oqezGaz8HDMu0ss0AgxCDVAcZ++DZsR/6uOnrgG39E2SWpu2fwiauIlHG/L 9klA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=pOb3rzseCiR8Xy7i8OaLSJuA44LGmp0qA1p0J8E5viY=; b=GrHdebP4mOEFoqz7Q9VE4SjGIG3e/IujDSbrQ/ye66FrWB5CRhCFgbWOyrkueD0Dmw KzvxAR/UqwDYA+Fr/kUV2PBwMgB52BTbsB0yDYPI/VGfDX913YfL2TFiiErWSUZbkbnv vtsinpu36Zki+wpyO4Y32Mhp/P5lRh33qYpWjmQNMv34MlKxTkMyoSw7bn1iyyGUK0fr Ss827WKLKFNV9PTBsvkTBRXvZsqotyw6LekE571cZrjYeggU2EgkmsKXPv6xhK3CkPB4 cGZFuzAFzkleVYWpsaP0N8XL/MID600INhahwUnOvBRltpX377yBbHn+Prvml+3b3PK1 v5Cw== X-Gm-Message-State: AOAM533SaJrlwiYEOOgRNFcVelJNb+YpSd1QYy3t6y+MO3f1U5rukVPp fVQA13RPBFt5WrV59jtrEkdvgx+aqA4DOQ== X-Google-Smtp-Source: ABdhPJwMV8HkW7mc1NGsTc04Q5d1ltmA6hzqOt4qp7rA2V4Nkw/LqIRU6Hfy1UH9vXIBBuC6OgvxMg== X-Received: by 2002:a17:902:a613:b0:156:b53d:c137 with SMTP id u19-20020a170902a61300b00156b53dc137mr6284992plq.73.1651384246904; Sat, 30 Apr 2022 22:50:46 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 18/45] target/arm: Reformat comments in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:50:00 -0700 Message-Id: <20220501055028.646596-19-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::634; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x634.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385770067100002 Content-Type: text/plain; charset="utf-8" Put the block comments into the current coding style. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 24 +++++++++++++++--------- 1 file changed, 15 insertions(+), 9 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 2ed07795d8..b690346469 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8496,15 +8496,16 @@ CpuDefinitionInfoList *qmp_query_cpu_definitions(Er= ror **errp) return cpu_list; } =20 +/* + * Private utility function for define_one_arm_cp_reg_with_opaque(): + * add a single reginfo struct to the hash table. + */ static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r, void *opaque, CPState state, CPSecureState secstate, int crm, int opc1, int opc2, const char *name) { - /* Private utility function for define_one_arm_cp_reg_with_opaque(): - * add a single reginfo struct to the hash table. - */ uint32_t key; ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; @@ -8568,7 +8569,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, =20 isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; if (isbanked) { - /* Register is banked (using both entries in array). + /* + * Register is banked (using both entries in array). * Overwriting fieldoffset as the array is only used to define * banked registers but later only fieldoffset is used. */ @@ -8577,7 +8579,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, =20 if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { - /* If the register is banked then we don't need to migrate or + /* + * If the register is banked then we don't need to migrate or * reset the 32-bit instance in certain cases: * * 1) If the register has both 32-bit and 64-bit instances the= n we @@ -8592,8 +8595,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } } else if ((secstate !=3D r->secure) && !ns) { - /* The register is not banked so we only want to allow migrati= on of - * the non-secure instance. + /* + * The register is not banked so we only want to allow migrati= on + * of the non-secure instance. */ r2->type |=3D ARM_CP_ALIAS; } @@ -8607,7 +8611,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, } } =20 - /* By convention, for wildcarded registers only the first + /* + * By convention, for wildcarded registers only the first * entry is used for migration; the others are marked as * ALIAS so we don't try to transfer the register * multiple times. Special registers (ie NOP/WFI) are @@ -8622,7 +8627,8 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS | ARM_CP_NO_GDB; } =20 - /* Check that raw accesses are either forbidden or handled. Note that + /* + * Check that raw accesses are either forbidden or handled. Note that * we can't assert this earlier because the setup of fieldoffset for * banked registers has to be done first. */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651386718; cv=none; d=zohomail.com; s=zohoarc; b=GHeTqK83Ylp77G8edj8D5ZQkNJei8W4QjxLn+s2TeAHiynqnnFW0F8FlMb4gVaAhLKTVuA6/GV8QbUO70Zut9uJQDXxqITdgfyym9vgSbe1uBFn9dqcjBfX+OZkx/Kdnv05pR3amXtL3guM9bOJlM6XgFqhhEH613sf1Y0TFeKk= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651386718; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=3plBYXX6SApkM+t7ZXN6wJ18Jh8soXA/Q1mctbH/v48=; b=i9OAWXvaqqej6F9PgK/0NUM+3kry5XtMc5yD7e1qvARswj+35q/74ZmPSZGVoewtcJg6ksLBV0BZHK2eBEgZwZ5vT9Dx5aOfEj4I9YSiS+MES/vicoyiyStnyqStZ6fuq/olkG+2w7gQjdGpIHjRK9Tbv6Tu33RUeWVZ2le2ch8= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651386718131216.66201975733634; Sat, 30 Apr 2022 23:31:58 -0700 (PDT) Received: from localhost ([::1]:39358 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl37c-0002K6-Hr for importer@patchew.org; Sun, 01 May 2022 02:31:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43580) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Ts-0006tP-64 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:58 -0400 Received: from mail-pj1-x102d.google.com ([2607:f8b0:4864:20::102d]:41553) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tp-0001Iu-2w for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:51 -0400 Received: by mail-pj1-x102d.google.com with SMTP id z5-20020a17090a468500b001d2bc2743c4so10494135pjf.0 for ; Sat, 30 Apr 2022 22:50:48 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:47 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=3plBYXX6SApkM+t7ZXN6wJ18Jh8soXA/Q1mctbH/v48=; b=Pc1fUI6F2kZ7VZF6EA7yj+Gt6lolPr80CN5Smrz5vWwO5nmQGuFEKPQVwrRQ2DmV/E a6DOJuLL9LbuuA7z73cYZooxhJq+nHtW4cbzXXHyYTJlcmh0px/zN1w1FlOHE91eSDo+ VcEDpgIBszlxeMhpX1r2TzkZJuVUnf98pfOYkzvquh3lQKmI/59GRh/kx+J4oInRke1e lVqZR0gnA1TgYPhcyT2EM9YzUsbexmB7sa3g5TJCRw542d12fO/CPPobGxY/ItPOxpGo iuNm/xwWSqZEE8hPZCWF2LgZYcPFeny+/6Bbj8Ud5VeanWP8y7Tgm1w/rbCQUTwnQqQS srOQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=3plBYXX6SApkM+t7ZXN6wJ18Jh8soXA/Q1mctbH/v48=; b=wjHfSwfmLYNI/1SLR768GXfBJ0T1cmTM4LRzferzbhb054bOYIG+HUxOgAu+RLlX9e QYujnRIDb/KtHfMu5I1KKVQjVas75R/5ICPXAYpo4vQ68yuQ+RoPO6Vp8rsImmiANBQ7 8E74jhAdim2MzASH2n+JwPRfgH7j2dWF0ynkUNs9uAu/+NmdRj3tryf+VHgQeYqXhBVl h1H7qnMSOrxFq2wFxj7okYvgyO118PGvc/8EmBcVdWjnaSPRFSkpgr3riaPtzBWBRSwQ /oeeLxf7DeAPnPD15swKZOjxrrXEc9fGFUHebpSLUUfeJqmP3gt9wkzO6EbaMCn3fKX1 eHxA== X-Gm-Message-State: AOAM530OuPdTNMKrk9jddGwIoxFvQ28KoPYTW8i/QDxnAYbbEvSMP785 Z00zndk82l5bvb/y+ce6tcQ2my/NiQk+jw== X-Google-Smtp-Source: ABdhPJwUb8Y8S90DoMLADKYIK99LhwKq/nfL1FVyE+pg5zu+1C+GCBmZfo8s5g120lv7BqMWqhJypQ== X-Received: by 2002:a17:90b:4a02:b0:1dc:4710:c1fe with SMTP id kk2-20020a17090b4a0200b001dc4710c1femr2252865pjb.208.1651384247795; Sat, 30 Apr 2022 22:50:47 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 19/45] target/arm: Remove HOST_BIG_ENDIAN ifdef in add_cpreg_to_hashtable Date: Sat, 30 Apr 2022 22:50:01 -0700 Message-Id: <20220501055028.646596-20-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102d; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651386718840100001 Content-Type: text/plain; charset="utf-8" Since ee3eb3a7ce72, our host endian indicator is unconditionally set, which means that we can use a normal C condition. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 9 +++------ 1 file changed, 3 insertions(+), 6 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index b690346469..4359739081 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -8602,12 +8602,9 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, r2->type |=3D ARM_CP_ALIAS; } =20 - if (r->state =3D=3D ARM_CP_STATE_BOTH) { -#if HOST_BIG_ENDIAN - if (r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); - } -#endif + if (HOST_BIG_ENDIAN && + r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); } } =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651385991; cv=none; d=zohomail.com; s=zohoarc; b=DNmYBfBUmkED801yW6CQ7BiMsVVyWbulqwhdlm6ao8OL77nxhercSwgrrByNvtcoarjJ39vBnGMp8PYmUhPhGL4BzWR+9v1uG0JbsmYxXRJ/d0sH1Dl1Dt7JlXhvXE1TOfAEUa6o9wu5MvQFpbxCj4MVM8fmJjqoKQ8+28HKOvE= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651385991; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=86JJW2/FsLKv+cotPyQaiKRVQrrBoAkHpPLmFPzaDwg=; b=eYKfqLw0FUPaC/fGC5uofF5JBpnBb14RpYjgn1BoqBqLEuC6VLiaHvKsKNmqZBeGp+4JYFEC7zv1ArxkpWpd9MtBHkJdYaAIXcNh/CDWMtCiUDXxABiSmltSMGeaWZimiLXalTjzIIxPinj1bhQwaW2n0wlXhg1BO5JaKRg3RlA= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651385991115129.41833593194826; Sat, 30 Apr 2022 23:19:51 -0700 (PDT) Received: from localhost ([::1]:52824 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2vt-0000de-UL for importer@patchew.org; Sun, 01 May 2022 02:19:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43636) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tt-0006tX-Ag for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:58 -0400 Received: from mail-pl1-x635.google.com ([2607:f8b0:4864:20::635]:40546) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tq-0001JN-8H for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:53 -0400 Received: by mail-pl1-x635.google.com with SMTP id i1so4136920plg.7 for ; Sat, 30 Apr 2022 22:50:49 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:48 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=86JJW2/FsLKv+cotPyQaiKRVQrrBoAkHpPLmFPzaDwg=; b=ekmmEKwRd9JGSms00gpnpBQruTkcfb1tSYSURO0+FzYuTmFloOuyeh+TG10Dj8aolv IeGym91dmCLr45pyQNXljS8fH9S2oflhAr0I4pFOhTX9ToR3UFVMdnwYmteIY5tIqXaU 0w/FcMyfz19KxS0kwcV9fMBk/ofrU2gk6ErNGtduLSYVqo9GMBGVoLb+IirX3IGW9UIm ByM7G+UUcXqU+vFrFqC+Tvs8w2a0pA2dXONMZggDHvqFGOfDOqIijbcAmhTYvJHVdmnf 4qnyCUcd4W4qVSItWoCflXWtzWIh3gPU+gtr5eGjQvN8R8Yu+aYIBkv5TfLmzG3e38wE +RlQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=86JJW2/FsLKv+cotPyQaiKRVQrrBoAkHpPLmFPzaDwg=; b=bJEkQaor9zPQn1pEOKgFCsFA4XNv3Yoz4oRYhcJrUiPrFtzlivvw/1ZQS4b+lN4Zzr mwmWFzlgMPIqABbI2iT7IJ4Ap2jFOZtndPgbpiNeIYkh8m0J2UIM8/l2Z/BqFQQqEQnc xt2rqRYOgWONBVBFEKqVj+29AcwbVfRMaD/xjI5lP0VMTtY+GmR30tSaViTE+rKO3XLO y9cknLuM9y8NiTj5qDpZrDjlqPNXqiekbEhmtMtfPpRLOKxjpv0FZzxiUMllmBYAnHhW M0blMfgkzetVCHSSfzdXGqRGPyeY6b/OR3pJh58ZgoSkm3GjZTrAwgqRGObuze8/lphs 8L4w== X-Gm-Message-State: AOAM533+tuYMJUvn+Ae8ZiAihL8ZWxKcLWBMX/Luyb74iET3Z4+Oa+iP lG+wQ1UoNBIMXcZOrNnJfoY7pshZQbzXdQ== X-Google-Smtp-Source: ABdhPJyLIxlQAmykSFzVT5igepbyNzFW2BOGf0RznG7lvMwlGFCO06NnfuwMUOJOTKUfGGoH4ewR6w== X-Received: by 2002:a17:90b:1d87:b0:1d9:c22a:eba with SMTP id pf7-20020a17090b1d8700b001d9c22a0ebamr7100156pjb.83.1651384248742; Sat, 30 Apr 2022 22:50:48 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 20/45] target/arm: Handle cpreg registration for missing EL Date: Sat, 30 Apr 2022 22:50:02 -0700 Message-Id: <20220501055028.646596-21-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::635; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x635.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651385993233100001 Content-Type: text/plain; charset="utf-8" More gracefully handle cpregs when EL2 and/or EL3 are missing. If the reg is entirely inaccessible, do not register it at all. If the reg is for EL2, and EL3 is present but EL2 is not, either discard, squash to const, or keep unchanged. Per rule RJFFP, mark the 4 aarch32 hypervisor access registers with ARM_CP_EL3_NO_EL2_KEEP, and mark all of the EL2 address translation and tlb invalidation "regs" ARM_CP_EL3_NO_EL2_UNDEF. This will simplify cpreg registration for conditional arm features. Signed-off-by: Richard Henderson --- v4: Add ARM_CP_EL3_NO_EL2_{UNDEF,KEEP}. --- target/arm/cpregs.h | 9 +++ target/arm/helper.c | 163 ++++++++++++++++++++++++++++++-------------- 2 files changed, 120 insertions(+), 52 deletions(-) diff --git a/target/arm/cpregs.h b/target/arm/cpregs.h index 73984549d2..9ed94d7121 100644 --- a/target/arm/cpregs.h +++ b/target/arm/cpregs.h @@ -102,6 +102,15 @@ enum { ARM_CP_SVE =3D 1 << 14, /* Flag: Do not expose in gdb sysreg xml. */ ARM_CP_NO_GDB =3D 1 << 15, + /* + * Flags: If EL3 but not EL2... + * - UNDEF: discard the cpreg, + * - KEEP: retain the cpreg as is, + * - else: set CONST on the cpreg. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + ARM_CP_EL3_NO_EL2_UNDEF =3D 1 << 16, + ARM_CP_EL3_NO_EL2_KEEP =3D 1 << 17, }; =20 /* diff --git a/target/arm/helper.c b/target/arm/helper.c index 4359739081..598a9253d0 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5056,16 +5056,17 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .access =3D PL1_RW, .readfn =3D spsel_read, .writefn =3D spsel_write= }, { .name =3D "FPEXC32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_ALIAS | ARM_CP_FPU, + .access =3D PL2_RW, + .type =3D ARM_CP_ALIAS | ARM_CP_FPU | ARM_CP_EL3_NO_EL2_KEEP, .fieldoffset =3D offsetof(CPUARMState, vfp.xregs[ARM_VFP_FPEXC]) }, { .name =3D "DACR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 3, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, .writefn =3D dacr_write, .raw_writefn =3D raw_write, .fieldoffset =3D offsetof(CPUARMState, cp15.dacr32_el2) }, { .name =3D "IFSR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, .resetvalue =3D 0, + .access =3D PL2_RW, .resetvalue =3D 0, .type =3D ARM_CP_EL3_NO_EL2_K= EEP, .fieldoffset =3D offsetof(CPUARMState, cp15.ifsr32_el2) }, { .name =3D "SPSR_IRQ", .state =3D ARM_CP_STATE_AA64, .type =3D ARM_CP_ALIAS, @@ -5542,27 +5543,27 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { .writefn =3D tlbimva_hyp_is_write }, { .name =3D "TLBI_ALLE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 0, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2_write }, { .name =3D "TLBI_VAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2_write }, { .name =3D "TLBI_VALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 7, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2_write }, { .name =3D "TLBI_ALLE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2is_write }, { .name =3D "TLBI_VAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 1, - .type =3D ARM_CP_NO_RAW, .access =3D PL2_W, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_VALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 3, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, #ifndef CONFIG_USER_ONLY /* Unlike the other EL2-related AT operations, these must @@ -5572,11 +5573,13 @@ static const ARMCPRegInfo el2_cp_reginfo[] =3D { { .name =3D "AT_S1E2R", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 0, .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, { .name =3D "AT_S1E2W", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 7, .crm =3D 8, .opc2 =3D 1, .access =3D PL2_W, .accessfn =3D at_s1e2_access, - .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC, .writefn =3D ats_write6= 4 }, + .type =3D ARM_CP_NO_RAW | ARM_CP_RAISES_EXC | ARM_CP_EL3_NO_EL2_UNDE= F, + .writefn =3D ats_write64 }, /* The AArch32 ATS1H* operations are CONSTRAINED UNPREDICTABLE * if EL2 is not implemented; we choose to UNDEF. Behaviour at EL3 * with SCR.NS =3D=3D 0 outside Monitor mode is UNPREDICTABLE; we choo= se @@ -6076,7 +6079,7 @@ static const ARMCPRegInfo debug_cp_reginfo[] =3D { { .name =3D "DBGVCR32_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 2, .opc1 =3D 4, .crn =3D 0, .crm =3D 7, .opc2 =3D 0, .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_NOP }, + .type =3D ARM_CP_NOP | ARM_CP_EL3_NO_EL2_KEEP }, /* Dummy MDCCINT_EL1, since we don't implement the Debug Communications * Channel but Linux may try to access this register. The 32-bit * alias is DBGDCCINT. @@ -6892,11 +6895,11 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NOP }, { .name =3D "TLBI_RVAE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVALE2IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 2, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RIPAS2E1", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 4, .opc2 =3D 2, @@ -6906,19 +6909,19 @@ static const ARMCPRegInfo tlbirange_reginfo[] =3D { .access =3D PL2_W, .type =3D ARM_CP_NOP }, { .name =3D "TLBI_RVAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 5, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2is_write }, { .name =3D "TLBI_RVAE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2_write }, { .name =3D "TLBI_RVALE2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 6, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_rvae2_write }, { .name =3D "TLBI_RVAE3IS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 6, .crn =3D 8, .crm =3D 2, .opc2 =3D 1, @@ -6973,11 +6976,11 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .writefn =3D tlbi_aa64_vae1is_write }, { .name =3D "TLBI_ALLE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_alle2is_write }, { .name =3D "TLBI_VAE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_ALLE1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 4, @@ -6985,7 +6988,7 @@ static const ARMCPRegInfo tlbios_reginfo[] =3D { .writefn =3D tlbi_aa64_alle1is_write }, { .name =3D "TLBI_VALE2OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 5, - .access =3D PL2_W, .type =3D ARM_CP_NO_RAW, + .access =3D PL2_W, .type =3D ARM_CP_NO_RAW | ARM_CP_EL3_NO_EL2_UNDEF, .writefn =3D tlbi_aa64_vae2is_write }, { .name =3D "TLBI_VMALLS12E1OS", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 1, .opc1 =3D 4, .crn =3D 8, .crm =3D 1, .opc2 =3D 6, @@ -8506,13 +8509,14 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, int crm, int opc1, int opc2, const char *name) { + CPUARMState *env =3D &cpu->env; uint32_t key; ARMCPRegInfo *r2; bool is64 =3D r->type & ARM_CP_64BIT; bool ns =3D secstate & ARM_CP_SECSTATE_NS; int cp =3D r->cp; - bool isbanked; size_t name_len; + bool make_const; =20 switch (state) { case ARM_CP_STATE_AA32: @@ -8547,6 +8551,32 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, cons= t ARMCPRegInfo *r, } } =20 + /* + * Eliminate registers that are not present because the EL is missing. + * Doing this here makes it easier to put all registers for a given + * feature into the same ARMCPRegInfo array and define them all at onc= e. + */ + make_const =3D false; + if (arm_feature(env, ARM_FEATURE_EL3)) { + /* + * An EL2 register without EL2 but with EL3 is (usually) RES0. + * See rule RJFFP in section D1.1.3 of DDI0487H.a. + */ + int min_el =3D ctz32(r->access) / 2; + if (min_el =3D=3D 2 && !arm_feature(env, ARM_FEATURE_EL2)) { + if (r->type & ARM_CP_EL3_NO_EL2_UNDEF) { + return; + } + make_const =3D !(r->type & ARM_CP_EL3_NO_EL2_KEEP); + } + } else { + CPAccessRights max_el =3D (arm_feature(env, ARM_FEATURE_EL2) + ? PL2_RW : PL1_RW); + if ((r->access & max_el) =3D=3D 0) { + return; + } + } + /* Combine cpreg and name into one allocation. */ name_len =3D strlen(name) + 1; r2 =3D g_malloc(sizeof(*r2) + name_len); @@ -8567,44 +8597,73 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, con= st ARMCPRegInfo *r, r2->opaque =3D opaque; } =20 - isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[1]; - if (isbanked) { + if (make_const) { + /* This should not have been a very special register to begin. */ + int old_special =3D r2->type & ARM_CP_SPECIAL_MASK; + assert(old_special =3D=3D 0 || old_special =3D=3D ARM_CP_NOP); /* - * Register is banked (using both entries in array). - * Overwriting fieldoffset as the array is only used to define - * banked registers but later only fieldoffset is used. + * Set the special function to CONST, retaining the other flags. + * This is important for e.g. ARM_CP_SVE so that we still + * take the SVE trap if CPTR_EL3.EZ =3D=3D 0. */ - r2->fieldoffset =3D r->bank_fieldoffsets[ns]; - } + r2->type =3D (r2->type & ~ARM_CP_SPECIAL_MASK) | ARM_CP_CONST; + /* + * Usually, these registers become RES0, but there are a few + * special cases like VPIDR_EL2 which have a constant non-zero + * value with writes ignored. So leave resetvalue as is. + * + * ARM_CP_CONST has precedence, so removing the callbacks and + * offsets are not strictly necessary, but it is potentially + * less confusing to debug later. + */ + r2->readfn =3D NULL; + r2->writefn =3D NULL; + r2->raw_readfn =3D NULL; + r2->raw_writefn =3D NULL; + r2->resetfn =3D NULL; + r2->fieldoffset =3D 0; + r2->bank_fieldoffsets[0] =3D 0; + r2->bank_fieldoffsets[1] =3D 0; + } else { + bool isbanked =3D r->bank_fieldoffsets[0] && r->bank_fieldoffsets[= 1]; =20 - if (state =3D=3D ARM_CP_STATE_AA32) { if (isbanked) { /* - * If the register is banked then we don't need to migrate or - * reset the 32-bit instance in certain cases: - * - * 1) If the register has both 32-bit and 64-bit instances the= n we - * can count on the 64-bit instance taking care of the - * non-secure bank. - * 2) If ARMv8 is enabled then we can count on a 64-bit version - * taking care of the secure bank. This requires that sepa= rate - * 32 and 64-bit definitions are provided. + * Register is banked (using both entries in array). + * Overwriting fieldoffset as the array is only used to define + * banked registers but later only fieldoffset is used. */ - if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || - (arm_feature(&cpu->env, ARM_FEATURE_V8) && !ns)) { + r2->fieldoffset =3D r->bank_fieldoffsets[ns]; + } + if (state =3D=3D ARM_CP_STATE_AA32) { + if (isbanked) { + /* + * If the register is banked then we don't need to migrate= or + * reset the 32-bit instance in certain cases: + * + * 1) If the register has both 32-bit and 64-bit instances + * then we can count on the 64-bit instance taking care + * of the non-secure bank. + * 2) If ARMv8 is enabled then we can count on a 64-bit + * version taking care of the secure bank. This requir= es + * that separate 32 and 64-bit definitions are provided. + */ + if ((r->state =3D=3D ARM_CP_STATE_BOTH && ns) || + (arm_feature(env, ARM_FEATURE_V8) && !ns)) { + r2->type |=3D ARM_CP_ALIAS; + } + } else if ((secstate !=3D r->secure) && !ns) { + /* + * The register is not banked so we only want to allow + * migration of the non-secure instance. + */ r2->type |=3D ARM_CP_ALIAS; } - } else if ((secstate !=3D r->secure) && !ns) { - /* - * The register is not banked so we only want to allow migrati= on - * of the non-secure instance. - */ - r2->type |=3D ARM_CP_ALIAS; - } =20 - if (HOST_BIG_ENDIAN && - r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { - r2->fieldoffset +=3D sizeof(uint32_t); + if (HOST_BIG_ENDIAN && + r->state =3D=3D ARM_CP_STATE_BOTH && r2->fieldoffset) { + r2->fieldoffset +=3D sizeof(uint32_t); + } } } =20 @@ -8615,7 +8674,7 @@ static void add_cpreg_to_hashtable(ARMCPU *cpu, const= ARMCPRegInfo *r, * multiple times. Special registers (ie NOP/WFI) are * never migratable and not even raw-accessible. */ - if (r->type & ARM_CP_SPECIAL_MASK) { + if (r2->type & ARM_CP_SPECIAL_MASK) { r2->type |=3D ARM_CP_NO_RAW; } if (((r->crm =3D=3D CP_ANY) && crm !=3D 0) || --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651387214; cv=none; d=zohomail.com; s=zohoarc; b=ZkXqn3b8cAKjuojZnxdsFcbVHPxkfrvDJcvV7N8KIuuS+de9scSp2NSvUqn51ycAN7tAcXLto2YgQ2RxLsDbMf3Ewv8TebItbNf9v/9WxdDNIjDuu0OvfYpZZnL+63wf4VeAJFRujVFuC8Adh2d5gNvqfBMcJwm/2DNnRrJRFAg= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651387214; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=lRiwKmtxyYjFps6kK3GQ6tE0B9LAUXXJNHq5l1sdG8c=; b=Q1RedEiXtsZAwV42bBwPOgdwj1v/9w3LYaOaUzpHtr4n3VnpxvdE4NkCdCDT16ztdM9fvyutd+14BE+a+z8K18RwCcNdabEp8OwpwVrLMrEITl9RBnvZe/8gSP8mjViwaJVG9nWhfDR3WdLPfvTEArAiqUvaKehUG8X/7gYlOQs= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387213935245.11646630464634; Sat, 30 Apr 2022 23:40:13 -0700 (PDT) Received: from localhost ([::1]:46504 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3Fc-0007Yc-7x for importer@patchew.org; Sun, 01 May 2022 02:40:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43660) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tt-0006tb-SD for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:58 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:39607) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tr-0001Js-4Y for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:53 -0400 Received: by mail-pj1-x1036.google.com with SMTP id a15-20020a17090ad80f00b001dc2e23ad84so1790710pjv.4 for ; Sat, 30 Apr 2022 22:50:50 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=lRiwKmtxyYjFps6kK3GQ6tE0B9LAUXXJNHq5l1sdG8c=; b=D8txeQ5Rq1oJGEiw8rVi9QZUCegTfomha5cdxRAOQMLo17h0wMx0ekodIF/TQKeIw+ s5Ae3Y2bkxbZPBmQNhshu3htqE99woTKov3CguBIIQ2GAQsANMXwMEWT/2x2IRlozqi0 Fn3IZzwDMKg0cUZL0WKAaAbots8Yee9CxTji/Ax1eDv8RnOhaLOPLfQd4RY7JIoj2s5t gOp57fmzD+jdZlocVJXsKGMtJm8gYv68G3jE/i5qDsuXgGU1rdFrcevNBWDqDJTg9CLZ /CJaFhgI1X3jqNJePH65JSZ5gYJlunDoAaP+bSFw+u21D/L3ZSuUMNyZSk4tW/075lvF 9xaQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=lRiwKmtxyYjFps6kK3GQ6tE0B9LAUXXJNHq5l1sdG8c=; b=QN+DPG+58juovO9q58eK7dCtBFyTma5nPm71+yuorzWmYiLOea8pp/6bcF/0QUZsMD QTpf5ojn1Lc15zXfsEMimkDu28UTGNcRUeF6pkrKe8eZrH471WmfrdsKj3XDpEqp6MJI 6Mys9d9U9P0+p2/s+1zpDbzeap/GZJalAUMIunAC83/Xr4kKm7LVEG36/1lTDzBb5r0h YoSE75KYraRe0Jb/14s124WbFE+XG7LpkStaJtPfBvRTJG7qtV39+GryVEzZ7CbBdumo r4wE4doOFv4zkUjiS0AU1cVEI5YGOmhTKEuvvSbxFDUfkGV5dy5JIJx5AvTmD22pI9D+ 2ZAA== X-Gm-Message-State: AOAM531FxRLv6B0CA2vY+lVU17XzAB2vwPdvHB7xnwMtjOrn3W/CfLSd laeQVMd6k0A+NmURYIxvngusKDcHkhAMBg== X-Google-Smtp-Source: ABdhPJyNxG26Sj5l5HAUoQw0/jortdf8R0+oImI/KcWywWrC1RGRdNO0T36i8X7C9og1miCWXG9Fbw== X-Received: by 2002:a17:903:32d2:b0:15e:8b2b:a5c2 with SMTP id i18-20020a17090332d200b0015e8b2ba5c2mr6554291plr.153.1651384249703; Sat, 30 Apr 2022 22:50:49 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 21/45] target/arm: Drop EL3 no EL2 fallbacks Date: Sat, 30 Apr 2022 22:50:03 -0700 Message-Id: <20220501055028.646596-22-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651387215214100001 Content-Type: text/plain; charset="utf-8" Drop el3_no_el2_cp_reginfo, el3_no_el2_v8_cp_reginfo, and the local vpidr_regs definition, and rely on the squasing to ARM_CP_CONST while registering. Signed-off-by: Richard Henderson --- target/arm/helper.c | 158 ++++---------------------------------------- 1 file changed, 13 insertions(+), 145 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 598a9253d0..e24e0749ac 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5099,124 +5099,6 @@ static const ARMCPRegInfo v8_cp_reginfo[] =3D { .fieldoffset =3D offsetoflow32(CPUARMState, cp15.mdcr_el3) }, }; =20 -/* Used to describe the behaviour of EL2 regs when EL2 does not exist. */ -static const ARMCPRegInfo el3_no_el2_cp_reginfo[] =3D { - { .name =3D "VBAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore }, - { .name =3D "HCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HACR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 7, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "ESR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "AMAIR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "HAMAIR1", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 10, .crm =3D 3, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR0_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "AFSR1_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "TCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "VTTBR", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 6, .crm =3D 2, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetvalue =3D 0 }, - { .name =3D "VTTBR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "SCTLR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "TTBR0_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HTTBR", .cp =3D 15, .opc1 =3D 4, .crm =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHCTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 1, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 0, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTVOFF", .cp =3D 15, .opc1 =3D 4, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 2, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CVAL", .cp =3D 15, .opc1 =3D 6, .crm =3D 14, - .access =3D PL2_RW, .type =3D ARM_CP_64BIT | ARM_CP_CONST, - .resetvalue =3D 0 }, - { .name =3D "CNTHP_TVAL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CNTHP_CTL_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 14, .crm =3D 2, .opc2 =3D 1, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "MDCR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 1, - .access =3D PL2_RW, .accessfn =3D access_tda, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HPFAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 4, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HSTR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 3, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "FAR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "HIFAR", .state =3D ARM_CP_STATE_AA32, - .type =3D ARM_CP_CONST, - .cp =3D 15, .opc1 =3D 4, .crn =3D 6, .crm =3D 0, .opc2 =3D 2, - .access =3D PL2_RW, .resetvalue =3D 0 }, -}; - -/* Ditto, but for registers which exist in ARMv8 but not v7 */ -static const ARMCPRegInfo el3_no_el2_v8_cp_reginfo[] =3D { - { .name =3D "HCR2", .state =3D ARM_CP_STATE_AA32, - .cp =3D 15, .opc1 =3D 4, .crn =3D 1, .crm =3D 1, .opc2 =3D 4, - .access =3D PL2_RW, - .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, -}; - static void do_hcr_write(CPUARMState *env, uint64_t value, uint64_t valid_= mask) { ARMCPU *cpu =3D env_archcpu(env); @@ -7902,7 +7784,17 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, v8_idregs); define_arm_cp_regs(cpu, v8_cp_reginfo); } - if (arm_feature(env, ARM_FEATURE_EL2)) { + + /* + * Register the base EL2 cpregs. + * Pre v8, these registers are implemented only as part of the + * Virtualization Extensions (EL2 present). Beginning with v8, + * if EL2 is missing but EL3 is enabled, mostly these become + * RES0 from EL3, with some specific exceptions. + */ + if (arm_feature(env, ARM_FEATURE_EL2) + || (arm_feature(env, ARM_FEATURE_EL3) + && arm_feature(env, ARM_FEATURE_V8))) { uint64_t vmpidr_def =3D mpidr_read_val(env); ARMCPRegInfo vpidr_regs[] =3D { { .name =3D "VPIDR", .state =3D ARM_CP_STATE_AA32, @@ -7943,33 +7835,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) }; define_one_arm_cp_reg(cpu, &rvbar); } - } else { - /* If EL2 is missing but higher ELs are enabled, we need to - * register the no_el2 reginfos. - */ - if (arm_feature(env, ARM_FEATURE_EL3)) { - /* When EL3 exists but not EL2, VPIDR and VMPIDR take the value - * of MIDR_EL1 and MPIDR_EL1. - */ - ARMCPRegInfo vpidr_regs[] =3D { - { .name =3D "VPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 0, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_CONST, .resetvalue =3D cpu->midr, - .fieldoffset =3D offsetof(CPUARMState, cp15.vpidr_el2) }, - { .name =3D "VMPIDR_EL2", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 0, .crm =3D 0, .opc2 = =3D 5, - .access =3D PL2_RW, .accessfn =3D access_el3_aa32ns, - .type =3D ARM_CP_NO_RAW, - .writefn =3D arm_cp_write_ignore, .readfn =3D mpidr_read= }, - }; - define_arm_cp_regs(cpu, vpidr_regs); - define_arm_cp_regs(cpu, el3_no_el2_cp_reginfo); - if (arm_feature(env, ARM_FEATURE_V8)) { - define_arm_cp_regs(cpu, el3_no_el2_v8_cp_reginfo); - } - } } + + /* Register the base EL3 cpregs. */ if (arm_feature(env, ARM_FEATURE_EL3)) { define_arm_cp_regs(cpu, el3_cp_reginfo); ARMCPRegInfo el3_regs[] =3D { --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651387861; cv=none; d=zohomail.com; s=zohoarc; b=WTF1fzpVcqxSn8rJ8lrZtGtm6slmJuTbp43rlQWlsI0wtcCU/s0Gf//RPboWlKWm/xJbnyyZJBdaSAVthDjkrEm/nymxFCwxZieJ8OlYonIY7rkJLFDwXsw0k32PbCvSqxq8yuUOjMMMwQwfKoi10v0cdvedztgkDA8f56R3YdU= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651387861; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=fg33AYGqWxlbsFqDHnUVCK+5A1bEa2zIHmnKmyfZL/g=; b=dbtgzucEzmhZljtnG1KfvZroFPKxgeXK5vjQk44d42hkbPIRNqUWdpNOEuA6s7tZ/UPMYzKxThXpqALcUuUbdBvIziNGkaC7poELXjX3Tr81k4VqK3TQuvahc+gPdJKJR+sxJzvhu4bUSSGNqcmpXtJlznBf1IJu6CdRsncayWU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387861790842.0012943177564; Sat, 30 Apr 2022 23:51:01 -0700 (PDT) Received: from localhost ([::1]:33204 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3Pz-0001B3-Vh for importer@patchew.org; Sun, 01 May 2022 02:50:58 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43688) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tw-0006ti-Oj for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:59 -0400 Received: from mail-pj1-x1030.google.com ([2607:f8b0:4864:20::1030]:37600) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Ts-0001KL-1B for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:54 -0400 Received: by mail-pj1-x1030.google.com with SMTP id t11-20020a17090ad50b00b001d95bf21996so13756154pju.2 for ; Sat, 30 Apr 2022 22:50:51 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:50 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=fg33AYGqWxlbsFqDHnUVCK+5A1bEa2zIHmnKmyfZL/g=; b=uaexpWmwTOmJFccnWa30znhIT5ngRAKa25R5CwGDYNtV2cmATC76F5QSL27b3l556o Wl+Hz2pPTCofWAdBbzdO4LogUB+5l/TENer+FXgfeIjNlFZ4Kc2Ghz4d7iKY3uvMR5H6 KpVwydUESd/qGAf8W+1xm59IaSRAIavwAOBWtEV3UFDk74iJ97xP85YZAZgmjru78kbM jdzgjSeUmdlJmDXHP5rBLt3+dMMCC6E2yn7wk0W1ZXfquMm6SvWOK3GA5/WSR1shfwiF +kkBeoJ9OcaBHsQ9jHhayXyzw6RSyai6nkzMJplSJml+7w+WOGpfnzBWW59UubTW198G W9BQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=fg33AYGqWxlbsFqDHnUVCK+5A1bEa2zIHmnKmyfZL/g=; b=4UdQ+jkZ4iO7TKy7Gso6uaxAu93ObBiCoLAgyp1UyPRcCjH4N9pgMA7MlKW4nVIV+p eFp3h0cSCfvioj7xQVCQyERq9mIWNDAv9V0u+55q43Wt1gCJLJsV2XQI5N/7IZf7zz5H ui8P3f4QvL99w6yJoyIg8bFIM5HbG7DSQA02FsVC0BmQweAwLYy6JENXLMKrc6nGUCfm 8TkO9xHVGzQSGqirLRT9Do7O1ZDW+k9Z/wN25hiDLkTqeVjJFGAhmLMch8KZjbYK7i8y U8iSLJ0ec/5vnxAbVj/E2X4K/oDeYGDPprFiEChv8+WWq8FwyOY2c/DMU1uPH0rpI6KC gzUA== X-Gm-Message-State: AOAM533K9bF0hv0xPDgblMsKIPRohG8gtka7E3hKbiHbt2IifLWEzYI5 BmZ2mrvFM5gRT49Y/6fp0KGfKpMhnOITaQ== X-Google-Smtp-Source: ABdhPJz98L9xTq3eJqhGER1aS/D0nh8xBUL50WFuYF+2NR/02apLPxWWTDNQQmabE5asjeMwBYMfHQ== X-Received: by 2002:a17:902:f60e:b0:158:5c4d:d9b0 with SMTP id n14-20020a170902f60e00b001585c4dd9b0mr6558268plg.63.1651384250698; Sat, 30 Apr 2022 22:50:50 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 22/45] target/arm: Merge zcr reginfo Date: Sat, 30 Apr 2022 22:50:04 -0700 Message-Id: <20220501055028.646596-23-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1030; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1030.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651387862798100001 Content-Type: text/plain; charset="utf-8" Drop zcr_no_el2_reginfo and merge the 3 registers into one array, now that ZCR_EL2 can be squashed to RES0 and ZCR_EL3 dropped while registering. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- target/arm/helper.c | 55 ++++++++++++++------------------------------- 1 file changed, 17 insertions(+), 38 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index e24e0749ac..228472506d 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6122,35 +6122,22 @@ static void zcr_write(CPUARMState *env, const ARMCP= RegInfo *ri, } } =20 -static const ARMCPRegInfo zcr_el1_reginfo =3D { - .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write -}; - -static const ARMCPRegInfo zcr_no_el2_reginfo =3D { - .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL2_RW, .type =3D ARM_CP_SVE, - .readfn =3D arm_cp_read_zero, .writefn =3D arm_cp_write_ignore -}; - -static const ARMCPRegInfo zcr_el3_reginfo =3D { - .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, - .access =3D PL3_RW, .type =3D ARM_CP_SVE, - .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), - .writefn =3D zcr_write, .raw_writefn =3D raw_write +static const ARMCPRegInfo zcr_reginfo[] =3D { + { .name =3D "ZCR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[1]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL2_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[2]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, + { .name =3D "ZCR_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 1, .crm =3D 2, .opc2 =3D 0, + .access =3D PL3_RW, .type =3D ARM_CP_SVE, + .fieldoffset =3D offsetof(CPUARMState, vfp.zcr_el[3]), + .writefn =3D zcr_write, .raw_writefn =3D raw_write }, }; =20 void hw_watchpoint_update(ARMCPU *cpu, int n) @@ -8230,15 +8217,7 @@ void register_cp_regs_for_features(ARMCPU *cpu) } =20 if (cpu_isar_feature(aa64_sve, cpu)) { - define_one_arm_cp_reg(cpu, &zcr_el1_reginfo); - if (arm_feature(env, ARM_FEATURE_EL2)) { - define_one_arm_cp_reg(cpu, &zcr_el2_reginfo); - } else { - define_one_arm_cp_reg(cpu, &zcr_no_el2_reginfo); - } - if (arm_feature(env, ARM_FEATURE_EL3)) { - define_one_arm_cp_reg(cpu, &zcr_el3_reginfo); - } + define_arm_cp_regs(cpu, zcr_reginfo); } =20 #ifdef TARGET_AARCH64 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387750521818.153504282818; Sat, 30 Apr 2022 23:49:10 -0700 (PDT) Received: from localhost ([::1]:58864 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3OH-0007p0-GX for importer@patchew.org; Sun, 01 May 2022 02:49:09 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43700) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tw-0006tk-TC for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:59 -0400 Received: from mail-pj1-x1032.google.com ([2607:f8b0:4864:20::1032]:44858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Ts-0001Kh-Pn for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:54 -0400 Received: by mail-pj1-x1032.google.com with SMTP id m14-20020a17090a34ce00b001d5fe250e23so10458964pjf.3 for ; Sat, 30 Apr 2022 22:50:52 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=89Nxo79E/u1S6zfSk3J+FzT8WNvYQHnxRQfRBu3u2Wc=; b=oal+3fOqvUiwxZaObLoAZyPYnfFMUoUk/FOFXzWZwdovXCG4xyYjg1xzTJzGSIWmof BLn+iDV0z3LkFdIotC+PRL+q0YWVJ1hTZuWpjfuQfqSmajubWQuaFx5Ud8tppfys2/47 hJJP2c1rbwIHJ19s+zE3CfolCT6KAqa13qN0MmC/1l5+dICaXev1E93iBNU2q4LoVdoS ZA1fsW7Gc8GUZrdXl5o1mWMJhVHTrCshXGhuI4kQs74MTImWNTgxNZWqQMOut3KQrjXW WRlOOc4JFFkWuUCd2fDqK/RZSNFm4+oA5Ps9wIaJJqiex7sr1Yc2/laIPpHF8RJqUfHh +skQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1032; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1032.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651387752003100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index d1b558385c..7303103016 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3704,6 +3704,11 @@ static inline bool isar_feature_aa32_ssbs(const ARMI= SARegisters *id) return FIELD_EX32(id->id_pfr2, ID_PFR2, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa32_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX32(id->id_dfr0, ID_DFR0, COPDBG) >=3D 8; +} + /* * 64-bit feature tests via id registers. */ @@ -4010,6 +4015,11 @@ static inline bool isar_feature_aa64_ssbs(const ARMI= SARegisters *id) return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; } =20 +static inline bool isar_feature_aa64_debugv8p2(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64dfr0, ID_AA64DFR0, DEBUGVER) >=3D 8; +} + static inline bool isar_feature_aa64_sve2(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64zfr0, ID_AA64ZFR0, SVEVER) !=3D 0; @@ -4093,6 +4103,11 @@ static inline bool isar_feature_any_tts2uxn(const AR= MISARegisters *id) return isar_feature_aa64_tts2uxn(id) || isar_feature_aa32_tts2uxn(id); } =20 +static inline bool isar_feature_any_debugv8p2(const ARMISARegisters *id) +{ + return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:52 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=yvCvZqd/G9ya+Ohyp6HL6QjxXksg2p0BkixwWFQxr5M=; b=bKRJ+yvTIKKDRxoS6GLShppVZJUTKoPxXEyXZi4Vt4xEUAcRpc4fUe8z1Mfbed1Hx6 aKgasFfLDevmJvcqjxqVG41tR2PRZ5qzPBPpg5BsO9LL6l5mqBT/LWtO1HNF2Gzenuyr krekMVaXCGOsgUHRmGNB+SLsQE4m85k8Ee3rNB8qqOqxrLDKDCx0Erj/L0NPTu1aSRrk 0jxmQpkPJpmF26o2gIBBw9oK6wY5pJ0tufrW+mIoiQI3hB2eqd/yuGlcenOq41x2Ut9e Oav7uLFUBIQgcT6SUBhLvkFVSHxJFITShJ7IYKNGzoLyLTL0kl1rUSAC+V2+Bhr+m64P NHlw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=yvCvZqd/G9ya+Ohyp6HL6QjxXksg2p0BkixwWFQxr5M=; b=rKvvsTGiMiVqVJH2MB/FFZmkci08hLSUmZYuKN7kHIZuDeqRTgkY2h/g6JXM3bMydV 2sv/468dZ30egQtsXjoIAKF4IVHPwnWRfJkgyLv6si2sfKtTYTivV+Vz9UcwjBMYCxqC a1c8m9wFHzj8C9JXO8QR1D7el28yGEYbra6AC1kwB0Tc41J3wz6AQAnlN5ObaPYgQa9l /cBO7AkPmdEkeGRDsop3Qh+Q4lKZPmYO+9hL8T2EPaCyU9I28Gi7zNMKtyzQhWFZWyXh jFqYeNEQdu9ENGDvixDw0kxcWl1/yHyAC4cxjN62Wv6rGlDfHUB+44MLrevBW3MuhKTr YkUA== X-Gm-Message-State: AOAM532kKBY+HiMcez5ubh8bk3XEb+NPzPstUA/q3o+Or025rJtYlZNx cG28TyUHDVIKVAor6cSLGd6vq6FeqXPX8A== X-Google-Smtp-Source: ABdhPJzGHAYUjf5kUfB6bjAw/DljZJUo48tGRMzcyfF7qKi+BJZO8Pz9AdiwJHRG66LZBmajbacBsw== X-Received: by 2002:a17:902:a705:b0:156:9cc5:1d6f with SMTP id w5-20020a170902a70500b001569cc51d6fmr6358930plq.66.1651384252739; Sat, 30 Apr 2022 22:50:52 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 24/45] target/arm: Adjust definition of CONTEXTIDR_EL2 Date: Sat, 30 Apr 2022 22:50:06 -0700 Message-Id: <20220501055028.646596-25-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388367028100001 Content-Type: text/plain; charset="utf-8" This register is present for either VHE or Debugv8p2. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/helper.c | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/target/arm/helper.c b/target/arm/helper.c index 228472506d..a5741e0ad7 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -7246,11 +7246,14 @@ static const ARMCPRegInfo jazelle_regs[] =3D { .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, }; =20 +static const ARMCPRegInfo contextidr_el2 =3D { + .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, + .access =3D PL2_RW, + .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) +}; + static const ARMCPRegInfo vhe_reginfo[] =3D { - { .name =3D "CONTEXTIDR_EL2", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 1, - .access =3D PL2_RW, - .fieldoffset =3D offsetof(CPUARMState, cp15.contextidr_el[2]) }, { .name =3D "TTBR1_EL2", .state =3D ARM_CP_STATE_AA64, .opc0 =3D 3, .opc1 =3D 4, .crn =3D 2, .crm =3D 0, .opc2 =3D 1, .access =3D PL2_RW, .writefn =3D vmsa_tcr_ttbr_el2_write, @@ -8212,6 +8215,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_one_arm_cp_reg(cpu, &ssbs_reginfo); } =20 + if (cpu_isar_feature(aa64_vh, cpu) || + cpu_isar_feature(aa64_debugv8p2, cpu)) { + define_one_arm_cp_reg(cpu, &contextidr_el2); + } if (arm_feature(env, ARM_FEATURE_EL2) && cpu_isar_feature(aa64_vh, cpu= )) { define_arm_cp_regs(cpu, vhe_reginfo); } --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651386838983488.64910454638994; Sat, 30 Apr 2022 23:33:58 -0700 (PDT) Received: from localhost ([::1]:42088 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl39Z-0004Xk-P3 for importer@patchew.org; Sun, 01 May 2022 02:33:57 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43796) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tz-0006uh-MH for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:00 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:41555) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tw-0001LX-GC for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:59 -0400 Received: by mail-pl1-x633.google.com with SMTP id s14so10274474plk.8 for ; Sat, 30 Apr 2022 22:50:54 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:53 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=RP7uxMyjyjVvNPdZI9ZcRwKJ1kV5jw0hdIhEr9Ry6LU=; b=KAOcGi22p5Y9B4U5qqfqhC0mCShSherkdwmz8bERIp62UUNtgA4jWxPqUsm84ZW93d 9L5/OYe1ANls4CFjvMbR3i2ItFUiIpRpMIsmKe6RePphY0rCDkTv8Cc7PtvIXfmnUF1c elCpcyPQn01xdn/RYJ9qkamNEsdLFCICBXQYavB4SAuYVkiHB+hYoewf+wszLjEhtidM sHoMnSja623IqTo29Yx+kCahGRyFQhmk5hazk4u2QtlICfmXiHUSBiNMASEZm9RlnB2M vua2oYNsICwak0ZNSoNzzXburSG67/4ZNjC2wNAYXdwHvrvx/9BKQEnelnk/9/IB9Eui ITLQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=RP7uxMyjyjVvNPdZI9ZcRwKJ1kV5jw0hdIhEr9Ry6LU=; b=AV92CPjqiIb9F6kIIncpPo2m/lNcfN5/vn88/ROqlTxn+z5yf07cAXbOJfEj9/EOjh ACj/87mIwnkCvthdttiEPakGSicqJhQCBrXghKLutjJoYgrTUORzBxSLXhV5OihI3ih3 JyHb7XrFfsPiljMzEgKpTiAo72vITY16nYJlRcSx+HnAoMD+46SC4vdmyDIncRSy7HB1 rhmoB3vUxUjx/Q7vUHqqdBI+B/IT02aM204LVWw4eS8+C6TKGORPj8LjFAiWYKWEZ/Cq ZFN0WmnFXazu/L1zZh/apPFV302YiI8Q/SCt9QQr4BCV5O1t8J40mN7khSvV6a8XH8LF IjHA== X-Gm-Message-State: AOAM531F9ha5s08fXvpy8ZEQkCX0mPl/3SShH/AOrE3yIzFaUiA/GR79 uTlK41eCmWts1CeUc4xuA1kqvDLsL0SB/w== X-Google-Smtp-Source: ABdhPJzLNOPtck+q9u/9wFc0QgIfAPjrNEgGKYv5nv8EgHnipuIz+CWf/zBo+ahPzjV89KdEHwcE6g== X-Received: by 2002:a17:902:ea06:b0:15e:8367:150b with SMTP id s6-20020a170902ea0600b0015e8367150bmr6340797plg.167.1651384253840; Sat, 30 Apr 2022 22:50:53 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 25/45] target/arm: Move cortex impdef sysregs to cpu_tcg.c Date: Sat, 30 Apr 2022 22:50:07 -0700 Message-Id: <20220501055028.646596-26-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651386841290100001 Content-Type: text/plain; charset="utf-8" Previously we were defining some of these in user-only mode, but none of them are accessible from user-only, therefore define them only in system mode. This will shortly be used from cpu_tcg.c also. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: New patch. --- target/arm/internals.h | 6 ++++ target/arm/cpu64.c | 64 +++--------------------------------------- target/arm/cpu_tcg.c | 59 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 69 insertions(+), 60 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 255833479d..343b465d51 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1307,4 +1307,10 @@ int aarch64_fpu_gdb_get_reg(CPUARMState *env, GByteA= rray *buf, int reg); int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg); #endif =20 +#ifdef CONFIG_USER_ONLY +static inline void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) { } +#else +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); +#endif + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index c841d55d0e..33a0a71900 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -34,65 +34,9 @@ #include "hvf_arm.h" #include "qapi/visitor.h" #include "hw/qdev-properties.h" -#include "cpregs.h" +#include "internals.h" =20 =20 -#ifndef CONFIG_USER_ONLY -static uint64_t a57_a53_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *= ri) -{ - ARMCPU *cpu =3D env_archcpu(env); - - /* Number of cores is in [25:24]; otherwise we RAZ */ - return (cpu->core_count - 1) << 24; -} -#endif - -static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { -#ifndef CONFIG_USER_ONLY - { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, - { .name =3D "L2CTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, - .access =3D PL1_RW, .readfn =3D a57_a53_l2ctlr_read, - .writefn =3D arm_cp_write_ignore }, -#endif - { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ECTLR", - .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUACTLR", - .cp =3D 15, .opc1 =3D 0, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUECTLR", - .cp =3D 15, .opc1 =3D 1, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "CPUMERRSR", - .cp =3D 15, .opc1 =3D 2, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, - { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, - .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, - .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, - { .name =3D "L2MERRSR", - .cp =3D 15, .opc1 =3D 3, .crm =3D 15, - .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, -}; - static void aarch64_a57_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); @@ -143,7 +87,7 @@ static void aarch64_a57_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a53_initfn(Object *obj) @@ -196,7 +140,7 @@ static void aarch64_a53_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 static void aarch64_a72_initfn(Object *obj) @@ -247,7 +191,7 @@ static void aarch64_a72_initfn(Object *obj) cpu->gic_num_lrs =3D 4; cpu->gic_vpribits =3D 5; cpu->gic_vprebits =3D 5; - define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); + define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9338088b22..d078f06931 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,65 @@ #endif #include "cpregs.h" =20 +#ifndef CONFIG_USER_ONLY +static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + ARMCPU *cpu =3D env_archcpu(env); + + /* Number of cores is in [25:24]; otherwise we RAZ */ + return (cpu->core_count - 1) << 24; +} + +static const ARMCPRegInfo cortex_a72_a57_a53_cp_reginfo[] =3D { + { .name =3D "L2CTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2CTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 2, + .access =3D PL1_RW, .readfn =3D l2ctlr_read, + .writefn =3D arm_cp_write_ignore }, + { .name =3D "L2ECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 11, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ECTLR", + .cp =3D 15, .opc1 =3D 1, .crn =3D 9, .crm =3D 0, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2ACTLR", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 0, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 0, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUACTLR", + .cp =3D 15, .opc1 =3D 0, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUECTLR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 1, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUECTLR", + .cp =3D 15, .opc1 =3D 1, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "CPUMERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 2, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "CPUMERRSR", + .cp =3D 15, .opc1 =3D 2, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, + { .name =3D "L2MERRSR_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 1, .crn =3D 15, .crm =3D 2, .opc2 =3D 3, + .access =3D PL1_RW, .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "L2MERRSR", + .cp =3D 15, .opc1 =3D 3, .crm =3D 15, + .access =3D PL1_RW, .type =3D ARM_CP_CONST | ARM_CP_64BIT, .resetval= ue =3D 0 }, +}; + +void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu) +{ + define_arm_cp_regs(cpu, cortex_a72_a57_a53_cp_reginfo); +} +#endif /* !CONFIG_USER_ONLY */ + /* CPU models. These are not needed for the AArch64 linux-user build. */ #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651388135998193.6066319511733; Sat, 30 Apr 2022 23:55:35 -0700 (PDT) Received: from localhost ([::1]:37360 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3UU-0004BD-ID for importer@patchew.org; Sun, 01 May 2022 02:55:34 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43814) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2Tz-0006uk-Qx for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:00 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:47089) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tw-0001Lf-LT for qemu-devel@nongnu.org; Sun, 01 May 2022 01:50:59 -0400 Received: by mail-pl1-x62e.google.com with SMTP id c11so32385plg.13 for ; Sat, 30 Apr 2022 22:50:56 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.54 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:54 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=UglyDtIiGqvTEpM7++4FJGDf8c2/b7gl9ujFn0OBb74=; b=tyCP9cMk5CNmKZ7kPX4YGzb7kjKus9nH5qPWoqa5dJcq2H213YOmUembdgWdMYEwbC oy9HSTeOW2+nt0kEZm1xVA9RbJ1KcCNCkk1ErC0u90f0TGyFZGUiM+pHoUN9Ev7m5H4S 9xgaqJ9ok14BzIl4f4kTguFgPAUMA2w8JD9V17bC0jeTXB7aya/XUg0od0iCwPI4q6/t sAuhdwrZooofphv2jtmVeRLvaJwCnhsqISnqDFD2/gm1+cUqcVCQ9mCcSBnut1aeuzdo oimDPeBuv/zZqupoGnVT8AOpCRMWOkV/XCvIaHy6jruhRvWVuV1yUouSBCo+juXHBiPk EP7A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=UglyDtIiGqvTEpM7++4FJGDf8c2/b7gl9ujFn0OBb74=; b=RjDGAUruyQ9bhrV7nWhUrnj8BeaxK3ocVUW5404Q9TemUtkwtMNjBZDeVa+81TULgA 5psIRL707v3YDpclQR5XOQy75BPbuCkDeGcGcwypYQv29aHgRYei/cgqxjAxhXwXg3xy KF293ytIFPF/AEdJJYcsZ5HX78ryLETJNuXSavtyie9cV8RveeE0HKf7XqEpj+b4cNvY qD8T52jQf2jitCLgc/joMZOsWbWkUicTO5Ty8Z+uCf8MSBfhYzhE7Pf2UKIl6QxpRo6U yYS1F2E1XWyIm0vuRyP856rHdD6hcvti5Yc90x7b9d2ZsVQG7Wp2wvNwpBU38N2sbYVf +OYQ== X-Gm-Message-State: AOAM5339BcNYFIOOLjJRpvqazD01PUXBR1KkerxgzMkiCjSeqHRQf608 3qLm73puYwMAOAg/PCKEN1hNrFjGQ0AL5Q== X-Google-Smtp-Source: ABdhPJx2+Y0PWoYRNNWgJqTqRz8Sg+g8dOihjlKxHfsHEkjpBSeS/59jYVy00oCYZ9XDHR9TROUE1Q== X-Received: by 2002:a17:90b:30c4:b0:1d8:3395:a158 with SMTP id hi4-20020a17090b30c400b001d83395a158mr6976321pjb.184.1651384255227; Sat, 30 Apr 2022 22:50:55 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 26/45] target/arm: Update qemu-system-arm -cpu max to cortex-a57 Date: Sat, 30 Apr 2022 22:50:08 -0700 Message-Id: <20220501055028.646596-27-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388138304100001 Content-Type: text/plain; charset="utf-8" Instead of starting with cortex-a15 and adding v8 features to a v7 cpu, begin with a v8 cpu stripped of its aarch64 features. This fixes the long-standing to-do where we only enabled v8 features for user-only. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Create impdef sysregs; only enable short-vector support for user-only. --- target/arm/cpu_tcg.c | 151 ++++++++++++++++++++++++++----------------- 1 file changed, 92 insertions(+), 59 deletions(-) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index d078f06931..f9094c1752 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -994,71 +994,104 @@ static void arm_v7m_class_init(ObjectClass *oc, void= *data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); + uint32_t t; =20 - cortex_a15_initfn(obj); + /* aarch64_a57_initfn, advertising none of the aarch64 features */ + cpu->dtb_compatible =3D "arm,cortex-a57"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + cpu->midr =3D 0x411fd070; + cpu->revidr =3D 0x00000000; + cpu->reset_fpsid =3D 0x41034070; + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x12111111; + cpu->isar.mvfr2 =3D 0x00000043; + cpu->ctr =3D 0x8444c004; + cpu->reset_sctlr =3D 0x00c50838; + cpu->isar.id_pfr0 =3D 0x00000131; + cpu->isar.id_pfr1 =3D 0x00011011; + cpu->isar.id_dfr0 =3D 0x03010066; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_mmfr0 =3D 0x10101105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02102211; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00011142; + cpu->isar.id_isar5 =3D 0x00011121; + cpu->isar.id_isar6 =3D 0; + cpu->isar.dbgdidr =3D 0x3516d000; + cpu->clidr =3D 0x0a200023; + cpu->ccsidr[0] =3D 0x701fe00a; /* 32KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe012; /* 48KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ + define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* old-style VFP short-vector support */ - cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; =20 #ifdef CONFIG_USER_ONLY /* - * We don't set these in system emulation mode for the moment, - * since we don't correctly set (all of) the ID registers to - * advertise them. + * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. + * Only do this for user-mode, where -cpu max is the default, so that + * older v6 and v7 programs are more likely to work without adjustment. */ - set_feature(&cpu->env, ARM_FEATURE_V8); - { - uint32_t t; - - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - } -#endif /* CONFIG_USER_ONLY */ + cpu->isar.mvfr0 =3D FIELD_DP32(cpu->isar.mvfr0, MVFR0, FPSHVEC, 1); +#endif } #endif /* !TARGET_AARCH64 */ =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Hr9XVqQdGgVN9QhGevO5NcMkH7ocZJOMtPxHUW2biKk=; b=zo8ZOnOYe5x9TL0vqrWTngMo2610HN43KkwZyAQqNw1bl4HYNcCJDbapL1zhZ9shcT Tsop9dpNFpkv4HTNodpBjvK39L5gmYUCh/5ftEYPcJT13BOVFBK/FtUmvNviBYDSmRDV vNa0akZX4UUY8eWFs/fKqUV7cfVkukI5TFoCBbgep2EF8z7DQFhch0Ha4vHhEyH6jVQm wDWxn6F4u5OP7DbR4iaCyJ6F9SGcejsJw0ZVSUkIrGGI3vwcZzZjzaDv7IReD03iYrr5 NwggZQsyzoPHVRY0+1kVQi2mc8G+eQ5PeugmQSeNvRvVyd95sQS5DpUwYAE5C9kz2hCD 6v8Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Hr9XVqQdGgVN9QhGevO5NcMkH7ocZJOMtPxHUW2biKk=; b=ju7hBE7wFCIcJtlEcRC62hl/eALCBXq7p6MZicKsUxTOTuux1RuaraxUVSYzeO5TbE VzN1/Z2wMz7aHzBlmFauSsFYzJakW0Jwp0LELyHYJ2MnOIBpwqnnISr8mGFAHtBF8x51 oG71ipY+fxbxzjfBUTTrwZPX52kqlVcW2fp183w5Hq6HzyvAxyv714KYsWSiwE3QVjRk 2ffyq9LkjbTivK3vYZDtiaNvktnZSdBkXzPEqovZ5JfsaaRjSqJci98AlOY28IUlihJ7 T6R/bGgMG3z3oMAOQXQoKviu8VigYuEaGNvatHeQyF8jguB0ohsioyQ0IJ0pTKfZ+wbt 7vpA== X-Gm-Message-State: AOAM533MUB+ogIpjkdfndKj1GMZWp/96HSbL7iEv+NYZiDmz7gGXSMnZ 2AxbmstCJ4wEs7f+QmdEuiK2h7FOLcyhfg== X-Google-Smtp-Source: ABdhPJzjKzWlXwDCaqZVPs7eGKpHQRQLBuw6JCjicGssQlyNUYfrsr67fUrx3xz4ZQatkpocb6ADJg== X-Received: by 2002:a17:90a:884:b0:1d9:531c:9cd6 with SMTP id v4-20020a17090a088400b001d9531c9cd6mr6907382pjc.211.1651384256275; Sat, 30 Apr 2022 22:50:56 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 27/45] target/arm: Set ID_DFR0.PerfMon for qemu-system-arm -cpu max Date: Sat, 30 Apr 2022 22:50:09 -0700 Message-Id: <20220501055028.646596-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651387561208100001 Content-Type: text/plain; charset="utf-8" We set this for qemu-system-aarch64, but failed to do so for the strictly 32-bit emulation. Fixes: 3bec78447a9 ("target/arm: Provide ARMv8.4-PMU in '-cpu max'") Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu_tcg.c | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index f9094c1752..9aa2f737c1 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -1084,6 +1084,10 @@ static void arm_max_initfn(Object *obj) t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); cpu->isar.id_pfr2 =3D t; =20 + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; + #ifdef CONFIG_USER_ONLY /* * Break with true ARMv8 and add back old-style VFP short-vector suppo= rt. --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 165138658483132.78194159917973; Sat, 30 Apr 2022 23:29:44 -0700 (PDT) Received: from localhost ([::1]:37130 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl35T-0000q7-Bj for importer@patchew.org; Sun, 01 May 2022 02:29:43 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43890) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2U1-000700-Vj for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:02 -0400 Received: from mail-pj1-x1033.google.com ([2607:f8b0:4864:20::1033]:34440) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Ty-0001MF-LS for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:01 -0400 Received: by mail-pj1-x1033.google.com with SMTP id qe3-20020a17090b4f8300b001dc24e4da73so1999334pjb.1 for ; Sat, 30 Apr 2022 22:50:58 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:56 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=PGHFtJCWwmKlydMV+7EArb7n4KOf/foV/LwhKZjMzG4=; b=GzTMN+NVOKCw5LuECqmy+yFPEiag4FPZBiu/eBRayP1x0SMqRG17ZbKMTSSRx7BLzS MJSWkZ4g4bBKXwePyqBX4fu5U0tQsmKBVuMt2I56A7WkOHRRGpZsFq8FPFcn4ogtIRe7 EBVTiEIn1z9/ageYlBj4FSsNWzml4BkNJfWkyFnmTAktjRxq2myz+5KF43wGIv6DqRaN skJc47Rwd/9CWPkz8oAlVpucsRg/DY6lqvMkmQD8mjxwLTJsM2XAc8GAVHaAjJZ9rtxJ bK8g3rb48GU7WyTnqzyWulgYLhS/wJVhMgA/GYQPuMPcIWSqejqKWMEjdRBJEPI7kalH VtCQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=PGHFtJCWwmKlydMV+7EArb7n4KOf/foV/LwhKZjMzG4=; b=CQom3ncuoQfjwUsJkbELLzEp3AQrtLCA1Iknsp3OClu+N43VvdeMdjvpLZIg7+3E02 YHrWy+yyEsqJrXHPO6ZKPJGHviroHxbT3qPIv7PntJHJpywwAZJojAwvTQu/ebbE5Dsb 4E45CMhrpe8RkaW7COVrEWngn/Vp5Y+TwaXFmXy4iFPD1UhxhRGghU5C1QNjEX5k0Xly ouDoiTcTbrMr5V8sBlVhHPtRncCDmLPHACImkJhrD6HmmGELiis5q8w1v3cIOsdLw+/j EtHrgCYVVa4Vp5qy4Q4yqMwHm8HmNh+8tBSKET+I62ozSFsXWBoD2KLrErAAjNADEOXV hIdg== X-Gm-Message-State: AOAM533/YxYFGMkg5Sy73lz4uHUPpF50E4NjFfTOz2NXINfUVRmESDYD 7LkyEcXa7KdeytBgA/iy5wjU/bga+cAong== X-Google-Smtp-Source: ABdhPJyTDESF4NlaWzeNP58EoGJ8KDoPUPniRzPkqoigESKnIQfla+aBgSddm+HL5FNulpaJ9Ue6+g== X-Received: by 2002:a17:90b:4f4e:b0:1da:3d4b:2923 with SMTP id pj14-20020a17090b4f4e00b001da3d4b2923mr11957200pjb.86.1651384257301; Sat, 30 Apr 2022 22:50:57 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 28/45] target/arm: Split out aa32_max_features Date: Sat, 30 Apr 2022 22:50:10 -0700 Message-Id: <20220501055028.646596-29-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1033; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1033.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651386586230100001 Content-Type: text/plain; charset="utf-8" Share the code to set AArch32 max features so that we no longer have code drift between qemu{-system,}-{arm,aarch64}. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/internals.h | 2 + target/arm/cpu64.c | 50 +----------------- target/arm/cpu_tcg.c | 114 ++++++++++++++++++++++------------------- 3 files changed, 65 insertions(+), 101 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 343b465d51..c563b3735f 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1313,4 +1313,6 @@ static inline void define_cortex_a72_a57_a53_cp_regin= fo(ARMCPU *cpu) { } void define_cortex_a72_a57_a53_cp_reginfo(ARMCPU *cpu); #endif =20 +void aa32_max_features(ARMCPU *cpu); + #endif diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 33a0a71900..6da42af56e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -682,7 +682,6 @@ static void aarch64_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); uint64_t t; - uint32_t u; =20 if (kvm_enabled() || hvf_enabled()) { /* With KVM or HVF, '-cpu max' is identical to '-cpu host' */ @@ -799,57 +798,12 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); cpu->isar.id_aa64zfr0 =3D t; =20 - /* Replicate the same data to the 32-bit id registers. */ - u =3D cpu->isar.id_isar5; - u =3D FIELD_DP32(u, ID_ISAR5, AES, 2); /* AES + PMULL */ - u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 1); - u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 1); - u =3D FIELD_DP32(u, ID_ISAR5, CRC32, 1); - u =3D FIELD_DP32(u, ID_ISAR5, RDM, 1); - u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D u; - - u =3D cpu->isar.id_isar6; - u =3D FIELD_DP32(u, ID_ISAR6, JSCVT, 1); - u =3D FIELD_DP32(u, ID_ISAR6, DP, 1); - u =3D FIELD_DP32(u, ID_ISAR6, FHM, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SB, 1); - u =3D FIELD_DP32(u, ID_ISAR6, SPECRES, 1); - u =3D FIELD_DP32(u, ID_ISAR6, BF16, 1); - u =3D FIELD_DP32(u, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D u; - - u =3D cpu->isar.id_pfr0; - u =3D FIELD_DP32(u, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D u; - - u =3D cpu->isar.id_pfr2; - u =3D FIELD_DP32(u, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D u; - - u =3D cpu->isar.id_mmfr3; - u =3D FIELD_DP32(u, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D u; - - u =3D cpu->isar.id_mmfr4; - u =3D FIELD_DP32(u, ID_MMFR4, HPDS, 1); /* AA32HPD */ - u =3D FIELD_DP32(u, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - u =3D FIELD_DP32(u, ID_MMFR4, CNP, 1); /* TTCNP */ - u =3D FIELD_DP32(u, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D u; - t =3D cpu->isar.id_aa64dfr0; t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ cpu->isar.id_aa64dfr0 =3D t; =20 - u =3D cpu->isar.id_dfr0; - u =3D FIELD_DP32(u, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D u; - - u =3D cpu->isar.mvfr1; - u =3D FIELD_DP32(u, MVFR1, FPHP, 3); /* v8.2-FP16 */ - u =3D FIELD_DP32(u, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D u; + /* Replicate the same data to the 32-bit id registers. */ + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 9aa2f737c1..b0dbf2c991 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -20,6 +20,66 @@ #endif #include "cpregs.h" =20 + +/* Share AArch32 -cpu max features with AArch64. */ +void aa32_max_features(ARMCPU *cpu) +{ + uint32_t t; + + /* Add additional features supported by QEMU */ + t =3D cpu->isar.id_isar5; + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + cpu->isar.id_isar5 =3D t; + + t =3D cpu->isar.id_isar6; + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + cpu->isar.id_isar6 =3D t; + + t =3D cpu->isar.mvfr1; + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + cpu->isar.mvfr1 =3D t; + + t =3D cpu->isar.mvfr2; + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + cpu->isar.mvfr2 =3D t; + + t =3D cpu->isar.id_mmfr3; + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + cpu->isar.id_mmfr3 =3D t; + + t =3D cpu->isar.id_mmfr4; + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + cpu->isar.id_mmfr4 =3D t; + + t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + cpu->isar.id_pfr0 =3D t; + + t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + cpu->isar.id_pfr2 =3D t; + + t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + cpu->isar.id_dfr0 =3D t; +} + #ifndef CONFIG_USER_ONLY static uint64_t l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri) { @@ -994,7 +1054,6 @@ static void arm_v7m_class_init(ObjectClass *oc, void *= data) static void arm_max_initfn(Object *obj) { ARMCPU *cpu =3D ARM_CPU(obj); - uint32_t t; =20 /* aarch64_a57_initfn, advertising none of the aarch64 features */ cpu->dtb_compatible =3D "arm,cortex-a57"; @@ -1035,58 +1094,7 @@ static void arm_max_initfn(Object *obj) cpu->ccsidr[2] =3D 0x70ffe07a; /* 2048KB L2 cache */ define_cortex_a72_a57_a53_cp_reginfo(cpu); =20 - /* Add additional features supported by QEMU */ - t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); - t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); - cpu->isar.id_isar5 =3D t; - - t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); - cpu->isar.id_isar6 =3D t; - - t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ - cpu->isar.mvfr1 =3D t; - - t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ - cpu->isar.mvfr2 =3D t; - - t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ - cpu->isar.id_mmfr3 =3D t; - - t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ - cpu->isar.id_mmfr4 =3D t; - - t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); - cpu->isar.id_pfr0 =3D t; - - t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); - cpu->isar.id_pfr2 =3D t; - - t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ - cpu->isar.id_dfr0 =3D t; + aa32_max_features(cpu); =20 #ifdef CONFIG_USER_ONLY /* --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651386146114862.8625206319981; Sat, 30 Apr 2022 23:22:26 -0700 (PDT) Received: from localhost ([::1]:56760 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl2yO-0003IW-TC for importer@patchew.org; Sun, 01 May 2022 02:22:24 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43896) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2U1-00070Z-TZ for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:01 -0400 Received: from mail-pf1-x433.google.com ([2607:f8b0:4864:20::433]:40502) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2Tz-0001MT-Kf for qemu-devel@nongnu.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.57 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:57 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=Z9jnYlb3diHDx/Tz1NJJu7ooSfZI5A88/Vi2Hs36v6U=; b=RpW6KbtL31vMIKBUuiVZxCOCgaYNAr5q4Vm28J/nhs9Sf/dJBNagfXTnUy15P+L1bW Uhff7qI3Uisp5auVZa0SqRAzvmdkgei/O5jfeDHlRxqh8GzvZ7WhYSHvJJWWPMLoKmnc E/WOMaGdC7lYsoF+B8DfLgB9o/aZILMrRvLLJytoLEW9/G23P1B4LBRgD84p6HR6TIkx +NHtm7ho58AHORUJIMo3AC0yNy4YpBP9Gk4mClKH+Jwpxf5fWP4U1ysMMgg4ySLXkbFH 9RNfHcOp3XiTVafdyuBS3rr8081C9dPLN7VgSBTsPHIFOMQciy5hXUPuvtzmuQGFlb7Y ymdg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=Z9jnYlb3diHDx/Tz1NJJu7ooSfZI5A88/Vi2Hs36v6U=; b=R4xqi9WwJgbdoxflQk09e5cQaI5LA0Br0uqjqQrJvXBXe6T5UmQcUp4xAV3ysV2dSN hvKixHKdjmoYx/BTV/7TPz3rqOT9/bAVmg9yiVAHnueCM8PjbtLledZJrjcDQ5MJWUeb Lr9zp5ORWRLTYd1FW6nL8M5vP6TYddmydoXl0mEfenfOFWCXxfAJZvX5S/gbNk7UGFr/ Oel/FQMddqhHAfOgf3cVKvPERPU36Pq2VPlJCLKgCB+d6HBB5226zIVV46uSBEVaEefV gNjvKMQ66ChhOtSFCwdmenNbSJf623hPOPuE0L6rlQQA9jgnqWQ9aEAqJFm7v2l2KxCp TaLw== X-Gm-Message-State: AOAM5314jl3K4EfkNdK6E9Uz+jZEO7LPdM8vz0zhJm/Vs3vWurX3dLU/ 3YaUEnrXNe2iKuN9tyhygJxJSTeLZwbbBA== X-Google-Smtp-Source: ABdhPJyWIQlkk10t5IBsa8XbIbNEre5WNmGS9UPAXWDOj/ZIu0rGa4otpYPUtZg+yk6AYa0y4g390g== X-Received: by 2002:aa7:8256:0:b0:4e0:78ad:eb81 with SMTP id e22-20020aa78256000000b004e078adeb81mr6030846pfn.30.1651384258242; Sat, 30 Apr 2022 22:50:58 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 29/45] target/arm: Annotate arm_max_initfn with FEAT identifiers Date: Sat, 30 Apr 2022 22:50:11 -0700 Message-Id: <20220501055028.646596-30-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::433; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x433.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01, UPPERCASE_50_75=0.008 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651386147810100001 Content-Type: text/plain; charset="utf-8" Update the legacy feature names to the current names. Provide feature names for id changes that were not marked. Sort the field updates into increasing bitfield order. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu64.c | 100 +++++++++++++++++++++---------------------- target/arm/cpu_tcg.c | 48 ++++++++++----------- 2 files changed, 74 insertions(+), 74 deletions(-) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 6da42af56e..5fce40a6bc 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -713,51 +713,51 @@ static void aarch64_max_initfn(Object *obj) cpu->midr =3D t; =20 t =3D cpu->isar.id_aa64isar0; - t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* AES + PMULL */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* SHA512 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 2); /* FEAT_SHA512 */ t =3D FIELD_DP64(t, ID_AA64ISAR0, CRC32, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* v8.5-CondM */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ - t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR0, ATOMIC, 2); /* FEAT_LSE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 1); /* FEAT_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 1); /* FEAT_SM3 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 1); /* FEAT_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 1); /* FEAT_DotProd */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TS, 2); /* FEAT_FlagM2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, TLB, 2); /* FEAT_TLBIRANGE */ + t =3D FIELD_DP64(t, ID_AA64ISAR0, RNDR, 1); /* FEAT_RNG */ cpu->isar.id_aa64isar0 =3D t; =20 t =3D cpu->isar.id_aa64isar1; - t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); - t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); - t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* ARMv8.4-RCPC */ - t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); + t =3D FIELD_DP64(t, ID_AA64ISAR1, DPB, 2); /* FEAT_DPB2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FCMA, 1); /* FEAT_FCMA */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, LRCPC, 2); /* FEAT_LRCPC2 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, FRINTTS, 1); /* FEAT_FRINTTS */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 t =3D cpu->isar.id_aa64pfr0; + t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); - t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); + t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; - t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); - t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); + t =3D FIELD_DP64(t, ID_AA64PFR1, BT, 1); /* FEAT_BTI */ + t =3D FIELD_DP64(t, ID_AA64PFR1, SSBS, 2); /* FEAT_SSBS2 */ /* * Begin with full support for MTE. This will be downgraded to MTE=3D0 * during realize if the board provides no tag memory, much like * we do for EL2 with the virtualization=3Don property. */ - t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); + t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; @@ -769,37 +769,37 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64mmfr0 =3D t; =20 t =3D cpu->isar.id_aa64mmfr1; - t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* HPD */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* ATS1E1 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* VMID16 */ - t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VMIDBITS, 2); /* FEAT_VMID16 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, VH, 1); /* FEAT_VHE */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, HPDS, 1); /* FEAT_HPDS */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, LO, 1); /* FEAT_LOR */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, PAN, 2); /* FEAT_PAN2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR1, XNX, 1); /* FEAT_XNX */ cpu->isar.id_aa64mmfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr2; - t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); - t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* TTCNP */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* TTST */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ - t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2 */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, BBM, 2); /* FEAT_BBM at level 2= */ cpu->isar.id_aa64mmfr2 =3D t; =20 t =3D cpu->isar.id_aa64zfr0; t =3D FIELD_DP64(t, ID_AA64ZFR0, SVEVER, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* PMULL */ - t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); - t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); + t =3D FIELD_DP64(t, ID_AA64ZFR0, AES, 2); /* FEAT_SVE_PMULL128 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BITPERM, 1); /* FEAT_SVE_BitPerm */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, BFLOAT16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SHA3, 1); /* FEAT_SVE_SHA3 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, SM4, 1); /* FEAT_SVE_SM4 */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, I8MM, 1); /* FEAT_I8MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F32MM, 1); /* FEAT_F32MM */ + t =3D FIELD_DP64(t, ID_AA64ZFR0, F64MM, 1); /* FEAT_F64MM */ cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* v8.4-PMU */ + t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 /* Replicate the same data to the 32-bit id registers. */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b0dbf2c991..bc8f9d0edf 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -28,55 +28,55 @@ void aa32_max_features(ARMCPU *cpu) =20 /* Add additional features supported by QEMU */ t =3D cpu->isar.id_isar5; - t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); - t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); - t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); + t =3D FIELD_DP32(t, ID_ISAR5, AES, 2); /* FEAT_PMULL */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA1, 1); /* FEAT_SHA1 */ + t =3D FIELD_DP32(t, ID_ISAR5, SHA2, 1); /* FEAT_SHA256 */ t =3D FIELD_DP32(t, ID_ISAR5, CRC32, 1); - t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); - t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); + t =3D FIELD_DP32(t, ID_ISAR5, RDM, 1); /* FEAT_RDM */ + t =3D FIELD_DP32(t, ID_ISAR5, VCMA, 1); /* FEAT_FCMA */ cpu->isar.id_isar5 =3D t; =20 t =3D cpu->isar.id_isar6; - t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); - t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); - t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); - t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); - t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); - t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); + t =3D FIELD_DP32(t, ID_ISAR6, JSCVT, 1); /* FEAT_JSCVT */ + t =3D FIELD_DP32(t, ID_ISAR6, DP, 1); /* Feat_DotProd */ + t =3D FIELD_DP32(t, ID_ISAR6, FHM, 1); /* FEAT_FHM */ + t =3D FIELD_DP32(t, ID_ISAR6, SB, 1); /* FEAT_SB */ + t =3D FIELD_DP32(t, ID_ISAR6, SPECRES, 1); /* FEAT_SPECRES */ + t =3D FIELD_DP32(t, ID_ISAR6, BF16, 1); /* FEAT_AA32BF16 */ + t =3D FIELD_DP32(t, ID_ISAR6, I8MM, 1); /* FEAT_AA32I8MM */ cpu->isar.id_isar6 =3D t; =20 t =3D cpu->isar.mvfr1; - t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* v8.2-FP16 */ - t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* v8.2-FP16 */ + t =3D FIELD_DP32(t, MVFR1, FPHP, 3); /* FEAT_FP16 */ + t =3D FIELD_DP32(t, MVFR1, SIMDHP, 2); /* FEAT_FP16 */ cpu->isar.mvfr1 =3D t; =20 t =3D cpu->isar.mvfr2; - t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ - t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ + t =3D FIELD_DP32(t, MVFR2, SIMDMISC, 3); /* SIMD MaxNum */ + t =3D FIELD_DP32(t, MVFR2, FPMISC, 4); /* FP MaxNum */ cpu->isar.mvfr2 =3D t; =20 t =3D cpu->isar.id_mmfr3; - t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* ATS1E1 */ + t =3D FIELD_DP32(t, ID_MMFR3, PAN, 2); /* FEAT_PAN2 */ cpu->isar.id_mmfr3 =3D t; =20 t =3D cpu->isar.id_mmfr4; - t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* AA32HPD */ - t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ - t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* TTCNP */ - t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* TTS2UXN */ + t =3D FIELD_DP32(t, ID_MMFR4, HPDS, 1); /* FEAT_AA32HPD */ + t =3D FIELD_DP32(t, ID_MMFR4, AC2, 1); /* ACTLR2, HACTLR2 */ + t =3D FIELD_DP32(t, ID_MMFR4, CNP, 1); /* FEAT_TTCNP */ + t =3D FIELD_DP32(t, ID_MMFR4, XNX, 1); /* FEAT_XNX*/ cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; - t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); + t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; - t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); + t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* v8.4-PMU */ + t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651388955541851.9154722067908; Sun, 1 May 2022 00:09:15 -0700 (PDT) Received: from localhost ([::1]:54938 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3hi-0007t8-0E for importer@patchew.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:58 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=qbh2KrYpsf5bd2gq07XULYnsZ3c1pnWPBFUbrKfWACk=; b=GfYoNQGYhO9BREdXE5ZBliAovdNBBuUSGrf4ggj/sjXsGD/DGXDM7FfNZYvMqRgzNw 0M/N4JijmUhN1eDqvGC59bcoGCsw032ufa/QQMRrQthmK3lC4uduqYVA/tPoUAf5HAxt VmtC76oe0vCtVFW8NE/MV1ZXCNhhTfEEcoPKFw6T5cn5kiIvDbRyxSukQW/Pr5MwzO8K G62g/CTAd6e6QOWfi/Grw2IS8sgI4fthtBl89rhXz9Of4BM9AegXKV1mhk2My4DSKVKH c8JdxPHlMoD5dW4r2/ZUxAaI6ZeswVNHQi2EXK7idlHkUstWnxCxzqQmDspmMcNHYV35 Uycg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=qbh2KrYpsf5bd2gq07XULYnsZ3c1pnWPBFUbrKfWACk=; b=yr0YjyHszKawNDBCCib1NNB4h2XDAhznqGEqtJvruX86rrPyBi5sBUGO8GhPFFn+eo dFHdjE+oDQSJSnHYoIYHKNwBNY07pL/r9zWhLQ6eh25OyHkc14V7PlbXyxlipixPniuW uwMCRZuFNmQPrcdz1z4WVXbGNCn7aUGXlHKdwho3pdbPloLdyM7mbYfrLQGIuK6jQwxp spWt+xJaXHO9wexCfY/4cyj7KY/J+jjLzxXC6wmyn8UfuIcw+Hh7W2J4pCnQUEcbYu/u Axx5uGfibb4edeBL6XNWfMnaM+VLoeU6XwET8bXZOMy2c42eFzT3Prqp/U+gLCslHaQS kheQ== X-Gm-Message-State: AOAM533kuy80GHk6BmBpktFINZ6Em5C7Uvsd6WVKtMAocbnPVxjn+rkq lfoMNzIli62wS5SnujXZCJvFZoZz8Q1baQ== X-Google-Smtp-Source: ABdhPJwxK3enN1hEjZ91/Ec4U3lMz+Cg73hbNMQErHLXPbpucK4Zo74Q0jXn/SPUaU685091wSY9JA== X-Received: by 2002:a17:902:d48a:b0:15e:a142:a9e8 with SMTP id c10-20020a170902d48a00b0015ea142a9e8mr552466plg.129.1651384259104; Sat, 30 Apr 2022 22:50:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 30/45] target/arm: Use field names for manipulating EL2 and EL3 modes Date: Sat, 30 Apr 2022 22:50:12 -0700 Message-Id: <20220501055028.646596-31-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388956374100001 Content-Type: text/plain; charset="utf-8" Use FIELD_DP{32,64} to manipulate id_pfr1 and id_aa64pfr0 during arm_cpu_realizefn. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.c | 22 +++++++++++++--------- 1 file changed, 13 insertions(+), 9 deletions(-) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 6e8b39dc9e..1b509bbd2a 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1799,11 +1799,13 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) */ unset_feature(env, ARM_FEATURE_EL3); =20 - /* Disable the security extension feature bits in the processor fe= ature - * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12= ]. + /* + * Disable the security extension feature bits in the processor + * feature registers as well. */ - cpu->isar.id_pfr1 &=3D ~0xf0; - cpu->isar.id_aa64pfr0 &=3D ~0xf000; + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL3, 0); } =20 if (!cpu->has_el2) { @@ -1834,12 +1836,14 @@ static void arm_cpu_realizefn(DeviceState *dev, Err= or **errp) } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { - /* Disable the hypervisor feature bits in the processor feature - * registers if we don't have EL2. These are id_pfr1[15:12] and - * id_aa64pfr0_el1[11:8]. + /* + * Disable the hypervisor feature bits in the processor feature + * registers if we don't have EL2. */ - cpu->isar.id_aa64pfr0 &=3D ~0xf00; - cpu->isar.id_pfr1 &=3D ~0xf000; + cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, + ID_AA64PFR0, EL2, 0); + cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, + ID_PFR1, VIRTUALIZATION, 0); } =20 #ifndef CONFIG_USER_ONLY --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651389235730395.44140694077305; Sun, 1 May 2022 00:13:55 -0700 (PDT) Received: from localhost ([::1]:60170 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3mE-000391-OO for importer@patchew.org; Sun, 01 May 2022 03:13:54 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43962) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2U5-00071s-S1 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:08 -0400 Received: from mail-pl1-x62d.google.com ([2607:f8b0:4864:20::62d]:35797) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U1-0001NG-A3 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:02 -0400 Received: by mail-pl1-x62d.google.com with SMTP id d15so10294156plh.2 for ; Sat, 30 Apr 2022 22:51:00 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.50.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:50:59 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=LoFkNZI0EPN3UHmsZdxsDTn+j+LzMoee7yMTRcYWMTM=; b=JXF4y4NSINpr1sepl2M9ZPwPVaPLbNDyacnsWZjWlkmmQCNQ7tbyG+bt7JRrN15THj XrnWCkHFE0HQsfnFYLw0XjcRXw1r343JZSabBam98PuNCfWtnRxuumyCVZbDdLK3e2t3 NDTvafGLPBGwjwAG0t3p+BZJEbKZj5SeXq5/VJ3AODGyQKgV09Xl5EECQdh2f3sse2Hx ROKUfBh7KUHr67e3gPdiixfCCH09MYuTnhfk9a+2pZvI1OPMEB+p/rjrxpXQpDN1KsR+ luBDUXh+xuCo7OKNj0356y9sIzC4ansxOVvPXwbiWZKJCj6hvMCoph0+qZ2w4wDrtAVt +Cog== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=LoFkNZI0EPN3UHmsZdxsDTn+j+LzMoee7yMTRcYWMTM=; b=QbUHTAnjkJsNiyRuamzXXBwohgxbQ/QsW3W0fq1rPdJAzigOPpstvqSMTil3h9Od6I c4x/xLm8WaDzjVm9dSLqZwUnYpK87c6nyeBabjyiU7QsBctL1a4/eRQJ1k7Tn2ir4UV3 Qy1TCdwwXmgxczdhXKShAsUEVPHy6G1LNs0eiwD3K068ZWa7P3AW4wh3zX4fBtJmdERe CqNrFhQhgJlQ5qwGV6SxZbxg2j0gj469vykovuoNTs/M97BaWogfb9hzhkRMTQfHPa/3 fkyQ07svu38QfH+UFpJ0g5Mog3H/oSR+Unhl7qiadz8XtKBQFQJhbm+Bb/8BQWUqQuF9 ruqg== X-Gm-Message-State: AOAM530E+CovqIJloUjBVcQVdTd4N0BzbgP91HVqdwSRBQn2rFzl4x8O h0ENNjgtOPjWiJS+RmxApxKiCf7krHrxSA== X-Google-Smtp-Source: ABdhPJyhTzLHYE81L3el6GXkf88zFc5U8r+uQNFYAElFh4d3rGcaASvxruWU6txX31r45PtGq8xHkA== X-Received: by 2002:a17:90b:688:b0:1d9:9ddd:1f71 with SMTP id m8-20020a17090b068800b001d99ddd1f71mr11918311pjz.207.1651384259960; Sat, 30 Apr 2022 22:50:59 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 31/45] target/arm: Enable FEAT_Debugv8p2 for -cpu max Date: Sat, 30 Apr 2022 22:50:13 -0700 Message-Id: <20220501055028.646596-32-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62d; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62d.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651389237596100001 Content-Type: text/plain; charset="utf-8" The only portion of FEAT_Debugv8p2 that is relevant to QEMU is CONTEXTIDR_EL2, which is also conditionally implemented with FEAT_VHE. The rest of the debug extension concerns the External debug interface, which is outside the scope of QEMU. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu.c | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 2 ++ 4 files changed, 5 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index c3bd0676a8..965f35d8c9 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -14,6 +14,7 @@ the following architecture extensions: - FEAT_BTI (Branch Target Identification) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) +- FEAT_Debugv8p2 (Debug changes for v8.2) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 1b509bbd2a..97b6f9f68c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1804,6 +1804,7 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) * feature registers as well. */ cpu->isar.id_pfr1 =3D FIELD_DP32(cpu->isar.id_pfr1, ID_PFR1, SECUR= ITY, 0); + cpu->isar.id_dfr0 =3D FIELD_DP32(cpu->isar.id_dfr0, ID_DFR0, COPSD= BG, 0); cpu->isar.id_aa64pfr0 =3D FIELD_DP64(cpu->isar.id_aa64pfr0, ID_AA64PFR0, EL3, 0); } diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 5fce40a6bc..202fd5c46e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -799,6 +799,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index bc8f9d0edf..b6fc3752f2 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,6 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387170199591.3317363790462; Sat, 30 Apr 2022 23:39:30 -0700 (PDT) Received: from localhost ([::1]:45758 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3Es-00070X-Mn for importer@patchew.org; Sun, 01 May 2022 02:39:26 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:43980) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2U6-00071x-M0 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:08 -0400 Received: from mail-pg1-x531.google.com ([2607:f8b0:4864:20::531]:34643) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U3-0001PI-Tg for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:06 -0400 Received: by mail-pg1-x531.google.com with SMTP id z21so9509726pgj.1 for ; Sat, 30 Apr 2022 22:51:01 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.00 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=NgxsvnW311osB1m0PaTzB1/zyzTpUBL9MpOPjCAC0zA=; b=rUOWgaS4vwR8VVvkrEvuhKIa7e1UdDZddaGjJek5fnPe9pFwWKkBWiX91H1aqAKuc4 o+akn8esQQieNVMXFK2q/Jnoz2PoKtrFlI3XW79A4aJbllbo9DR6Ug3FFs/mpbbFr/hL 2k/+T9gqGKgE26fBhoyMts2ZGfjtZZEaTI1PuUHrvpIBiH9tlMNEZ8gK/MKQ/OXnCgG2 qEP8SEUUokr1aFMQeg3FmdjsF8v41DWyTsTm6OuXa/WsKLuKerTKd6BXZ9iACgwHT81z +RqVR6gcls8C6KP7X97HMaApkflDjN7FINGLIcrQngBRFkGU7FvuSCJ+i+MPLwhu3bFD 6bNA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=NgxsvnW311osB1m0PaTzB1/zyzTpUBL9MpOPjCAC0zA=; b=hpKFSwbkMiAWiHHlpiNuDmtr959NaqyjZUx2QUumFqVpQI4fQk+33TQxuoydReJ4Ed 0mmYvHhycff91XtkHcvPNyNQGqemBTWiUblRssnXXx2LBI4I2jV4TbB91byB8SLyCz37 fkdbLRC2pl29VtKexf9GJ2TtWaVE+EIhppPYdTE9mb9YoJTuJYrHWwE9CBf5QHbITT4g vc1CZHFUO9Rn9yTQXnIm4KpcGCSFFt/WKvKa/HAG8LB4SMh2hIdK0MXNTq+TlR/7LU1K +WTmL6nf94TT90XbGPoPuX7PKnBFJUrucs0Fon0C7NR5n+oHlnMnz8uoiR++P1c6n007 oV1g== X-Gm-Message-State: AOAM533OGf8ADmTHvNn8u+tnrXnL3TkM58zrxWokE/KOHHRlXJ9JGTxx j7jI+bKMqImkZh4t9b/ZYop7H3rul5FoJQ== X-Google-Smtp-Source: ABdhPJwg6m66RLxQ4Gyr6mbBR3MdFxtklTRzox96eIpkMJStFVWE901OF82IAykbvEMSfFUuU7txCw== X-Received: by 2002:a62:170b:0:b0:50a:6901:b633 with SMTP id 11-20020a62170b000000b0050a6901b633mr6221375pfx.34.1651384260981; Sat, 30 Apr 2022 22:51:00 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 32/45] target/arm: Enable FEAT_Debugv8p4 for -cpu max Date: Sat, 30 Apr 2022 22:50:14 -0700 Message-Id: <20220501055028.646596-33-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::531; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x531.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651387171168100001 Content-Type: text/plain; charset="utf-8" This extension concerns changes to the External Debug interface, with Secure and Non-secure access to the debug registers, and all of it is outside the scope of QEMU. Indicating support for this is mandatory with FEAT_SEL2, which we do implement. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 2 +- target/arm/cpu_tcg.c | 4 ++-- 3 files changed, 4 insertions(+), 3 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 965f35d8c9..0acac6347c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -15,6 +15,7 @@ the following architecture extensions: - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) +- FEAT_Debugv8p4 (Debug changes for v8.4) - FEAT_DotProd (Advanced SIMD dot product instructions) - FEAT_FCMA (Floating-point complex number instructions) - FEAT_FHM (Floating-point half-precision multiplication instructions) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 202fd5c46e..88d3cef93e 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -799,7 +799,7 @@ static void aarch64_max_initfn(Object *obj) cpu->isar.id_aa64zfr0 =3D t; =20 t =3D cpu->isar.id_aa64dfr0; - t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP64(t, ID_AA64DFR0, DEBUGVER, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP64(t, ID_AA64DFR0, PMUVER, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_aa64dfr0 =3D t; =20 diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index b6fc3752f2..337598e949 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -76,8 +76,8 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr2 =3D t; =20 t =3D cpu->isar.id_dfr0; - t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 8); /* FEAT_Debugv8p2 */ - t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 8); /* FEAT_Debugv8p2 */ + t =3D FIELD_DP32(t, ID_DFR0, COPDBG, 9); /* FEAT_Debugv8p4 */ + t =3D FIELD_DP32(t, ID_DFR0, COPSDBG, 9); /* FEAT_Debugv8p4 */ t =3D FIELD_DP32(t, ID_DFR0, PERFMON, 5); /* FEAT_PMUv3p4 */ cpu->isar.id_dfr0 =3D t; } --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387479143935.7397463596932; Sat, 30 Apr 2022 23:44:39 -0700 (PDT) Received: from localhost ([::1]:52354 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3Jt-0003LN-Mm for importer@patchew.org; Sun, 01 May 2022 02:44:37 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44036) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2U8-00072H-Lp for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:09 -0400 Received: from mail-pj1-x1036.google.com ([2607:f8b0:4864:20::1036]:52772) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U4-0001Pr-Qy for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:07 -0400 Received: by mail-pj1-x1036.google.com with SMTP id e24so10351328pjt.2 for ; Sat, 30 Apr 2022 22:51:02 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:01 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=eLmL8OHUPXIjo0sXAU8FjVln9l2ooq2J7ROpHXXZtis=; b=aRyFtQqnrJwkTfdumlf2aIP22ZbTQ6UdyAedj3ff7clHfnu3Y/xgxR9OODXH0IsKu5 Akdvs/L2pudrastpqibBlXi9FB8yu2iAZzdVyGN+slj6Z157Kq0NcMMP6ZiUe1l+49kl 4YBMs+ghtv4ckHPZkYYU+nwwcOodnFurakoissllOiGf88T6gQOgccqSve+MssB/Paem PSg7W8z2V/gjY6k4Bhs6HMWyJ7LpXFPJioW8/DGLBOTapF7dZ18CUgV+SCTW1Dtmd3+M 9SSbb6o3x2IzJwLJ5tfJ4UzaQ9BP6Zh5jjr/BeDDMKcEn6sGkaHmyrcT6Bqn0s22PVV4 eHvQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=eLmL8OHUPXIjo0sXAU8FjVln9l2ooq2J7ROpHXXZtis=; b=L8qQRsfatY6ExenbAi3aHZvdE0NJmjQYCg1canPBoEst/KL2oNv2F9MuOaf4tVzvUy CnLpZBszVpF8w0kz9iitAAEQJN22q4HW9IvnlXri0UDvXFdh842jA/pwWv+8+pRO5Use 4MOT9LdiGTRJgKSvw2OnldDvfVBs3J3/BBarisRYXK6ZGcKxTcQHUFcLfiY8p5RWGDR/ gFlF7/iAjZ2v7gyNvy9sMHMKZR5lk4Z/U0zCI5VddR+kvpcuLG04wDs0u2pPt48kz9sA XamfnWDfv+BzakXLrMTlKETjVMw+Dy5TQ62Q1728alccQXPorpOoy7h74zRx3/zSwWya tlZg== X-Gm-Message-State: AOAM531A4fEWV84hnJ6CJwWVW5DLHdv9wlCMIf99Yiu04/3OFvYK/sLD ajZaalVzHh8PVpFWRMykO7uckn8+vS4Fqg== X-Google-Smtp-Source: ABdhPJwuoWowyC2tn9/9nqLxuM6kgsDJvlc4zYuIfrHOTPydPpQLC/x/GLlWYwnYsu/5jZPILUXXfw== X-Received: by 2002:a17:90b:4d0c:b0:1d9:aee3:fac1 with SMTP id mw12-20020a17090b4d0c00b001d9aee3fac1mr12283101pjb.15.1651384261966; Sat, 30 Apr 2022 22:51:01 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 33/45] target/arm: Add isar_feature_{aa64,any}_ras Date: Sat, 30 Apr 2022 22:50:15 -0700 Message-Id: <20220501055028.646596-34-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1036; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1036.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651387480803100001 Content-Type: text/plain; charset="utf-8" Add the aa64 predicate for detecting RAS support from id registers. We already have the aa32 version from the M-profile work. Add the 'any' predicate for testing both aa64 and aa32. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/cpu.h | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 7303103016..ca01f909a8 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -3886,6 +3886,11 @@ static inline bool isar_feature_aa64_aa32_el1(const = ARMISARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, EL1) >=3D 2; } =20 +static inline bool isar_feature_aa64_ras(const ARMISARegisters *id) +{ + return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, RAS) !=3D 0; +} + static inline bool isar_feature_aa64_sve(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, SVE) !=3D 0; @@ -4108,6 +4113,11 @@ static inline bool isar_feature_any_debugv8p2(const = ARMISARegisters *id) return isar_feature_aa64_debugv8p2(id) || isar_feature_aa32_debugv8p2(= id); } =20 +static inline bool isar_feature_any_ras(const ARMISARegisters *id) +{ + return isar_feature_aa64_ras(id) || isar_feature_aa32_ras(id); +} + /* * Forward to the above feature tests given an ARMCPU pointer. */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651389701; cv=none; d=zohomail.com; s=zohoarc; b=k/pyU0s+cMN3QVAlwxAdIdFw81QT99U2JpoIypWn68snHOd4Iy/ippIs40xMggcLassoKpTzRdNrhCjggwM12ZvIJWWg8Y9WXHUkInClziBYTVIhkavkkJEyhi7Vr0p+sd1K5Qe43gc6uACaqzuPuKbG9kpSFWQj6Xgnnxtt47U= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651389701; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=OgK/bg8qfHwwWTHPP3NZqw3YdheAlsDilvaD2LibWrI=; b=Fv9z+chHlmA5LBjL+yXKSyikR8q3Qll1KG61uSFBsh1A3zpryXM4vTCUJag3os0kpM7jOXe8piiDbippdUf90TaSXuFeUmN95y9Lh/DdBLtytI0fuhuZhgLiPyvpLqhhoxVY5z+PDeYqhBSr2baISmy3K+hSq9UfIo97arNAwiU= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651389701801400.3631478472274; Sun, 1 May 2022 00:21:41 -0700 (PDT) Received: from localhost ([::1]:42506 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3tk-0001v2-HR for importer@patchew.org; Sun, 01 May 2022 03:21:40 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44190) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2UD-00077o-Aw for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:14 -0400 Received: from mail-pf1-x42c.google.com ([2607:f8b0:4864:20::42c]:45763) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U8-0001Q6-Gu for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:12 -0400 Received: by mail-pf1-x42c.google.com with SMTP id h1so10049743pfv.12 for ; Sat, 30 Apr 2022 22:51:03 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.02 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:02 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=OgK/bg8qfHwwWTHPP3NZqw3YdheAlsDilvaD2LibWrI=; b=U1Y6ZakEi2LMpP+oP/YCAbXEpQ97pTuP2QGD8C3UeDqqeWqk6IwK76XqfSV8uZViKH GWPfY0bW4IEd4KdqDl+uvhWsDQ7D5Rr+/TWiPDJKh16788mcMczsjJkbuVO35KC1CWHX fQOHweNFWbctlp62jf01/mQIiIVkR1MQEM7nrTUbMmaW2HRoHtASd+fojhB4jpPRwwA3 d6hJ88BwkfFoyBjhQVdmhG6KOaHU5kgdWbYzYqwKcpejiTM47NwSB003PnpVHNkQKAuI +T0cyUBnKi9jc7so4Ij1v1Ey77K6JvF8dGTk6bnDak6glhOsqF5+ASvdG+3WCIxNL8cL HGaA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=OgK/bg8qfHwwWTHPP3NZqw3YdheAlsDilvaD2LibWrI=; b=ZYncZu1IPoe1DzHKvYIBgXiRwcNO6k0lbsXFjs2aRiI1lUkq0NZL+BUZzlOVy5zL18 TBGFW+/hJnMrn3JBXGzawEkkjec0iq/PiZOEu8dWrwtQWt1bMeflicHWKyFV9pkRKpIm ArhCJzGMFViS3lfXTE1Nsk/skU6p+2hlQR3aTwHDrPW9KZee8cE9wIv+zsTuiSUJjU+q P48kJXBfn56lwGtdorEQYSXl4Bj5sHyoCQscWWwQULEuotmsSFloKL9HaL4oum4QU7nN cb4Hn2PVty25fblYAe9tNc47g5sQG4SSItHaPIhzlqIZssxbeEXojCnHKWg1BnUITIWd vr6g== X-Gm-Message-State: AOAM530wlfNc4EKE/YGnlmXXNeB55PjmCTQexh9120htI7qwGmh05bYB h63vD3UXKPtVNBX9BwIVfDkxozwk47eaLQ== X-Google-Smtp-Source: ABdhPJyDcpTH426kyAZvISppDWnGV66rO6ILf0UkuDuEJGEIjUrRbi9/ceBk6/GML21bsBBd1DQKHA== X-Received: by 2002:a05:6a00:98b:b0:50d:ac70:c39a with SMTP id u11-20020a056a00098b00b0050dac70c39amr6112590pfg.25.1651384262943; Sat, 30 Apr 2022 22:51:02 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 34/45] target/arm: Add minimal RAS registers Date: Sat, 30 Apr 2022 22:50:16 -0700 Message-Id: <20220501055028.646596-35-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::42c; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x42c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651389703942100001 Content-Type: text/plain; charset="utf-8" Add only the system registers required to implement zero error records. This means we need to save state for ERRSELR, but all values are out of range, so none of the indexed error record registers need be implemented. Add the EL2 registers required for injecting virtual SError. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Leave ERRSELR_EL1 undefined. v3: Rely on EL3-no-EL2 squashing during registration. --- target/arm/cpu.h | 5 +++ target/arm/helper.c | 84 +++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 89 insertions(+) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index ca01f909a8..a55980d66d 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -525,6 +525,11 @@ typedef struct CPUArchState { uint64_t tfsr_el[4]; /* tfsre0_el1 is index 0. */ uint64_t gcr_el1; uint64_t rgsr_el1; + + /* Minimal RAS registers */ + uint64_t disr_el1; + uint64_t vdisr_el2; + uint64_t vsesr_el2; } cp15; =20 struct { diff --git a/target/arm/helper.c b/target/arm/helper.c index a5741e0ad7..b4bdd4a4a6 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -5980,6 +5980,87 @@ static const ARMCPRegInfo debug_lpae_cp_reginfo[] = =3D { .access =3D PL0_R, .type =3D ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = =3D 0 }, }; =20 +/* + * Check for traps to RAS registers, which are controlled + * by HCR_EL2.TERR and SCR_EL3.TERR. + */ +static CPAccessResult access_terr(CPUARMState *env, const ARMCPRegInfo *ri, + bool isread) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_TERR)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_TERR)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static uint64_t disr_read(CPUARMState *env, const ARMCPRegInfo *ri) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + return env->cp15.vdisr_el2; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return 0; /* RAZ/WI */ + } + return env->cp15.disr_el1; +} + +static void disr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t = val) +{ + int el =3D arm_current_el(env); + + if (el < 2 && (arm_hcr_el2_eff(env) & HCR_AMO)) { + env->cp15.vdisr_el2 =3D val; + return; + } + if (el < 3 && (env->cp15.scr_el3 & SCR_EA)) { + return; /* RAZ/WI */ + } + env->cp15.disr_el1 =3D val; +} + +/* + * Minimal RAS implementation with no Error Records. + * Which means that all of the Error Record registers: + * ERXADDR_EL1 + * ERXCTLR_EL1 + * ERXFR_EL1 + * ERXMISC0_EL1 + * ERXMISC1_EL1 + * ERXMISC2_EL1 + * ERXMISC3_EL1 + * ERXPFGCDN_EL1 (RASv1p1) + * ERXPFGCTL_EL1 (RASv1p1) + * ERXPFGF_EL1 (RASv1p1) + * ERXSTATUS_EL1 + * and + * ERRSELR_EL1 + * may generate UNDEFINED, which is the effect we get by not + * listing them at all. + */ +static const ARMCPRegInfo minimal_ras_reginfo[] =3D { + { .name =3D "DISR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL1_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.disr= _el1), + .readfn =3D disr_read, .writefn =3D disr_write, .raw_writefn =3D raw= _write }, + { .name =3D "ERRIDR_EL1", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 5, .crm =3D 3, .opc2 =3D 0, + .access =3D PL1_R, .accessfn =3D access_terr, + .type =3D ARM_CP_CONST, .resetvalue =3D 0 }, + { .name =3D "VDISR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 12, .crm =3D 1, .opc2 =3D 1, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vdis= r_el2) }, + { .name =3D "VSESR_EL2", .state =3D ARM_CP_STATE_BOTH, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 5, .crm =3D 2, .opc2 =3D 3, + .access =3D PL2_RW, .fieldoffset =3D offsetof(CPUARMState, cp15.vses= r_el2) }, +}; + /* Return the exception level to which exceptions should be taken * via SVEAccessTrap. If an exception should be routed through * AArch64.AdvSIMDFPAccessTrap, return 0; fp_exception_el should @@ -8214,6 +8295,9 @@ void register_cp_regs_for_features(ARMCPU *cpu) if (cpu_isar_feature(aa64_ssbs, cpu)) { define_one_arm_cp_reg(cpu, &ssbs_reginfo); } + if (cpu_isar_feature(any_ras, cpu)) { + define_arm_cp_regs(cpu, minimal_ras_reginfo); + } =20 if (cpu_isar_feature(aa64_vh, cpu) || cpu_isar_feature(aa64_debugv8p2, cpu)) { --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651387752201650.4828364127088; Sat, 30 Apr 2022 23:49:12 -0700 (PDT) Received: from localhost ([::1]:58852 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3OI-0007oX-LO for importer@patchew.org; Sun, 01 May 2022 02:49:10 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44126) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2UB-000771-4G for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:13 -0400 Received: from mail-pg1-x52f.google.com ([2607:f8b0:4864:20::52f]:33675) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U8-0001QE-CH for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:10 -0400 Received: by mail-pg1-x52f.google.com with SMTP id k14so9534269pga.0 for ; Sat, 30 Apr 2022 22:51:04 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=0WvXcqJE+bSJxjY0PJJiNeF+EUgDHhL7U//iKcka87g=; b=WjSJ8SGhGuV0j3T/FqKFlwFd86Omn0G872y3B0J6WEsSHHidU0l5Z36rJBRZ2JtcY3 JjPKtHTwe5O+F4R03uM4H/97PP24ibTky4Sk99vn/yfD6lEKPKul8BsekHRPXohS6n3Q oopRdqh1RlLTZfOUF8ME3uQbaof2U3eArWSUbbiUzCOZHYMUaJVqgCp65o3p+QNw9wHa EVJOjLY1s5Woq/qmu5vnEAP0D5Ivscgi10O7uqbBdc36lxAdcGkm22+x7i+mad7Rqu8p WA0zXzO5vARiIf0rjacORF+9FldOTNiLCnsW/YfrXeU4P9HdaxqUy/lbV85yZOb4hoMv 5ofw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=0WvXcqJE+bSJxjY0PJJiNeF+EUgDHhL7U//iKcka87g=; b=xG6ge0fa/jnnis1v+SyZgxyxgW0mPYq29kgHAETjo+x8x0f1qyEZxFlRu3fs/bkIzB raW1NI1lLFa2bS2HaMvnMczxJxFSEO/OGrJJgFDH+naJld6sytmqb1C7//thbVpetGdn J1il7iBDPHnu2sfemgCNxdBpFbTUeDM3EDY2MakRi4Vwi/BFkrXyfa17Lx7zazp2yO/Q Q8oJmkz2SZfWa2Dem9J5N7Fz2slcYfHKdV1wq1MNS81AfCvKpS5ViR+Xhln+7ypJLJuH ZQ6nezkwFjKlBoa+3OC7Be7PGAKxlrwUGyEagJL87CbZf/oBDTca4cOmX3ji87GbD4bf kS9g== X-Gm-Message-State: AOAM533aXAMZ0XydeakkMj4LqT+GVzRfPc1+ipaG3BirIlVayzJaoyee Ij4GL/MUXTmdDFoBsmq1ojUFxEAWPlzT8g== X-Google-Smtp-Source: ABdhPJz4fwXm9akcYbal7diaG5yya1XisyeutTFDcLIMheKtG0W2GedMtsaLNAPYxJHmQg2/a+LFFg== X-Received: by 2002:a05:6a00:23c4:b0:50d:e8b0:6108 with SMTP id g4-20020a056a0023c400b0050de8b06108mr74455pfc.76.1651384263779; Sat, 30 Apr 2022 22:51:03 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 35/45] target/arm: Enable SCR and HCR bits for RAS Date: Sat, 30 Apr 2022 22:50:17 -0700 Message-Id: <20220501055028.646596-36-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651387754014100003 Content-Type: text/plain; charset="utf-8" Enable writes to the TERR and TEA bits when RAS is enabled. These bits are otherwise RES0. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- target/arm/helper.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/helper.c b/target/arm/helper.c index b4bdd4a4a6..f6f26766e2 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1755,6 +1755,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } valid_mask &=3D ~SCR_NET; =20 + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D SCR_TLOR; } @@ -1769,6 +1772,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); + if (cpu_isar_feature(aa32_ras, cpu)) { + valid_mask |=3D SCR_TERR; + } } =20 if (!arm_feature(env, ARM_FEATURE_EL2)) { @@ -5126,6 +5132,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_vh, cpu)) { valid_mask |=3D HCR_E2H; } + if (cpu_isar_feature(aa64_ras, cpu)) { + valid_mask |=3D HCR_TERR | HCR_TEA; + } if (cpu_isar_feature(aa64_lor, cpu)) { valid_mask |=3D HCR_TLOR; } --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651388553357706.5077693997238; Sun, 1 May 2022 00:02:33 -0700 (PDT) Received: from localhost ([::1]:48298 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3bD-0003JE-Rk for importer@patchew.org; Sun, 01 May 2022 03:02:31 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44148) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2UB-00077K-Jz for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:13 -0400 Received: from mail-pl1-x631.google.com ([2607:f8b0:4864:20::631]:35801) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U8-0001QO-Ce for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:11 -0400 Received: by mail-pl1-x631.google.com with SMTP id d15so10294207plh.2 for ; Sat, 30 Apr 2022 22:51:05 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=cjC+raRYUVGl1NEdZAPsvtNYW3ffrw4dDRtiXLYvqcI=; b=Wd6ykq4ImefzVLd2MTs6iTXYPmdJ8q6rbOfC8LC7PC/PspH7/it9Ldq7fhlCqYsKcI UXWC13jaDgX3uqLNxR64rt2FIhaBSn3nk70yQ0GdjfRXPTxS5ilDl7fCYtg2pFhutC2d mXDMn+7woKpiccH2e8rOhuelwqTN+S5sq/TjAHlTnodyVdu/SAy7IipMjxPdaSQiTlSi 7C3C50qMFKNgWV1lAsBXazFWetwS7pyQ5yHdAAiWr+2qpjLzYyo5aEZ2VKPF57FSFyOx NoshOdAQV20h4Fhl6cZ/5Vo43VjGZfVKyCkupJQrVSVAhKv2ylbxKIWkAYAR2popCAbv tt/A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=cjC+raRYUVGl1NEdZAPsvtNYW3ffrw4dDRtiXLYvqcI=; b=b+TaG2WlKjZCqIUhlxue8ffrz6lZIiv49qot2PUWVvqv+K33H+DFiZXRKiF5MnIcSq k/yTy8wSvWS0jeBvlZVEaKurEy3qAZMajc7gAMwe4pLn4SVOZyOiTOSEx5aZZx7Nj/3X xj7J9XmTeV970oPCKMpiA2Qs5qgDPWcHdAePZhwLCY088Zs2wd7AFwmhK1poFJrCRe/p X7KG8EZqwa0w0QSYa+dY8Oe5WNtNZ6zAQ2CbeufGt05RFFTrntrqcptiNciqSlketz55 OvFfBDo1zqkFf7l1bHxAwHsQ6v8UPj8rW9+c7LnGp7k5Ia/py78mmGsIW+TWwsAZ2BDi V2EA== X-Gm-Message-State: AOAM530/mcuRlb4Ap8BokSZ6QoFctwsZg2udf+Pm47XcFcx30peplk/R CS5V8loMZfsHp/jRb3D+Wygz9Mf9N3knzQ== X-Google-Smtp-Source: ABdhPJx5T+31xMim7eF4/HetpU6JsCKTqwnnAPcym8Ysve2FY/QPsmTPyq2TZ8LOjBJVYOdcTqrBqg== X-Received: by 2002:a17:902:f60c:b0:156:82c9:e44b with SMTP id n12-20020a170902f60c00b0015682c9e44bmr6317311plg.106.1651384264514; Sat, 30 Apr 2022 22:51:04 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 36/45] target/arm: Implement virtual SError exceptions Date: Sat, 30 Apr 2022 22:50:18 -0700 Message-Id: <20220501055028.646596-37-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::631; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x631.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388553864100001 Content-Type: text/plain; charset="utf-8" Virtual SError exceptions are raised by setting HCR_EL2.VSE, and are routed to EL1 just like other virtual exceptions. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Honor EAE for reporting VSERR to aa32. --- target/arm/cpu.h | 2 ++ target/arm/internals.h | 8 ++++++++ target/arm/syndrome.h | 5 +++++ target/arm/cpu.c | 38 +++++++++++++++++++++++++++++++++++++- target/arm/helper.c | 40 +++++++++++++++++++++++++++++++++++++++- 5 files changed, 91 insertions(+), 2 deletions(-) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index a55980d66d..aade9237bd 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -56,6 +56,7 @@ #define EXCP_LSERR 21 /* v8M LSERR SecureFault */ #define EXCP_UNALIGNED 22 /* v7M UNALIGNED UsageFault */ #define EXCP_DIVBYZERO 23 /* v7M DIVBYZERO UsageFault */ +#define EXCP_VSERR 24 /* NB: add new EXCP_ defines to the array in arm_log_exception() too */ =20 #define ARMV7M_EXCP_RESET 1 @@ -89,6 +90,7 @@ enum { #define CPU_INTERRUPT_FIQ CPU_INTERRUPT_TGT_EXT_1 #define CPU_INTERRUPT_VIRQ CPU_INTERRUPT_TGT_EXT_2 #define CPU_INTERRUPT_VFIQ CPU_INTERRUPT_TGT_EXT_3 +#define CPU_INTERRUPT_VSERR CPU_INTERRUPT_TGT_INT_0 =20 /* The usual mapping for an AArch64 system register to its AArch32 * counterpart is for the 32 bit world to have access to the lower diff --git a/target/arm/internals.h b/target/arm/internals.h index c563b3735f..6ca0e95746 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -947,6 +947,14 @@ void arm_cpu_update_virq(ARMCPU *cpu); */ void arm_cpu_update_vfiq(ARMCPU *cpu); =20 +/** + * arm_cpu_update_vserr: Update CPU_INTERRUPT_VSERR bit + * + * Update the CPU_INTERRUPT_VSERR bit in cs->interrupt_request, + * following a change to the HCR_EL2.VSE bit. + */ +void arm_cpu_update_vserr(ARMCPU *cpu); + /** * arm_mmu_idx_el: * @env: The cpu environment diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h index 8cde8e7243..0cb26dde7d 100644 --- a/target/arm/syndrome.h +++ b/target/arm/syndrome.h @@ -287,4 +287,9 @@ static inline uint32_t syn_pcalignment(void) return (EC_PCALIGNMENT << ARM_EL_EC_SHIFT) | ARM_EL_IL; } =20 +static inline uint32_t syn_serror(uint32_t extra) +{ + return (EC_SERROR << ARM_EL_EC_SHIFT) | ARM_EL_IL | extra; +} + #endif /* TARGET_ARM_SYNDROME_H */ diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 97b6f9f68c..87d1e28896 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -85,7 +85,7 @@ static bool arm_cpu_has_work(CPUState *cs) return (cpu->power_state !=3D PSCI_OFF) && cs->interrupt_request & (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD - | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ + | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ | CPU_INTERRUPT_VSERR | CPU_INTERRUPT_EXITTB); } =20 @@ -509,6 +509,12 @@ static inline bool arm_excp_unmasked(CPUState *cs, uns= igned int excp_idx, return false; } return !(env->daif & PSTATE_I); + case EXCP_VSERR: + if (!(hcr_el2 & HCR_AMO) || (hcr_el2 & HCR_TGE)) { + /* VIRQs are only taken when hypervized. */ + return false; + } + return !(env->daif & PSTATE_A); default: g_assert_not_reached(); } @@ -630,6 +636,17 @@ static bool arm_cpu_exec_interrupt(CPUState *cs, int i= nterrupt_request) goto found; } } + if (interrupt_request & CPU_INTERRUPT_VSERR) { + excp_idx =3D EXCP_VSERR; + target_el =3D 1; + if (arm_excp_unmasked(cs, excp_idx, target_el, + cur_el, secure, hcr_el2)) { + /* Taking a virtual abort clears HCR_EL2.VSE */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + goto found; + } + } return false; =20 found: @@ -682,6 +699,25 @@ void arm_cpu_update_vfiq(ARMCPU *cpu) } } =20 +void arm_cpu_update_vserr(ARMCPU *cpu) +{ + /* + * Update the interrupt level for VSERR, which is the HCR_EL2.VSE bit. + */ + CPUARMState *env =3D &cpu->env; + CPUState *cs =3D CPU(cpu); + + bool new_state =3D env->cp15.hcr_el2 & HCR_VSE; + + if (new_state !=3D ((cs->interrupt_request & CPU_INTERRUPT_VSERR) !=3D= 0)) { + if (new_state) { + cpu_interrupt(cs, CPU_INTERRUPT_VSERR); + } else { + cpu_reset_interrupt(cs, CPU_INTERRUPT_VSERR); + } + } +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { diff --git a/target/arm/helper.c b/target/arm/helper.c index f6f26766e2..f62d16a456 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1863,7 +1863,12 @@ static uint64_t isr_read(CPUARMState *env, const ARM= CPRegInfo *ri) } } =20 - /* External aborts are not possible in QEMU so A bit is always clear */ + if (hcr_el2 & HCR_AMO) { + if (cs->interrupt_request & CPU_INTERRUPT_VSERR) { + ret |=3D CPSR_A; + } + } + return ret; } =20 @@ -5175,6 +5180,7 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) g_assert(qemu_mutex_iothread_locked()); arm_cpu_update_virq(cpu); arm_cpu_update_vfiq(cpu); + arm_cpu_update_vserr(cpu); } =20 static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t v= alue) @@ -9324,6 +9330,7 @@ void arm_log_exception(CPUState *cs) [EXCP_LSERR] =3D "v8M LSERR UsageFault", [EXCP_UNALIGNED] =3D "v7M UNALIGNED UsageFault", [EXCP_DIVBYZERO] =3D "v7M DIVBYZERO UsageFault", + [EXCP_VSERR] =3D "Virtual SERR", }; =20 if (idx >=3D 0 && idx < ARRAY_SIZE(excnames)) { @@ -9836,6 +9843,31 @@ static void arm_cpu_do_interrupt_aarch32(CPUState *c= s) mask =3D CPSR_A | CPSR_I | CPSR_F; offset =3D 4; break; + case EXCP_VSERR: + { + /* + * Note that this is reported as a data abort, but the DFAR + * has an UNKNOWN value. Construct the SError syndrome from + * AET and ExT fields. + */ + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal, }; + + if (extended_addresses_enabled(env)) { + env->exception.fsr =3D arm_fi_to_lfsc(&fi); + } else { + env->exception.fsr =3D arm_fi_to_sfsc(&fi); + } + env->exception.fsr |=3D env->cp15.vsesr_el2 & 0xd000; + A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr); + qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x\n", + env->exception.fsr); + + new_mode =3D ARM_CPU_MODE_ABT; + addr =3D 0x10; + mask =3D CPSR_A | CPSR_I; + offset =3D 8; + } + break; case EXCP_SMC: new_mode =3D ARM_CPU_MODE_MON; addr =3D 0x08; @@ -10056,6 +10088,12 @@ static void arm_cpu_do_interrupt_aarch64(CPUState = *cs) case EXCP_VFIQ: addr +=3D 0x100; break; + case EXCP_VSERR: + addr +=3D 0x180; + /* Construct the SError syndrome from IDS and ISS fields. */ + env->exception.syndrome =3D syn_serror(env->cp15.vsesr_el2 & 0x1ff= ffff); + env->cp15.esr_el[new_el] =3D env->exception.syndrome; + break; default: cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index); } --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651388157680103.08356353258807; Sat, 30 Apr 2022 23:55:57 -0700 (PDT) Received: from localhost ([::1]:38264 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3Uq-0004nq-KX for importer@patchew.org; Sun, 01 May 2022 02:55:56 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44144) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2UB-00077J-Hh for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:13 -0400 Received: from mail-pf1-x430.google.com ([2607:f8b0:4864:20::430]:36678) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2U8-0001RX-B4 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:51:11 -0400 Received: by mail-pf1-x430.google.com with SMTP id z16so10073083pfh.3 for ; Sat, 30 Apr 2022 22:51:06 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:04 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=abpiSeB9GnhU+yu70oxG40w5Q8oxipcU81kEqVLhpps=; b=b9u21RCgodWMMhGgzTIQktwXbRmudRM1BXXHmpVcpbWKEq7XVioI9AhStJJc3thwvm WSTLv1ll7kTlMNPPakeQhT3URRI++TPIzbJNGiC8u6Q75lEja940KvLT7gloLFKeyXUq zd4hSjkcfdNSXgPu6G1MIzd+pvBefgEUHDJp1WkgUlZrQTb883lmg9j7JK/ssh4XeEfM eHkVxgiqePOUTvjWYViX0SvhSdBi8eznsmUjXqnEXVVu8ZbjDpVNeeXoZr+mdwkQzijg GXxILFPEm2ZCCfutpJTytoeEnCX3uFSwBkwJ3Xt8IKa+TOEIwHNBqddJ5urFPq+fWvNM GZBw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=abpiSeB9GnhU+yu70oxG40w5Q8oxipcU81kEqVLhpps=; b=hHc+q6BvVooKNNHRssbm7yyGL36rZLkogT8X2s65k8h4pkV1BGPrGhqvz82l6znZi+ m5NYT6thzoxwe3TnEauNzWPvGgDyBdYQwpzVOL+Qi0ICU/EFdbGvKgJx/KSe3oRAuzhK W9zbpHxm7o7SHW7F/jhXNv4mQtBhet+cOO5JSQC/e6zFe/iw2F6pH6Fj1+7PZpri2187 LvOJ5+zWT9hP6FtOtuPicKIOJ5zE21955i+Txndf4KRz37pRSOFpmDN2OrIxSEDypVGe SOUokoWV4ix3raRfafjjsbS0Dkb52fR1b8jdwue1u0Ju4B/p1XRagTQfz/KqoPdL/mx6 Rjvg== X-Gm-Message-State: AOAM530qloGhfNAl2J0wuFOKXp3UVvmMWRt/5d3tw/0I+QaHL0wRGX1C YZbUNM5qWB8khceCvEw6ZOPYhRM4EHcz6Q== X-Google-Smtp-Source: ABdhPJxuizuhXLM9D3v1EXz14NSJDjdT3TKSMlh8KReMHD2bL0NqvT2PlO/zN6xpRJZegSzT+/o1pQ== X-Received: by 2002:a63:e849:0:b0:3c1:cf88:7b17 with SMTP id a9-20020a63e849000000b003c1cf887b17mr4821354pgk.590.1651384265316; Sat, 30 Apr 2022 22:51:05 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 37/45] target/arm: Implement ESB instruction Date: Sat, 30 Apr 2022 22:50:19 -0700 Message-Id: <20220501055028.646596-38-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::430; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x430.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388158162100001 Content-Type: text/plain; charset="utf-8" Check for and defer any pending virtual SError. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Retain m-profile check; improve comments. --- target/arm/helper.h | 1 + target/arm/a32.decode | 16 ++++++++------ target/arm/t32.decode | 18 ++++++++-------- target/arm/op_helper.c | 43 ++++++++++++++++++++++++++++++++++++++ target/arm/translate-a64.c | 17 +++++++++++++++ target/arm/translate.c | 23 ++++++++++++++++++++ 6 files changed, 103 insertions(+), 15 deletions(-) diff --git a/target/arm/helper.h b/target/arm/helper.h index b463d9343b..b1334e0c42 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -54,6 +54,7 @@ DEF_HELPER_1(wfe, void, env) DEF_HELPER_1(yield, void, env) DEF_HELPER_1(pre_hvc, void, env) DEF_HELPER_2(pre_smc, void, env, i32) +DEF_HELPER_1(vesb, void, env) =20 DEF_HELPER_3(cpsr_write, void, env, i32, i32) DEF_HELPER_2(cpsr_write_eret, void, env, i32) diff --git a/target/arm/a32.decode b/target/arm/a32.decode index fcd8cd4f7d..f2ca480949 100644 --- a/target/arm/a32.decode +++ b/target/arm/a32.decode @@ -187,13 +187,17 @@ SMULTT .... 0001 0110 .... 0000 .... 1110 .= ... @rd0mn =20 { { - YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 - WFE ---- 0011 0010 0000 1111 ---- 0000 0010 - WFI ---- 0011 0010 0000 1111 ---- 0000 0011 + [ + YIELD ---- 0011 0010 0000 1111 ---- 0000 0001 + WFE ---- 0011 0010 0000 1111 ---- 0000 0010 + WFI ---- 0011 0010 0000 1111 ---- 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 - # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV ---- 0011 0010 0000 1111 ---- 0000 0100 + # SEVL ---- 0011 0010 0000 1111 ---- 0000 0101 + + ESB ---- 0011 0010 0000 1111 ---- 0001 0000 + ] =20 # The canonical nop ends in 00000000, but the whole of the # rest of the space executes as nop if otherwise unsupported. diff --git a/target/arm/t32.decode b/target/arm/t32.decode index 78fadef9d6..f21ad0167a 100644 --- a/target/arm/t32.decode +++ b/target/arm/t32.decode @@ -364,17 +364,17 @@ CLZ 1111 1010 1011 ---- 1111 .... 1000 .= ... @rdm [ # Hints, and CPS { - YIELD 1111 0011 1010 1111 1000 0000 0000 0001 - WFE 1111 0011 1010 1111 1000 0000 0000 0010 - WFI 1111 0011 1010 1111 1000 0000 0000 0011 + [ + YIELD 1111 0011 1010 1111 1000 0000 0000 0001 + WFE 1111 0011 1010 1111 1000 0000 0000 0010 + WFI 1111 0011 1010 1111 1000 0000 0000 0011 =20 - # TODO: Implement SEV, SEVL; may help SMP performance. - # SEV 1111 0011 1010 1111 1000 0000 0000 0100 - # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 + # TODO: Implement SEV, SEVL; may help SMP performance. + # SEV 1111 0011 1010 1111 1000 0000 0000 0100 + # SEVL 1111 0011 1010 1111 1000 0000 0000 0101 =20 - # For M-profile minimal-RAS ESB can be a NOP, which is the - # default behaviour since it is in the hint space. - # ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ESB 1111 0011 1010 1111 1000 0000 0001 0000 + ] =20 # The canonical nop ends in 0000 0000, but the whole rest # of the space is "reserved hint, behaves as nop". diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 76499ffa14..390b6578a8 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -960,3 +960,46 @@ void HELPER(probe_access)(CPUARMState *env, target_ulo= ng ptr, access_type, mmu_idx, ra); } } + +/* + * This function corresponds to AArch64.vESBOperation(). + * Note that the AArch32 version is not functionally different. + */ +void HELPER(vesb)(CPUARMState *env) +{ + /* + * The EL2Enabled() check is done inside arm_hcr_el2_eff, + * and will return HCR_EL2.VSE =3D=3D 0, so nothing happens. + */ + uint64_t hcr =3D arm_hcr_el2_eff(env); + bool enabled =3D !(hcr & HCR_TGE) && (hcr & HCR_AMO); + bool pending =3D enabled && (hcr & HCR_VSE); + bool masked =3D (env->daif & PSTATE_A); + + /* If VSE pending and masked, defer the exception. */ + if (pending && masked) { + uint32_t syndrome; + + if (arm_el_is_aa64(env, 1)) { + /* Copy across IDS and ISS from VSESR. */ + syndrome =3D env->cp15.vsesr_el2 & 0x1ffffff; + } else { + ARMMMUFaultInfo fi =3D { .type =3D ARMFault_AsyncExternal }; + + if (extended_addresses_enabled(env)) { + syndrome =3D arm_fi_to_lfsc(&fi); + } else { + syndrome =3D arm_fi_to_sfsc(&fi); + } + /* Copy across AET and ExT from VSESR. */ + syndrome |=3D env->cp15.vsesr_el2 & 0xd000; + } + + /* Set VDISR_EL2.A along with the syndrome. */ + env->cp15.vdisr_el2 =3D syndrome | (1u << 31); + + /* Clear pending virtual SError */ + env->cp15.hcr_el2 &=3D ~HCR_VSE; + cpu_reset_interrupt(env_cpu(env), CPU_INTERRUPT_VSERR); + } +} diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index b80313670f..5a02e076b7 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1454,6 +1454,23 @@ static void handle_hint(DisasContext *s, uint32_t in= sn, gen_helper_autib(cpu_X[17], cpu_env, cpu_X[17], cpu_X[16]); } break; + case 0b10000: /* ESB */ + /* Without RAS, we must implement this as NOP. */ + if (dc_isar_feature(aa64_ras, s)) { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch64.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)= ) { + gen_helper_vesb(cpu_env); + } + } + break; case 0b11000: /* PACIAZ */ if (s->pauth_active) { gen_helper_pacia(cpu_X[30], cpu_env, cpu_X[30], diff --git a/target/arm/translate.c b/target/arm/translate.c index 4e19191ed5..87a899d638 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -6239,6 +6239,29 @@ static bool trans_WFI(DisasContext *s, arg_WFI *a) return true; } =20 +static bool trans_ESB(DisasContext *s, arg_ESB *a) +{ + /* + * For M-profile, minimal-RAS ESB can be a NOP. + * Without RAS, we must implement this as NOP. + */ + if (!arm_dc_feature(s, ARM_FEATURE_M) && dc_isar_feature(aa32_ras, s))= { + /* + * QEMU does not have a source of physical SErrors, + * so we are only concerned with virtual SErrors. + * The pseudocode in the ARM for this case is + * if PSTATE.EL IN {EL0, EL1} && EL2Enabled() then + * AArch32.vESBOperation(); + * Most of the condition can be evaluated at translation time. + * Test for EL2 present, and defer test for SEL2 to runtime. + */ + if (s->current_el <=3D 1 && arm_dc_feature(s, ARM_FEATURE_EL2)) { + gen_helper_vesb(cpu_env); + } + } + return true; +} + static bool trans_NOP(DisasContext *s, arg_NOP *a) { return true; --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651389527455272.7858250464001; Sun, 1 May 2022 00:18:47 -0700 (PDT) Received: from localhost ([::1]:38094 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3qw-0007KR-4t for importer@patchew.org; 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envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102f; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651389529191100001 Content-Type: text/plain; charset="utf-8" Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 0acac6347c..8110408000 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -42,6 +42,7 @@ the following architecture extensions: - FEAT_PMULL (PMULL, PMULL2 instructions) - FEAT_PMUv3p1 (PMU Extensions v3.1) - FEAT_PMUv3p4 (PMU Extensions v3.4) +- FEAT_RAS (Reliability, availability, and serviceability) - FEAT_RDM (Advanced SIMD rounding double multiply accumulate instructions) - FEAT_RNG (Random number generator) - FEAT_SB (Speculation Barrier) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 88d3cef93e..35881c74b2 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -744,6 +744,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64pfr0; t =3D FIELD_DP64(t, ID_AA64PFR0, FP, 1); /* FEAT_FP16 */ t =3D FIELD_DP64(t, ID_AA64PFR0, ADVSIMD, 1); /* FEAT_FP16 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, RAS, 1); /* FEAT_RAS */ t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 337598e949..c5cf7efe95 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -69,6 +69,7 @@ void aa32_max_features(ARMCPU *cpu) =20 t =3D cpu->isar.id_pfr0; t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id cm18-20020a17090afa1200b001cd8e9ea22asm17310342pjb.52.2022.04.30.22.51.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:51:06 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=GY2odDA192T0ClkUF75+bPEfdCFgpsNoLihYttz/3zY=; b=gM+/p6GPe69vxR/Q8J/FwQDrVSqGyVzkIQ+2D5My/lgBUBneEIV3nqs1D0dO12nk/7 mpYriYU2QTMMeoORugqyStoFX+KJVJtLATWT/g/VLfq7TG15G1iuOHy1VFf3xPfbZegA vJtiftjz00PZnOPb7etULLYqE5uzA19pRlzc+csNpmIASlwDZv8/y3rkC1+J65+RGdzb 1efEc62aEYwevxqNlv4ob4fIf7TddzUfkb6nr7vh5KqUrqDF4nuAWuYERhe1Rf3S7tyA 1VE96WirY7r5wN13OoekKa1gWflJMGlil2XIeR8gmPJeJXVK0fm0ICPHVB6mJ12CoP1N zOPw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=GY2odDA192T0ClkUF75+bPEfdCFgpsNoLihYttz/3zY=; b=piSUP9CpDXiM7ZosTA8qpWB/FKUTg0LbCKWesuFTBfjDx5WdeLvqrhthKj+i3V+EZ5 g7grkU3cs/jeeiuY99UoIX/rVvKl01srG/xNRwrKqgI+btUBGDNxa+S0zSLQQ6G6vh48 V9RrSEV6i3qKqYU7gxbOfF6Hx38FuLz6T7RLToN5lzkulVaTuh6D7QpatN2q2YRHgU5r b9GwDoxz83O8ru+vCD7q+gIu33TG0bYB8cmSx/TQN6Ekak8Ujlgcth2WbG7vadeyTRyc C5r72NWHHuLZWXh97JOP1RsreKiavTNBsdKqoPCZH4HO0yVoRdAQcUCJaKxXMRr4jI7L PjEQ== X-Gm-Message-State: AOAM533pfyqd7wV425Ossot5rh/7y8dnYpJPFWJ7b0N2fyBCKfAPmcPI VTZ0fE1MR0JzE4Fbg6jQWdkd0SL/FMfHiQ== X-Google-Smtp-Source: ABdhPJy5UV7Z0F6zzBFYEFJw6QzUBnJcJT3c1Mg3EJFyquM/sT4SnP1eySpEgrcHhU9KcGoQML5hjA== X-Received: by 2002:a17:902:e38c:b0:15b:40ca:37c8 with SMTP id g12-20020a170902e38c00b0015b40ca37c8mr6271854ple.23.1651384267065; Sat, 30 Apr 2022 22:51:07 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 39/45] target/arm: Enable FEAT_IESB for -cpu max Date: Sat, 30 Apr 2022 22:50:21 -0700 Message-Id: <20220501055028.646596-40-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::1029; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x1029.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388316804100001 Content-Type: text/plain; charset="utf-8" This feature is AArch64 only, and applies to physical SErrors, which QEMU does not implement, thus the feature is a nop. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + 2 files changed, 2 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 8110408000..b200012d89 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -25,6 +25,7 @@ the following architecture extensions: - FEAT_FlagM2 (Enhancements to flag manipulation instructions) - FEAT_HPDS (Hierarchical permission disables) - FEAT_I8MM (AArch64 Int8 matrix multiplication instructions) +- FEAT_IESB (Implicit error synchronization event) - FEAT_JSCVT (JavaScript conversion instructions) - FEAT_LOR (Limited ordering regions) - FEAT_LPA (Large Physical Address space) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 35881c74b2..10410619f9 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -781,6 +781,7 @@ static void aarch64_max_initfn(Object *obj) t =3D cpu->isar.id_aa64mmfr2; t =3D FIELD_DP64(t, ID_AA64MMFR2, CNP, 1); /* FEAT_TTCNP */ t =3D FIELD_DP64(t, ID_AA64MMFR2, UAO, 1); /* FEAT_UAO */ + t =3D FIELD_DP64(t, ID_AA64MMFR2, IESB, 1); /* FEAT_IESB */ t =3D FIELD_DP64(t, ID_AA64MMFR2, VARANGE, 1); /* FEAT_LVA */ t =3D FIELD_DP64(t, ID_AA64MMFR2, ST, 1); /* FEAT_TTST */ t =3D FIELD_DP64(t, ID_AA64MMFR2, TTL, 1); /* FEAT_TTL */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 16513891504669.188636417709859; Sun, 1 May 2022 00:12:30 -0700 (PDT) Received: from localhost ([::1]:56596 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3kr-0000hh-AW for importer@patchew.org; Sun, 01 May 2022 03:12:29 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44450) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2X5-0001AQ-V5 for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:12 -0400 Received: from mail-pl1-x633.google.com ([2607:f8b0:4864:20::633]:38594) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2X3-0001lY-Pn for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:11 -0400 Received: by mail-pl1-x633.google.com with SMTP id n18so10285324plg.5 for ; Sat, 30 Apr 2022 22:54:09 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id u63-20020a626042000000b005082a7fd144sm2341507pfb.3.2022.04.30.22.54.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:54:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=YgPJJBWxd6UwNbu8I9UhpjXUvb+eh/ewRL4C5SYoXZc=; b=ljUxeRGa0jwvJTYyNAzohNeJNnLr1DQxCjttj/QKBYNjVUQnWWSZaRvLgKJdB9R2To 0LwzWV0iSsS6nXujHOrRXUSgM6FjbjTfeXIQDW0SBt3Drymx8aOQPrhtXtNVT+Nzh1pH OKpgFzQGVJbbyO6mMnKaAcpO7ZUnFA2z2DakqgXM8U9qQQjYgY+SKPaoLMD/GdUky9iK lhir4+PO8gtLuTB21oW6m7RcefTz/eUeF6b806x6OZ28K/gx/ZSujZExs/gjBgye3uDy U4+K6+Ef+9ef97Uu+izG6WQQ47lcIpsrkaUKgL7e5R+E4BsnUSBny6hWqlUVHAc+CWLZ DLZg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=YgPJJBWxd6UwNbu8I9UhpjXUvb+eh/ewRL4C5SYoXZc=; b=qalagUWsB/c9gPmLte+GidoyW7AvoTKNaIoxT0MLWzcBQU3QM0AmFf6WG0/JZJSBt3 9nL/6iorFvN/jyMX5Z75iQJaLJqhqhmIf6jHzps1vCrF4BcNpo+WtefavyJCGasEQarf MndTKXxyZ8LEK3rUdVzO3N1EKLSmzYy5pJDSrx19LiQTp1L49FyAX4ttHo4QcYG49Q01 Q1Y4h3WjWxlwC5lGlY+bk4k2tyqEshhd5DL2sIL9Q28w5wKeIGoAmWG9PGJIAo4yNgZl 51UUhd9vGC6SDMzmprUgTW61f/WFX5C/uOgzU32hz57s1cVovJEnS3mFFqpKSxTt9Yn5 /lgQ== X-Gm-Message-State: AOAM532jp3XO40AF83fj8RsYw1QNa00RIJIQVk2FNjUbgrmJrysznT6M +ZedrxIKLBfW6SrvaByh2J/lozOtMdEbVA== X-Google-Smtp-Source: ABdhPJxvunAgWX2I9XQi7UlWakfZr9WjznsyjEEcOCZzDZpim+GNJhI5Tx95MBCNaiEjMohz+S45Gg== X-Received: by 2002:a17:90b:124a:b0:1d9:de12:520f with SMTP id gx10-20020a17090b124a00b001d9de12520fmr7139816pjb.28.1651384448637; Sat, 30 Apr 2022 22:54:08 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 40/45] target/arm: Enable FEAT_CSV2 for -cpu max Date: Sat, 30 Apr 2022 22:50:22 -0700 Message-Id: <20220501055028.646596-41-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::633; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x633.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651389151266100001 Content-Type: text/plain; charset="utf-8" This extension concerns branch speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b200012d89..b2a3e2a437 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -12,6 +12,7 @@ the following architecture extensions: - FEAT_BBM at level 2 (Translation table break-before-make levels) - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) +- FEAT_CSV2 (Cache speculation variant 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 10410619f9..25fe74f928 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,6 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index c5cf7efe95..762b961707 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -68,6 +68,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_mmfr4 =3D t; =20 t =3D cpu->isar.id_pfr0; + t =3D FIELD_DP32(t, ID_PFR0, CSV2, 2); /* FEAT_CVS2 */ t =3D FIELD_DP32(t, ID_PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP32(t, ID_PFR0, RAS, 1); /* FEAT_RAS */ cpu->isar.id_pfr0 =3D t; --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass(p=none dis=none) header.from=linaro.org ARC-Seal: i=1; a=rsa-sha256; t=1651389351; cv=none; d=zohomail.com; s=zohoarc; b=d+95VvymK0FUrYIRUL9GSl4Z3yzhPEO+/BHIvmvxCy7Tm/4pPMNeluSPFhqQ+DDpLBtXoRXqLgYPhpyBTjEDV1ildC5NfZthdg2U8VE0DoCrg6BarlGV16UA4QM5HaMt8gGOReEFtRBRu8DHuaABIytjI51EEi7dYzVZx1wzhyo= ARC-Message-Signature: i=1; a=rsa-sha256; c=relaxed/relaxed; d=zohomail.com; s=zohoarc; t=1651389351; h=Content-Transfer-Encoding:Cc:Date:From:In-Reply-To:List-Subscribe:List-Post:List-Id:List-Archive:List-Help:List-Unsubscribe:MIME-Version:Message-ID:References:Sender:Subject:To; bh=/sNyQVoVFwLD7H79tLZF0H2cEnOA75R4VObpiVd2KY8=; b=oG1exgWq7WGC2Y9nAOZa5ddWRIOg+PMq1gu6BR841L3TTZXsI3FwFZtBJBP4jrdi1rWegdxwQVOieQAf6pIICqUGOLpWOuwGsjc/dfgHLcLCZLiGsPuGQpD1WUdwvS5yvjJKgoB7gK2OfS9W3B0unSraVSUrJrF4NYYLNXqILVk= ARC-Authentication-Results: i=1; mx.zohomail.com; dkim=pass; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=pass header.from= (p=none dis=none) Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651389351813962.066397854447; Sun, 1 May 2022 00:15:51 -0700 (PDT) Received: from localhost ([::1]:33588 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3o6-0004GH-6e for importer@patchew.org; Sun, 01 May 2022 03:15:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44522) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2X8-0001BG-6e for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:14 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:37858) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2X4-0001lh-Va for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:13 -0400 Received: by mail-pl1-x62a.google.com with SMTP id k1so1681555pll.4 for ; Sat, 30 Apr 2022 22:54:10 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id u63-20020a626042000000b005082a7fd144sm2341507pfb.3.2022.04.30.22.54.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:54:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=/sNyQVoVFwLD7H79tLZF0H2cEnOA75R4VObpiVd2KY8=; b=b+DddqxZ/05Y0nT0JV9fhwC1EIvGDvei8nvtfbama/c0V/L5t+jIWoAbA0eQr+25Vv FmZJLzsAAAdDY+7E03ln+ZvKOUjX4jWDKaCC9dkrUvrD3S4GD3AE89zyZFVJhBBSB9cO s6JaMDtc2C8oNkS/tfw+FkDDRb5hzBFSKExq0jCyXzvX+bDOBu5yXKpC9SHbvOnXpvQt 8IosFxkjkJwJ5DVi9lHMOEPa1QR386ruA5ZW2WNFIjrhxwBFkKV1pQxudL3SOfpkqWBQ QpD1eoO+riqZVC+UdMx62MaiKwBuF47GX0u90wAH/8ptXArzdB/x9fgLgSIRd7Ta+Lqc YwJA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=/sNyQVoVFwLD7H79tLZF0H2cEnOA75R4VObpiVd2KY8=; b=F0FaEE+C7af2KqPtghssqDeqIuQ8HAFIagQv9Iu2pAbswG6ETnaUQy1j/qRSUukzKJ IWG9cNk0k32hw/fBbaSqC+WSfS0aBiW/mxoM/j9+qq7dUdG0UB+rdxhBcAVf5nJPdQmV qSiNIFsm76csJRIMpj4X0h149Dt5Zs3VuVqhYJvcb7Q6h0BjH2pvBGjaOtY4yBe6fwQw 8U2XSKZKnIJidEiy6gGSagYBGbx3mA1wYeCq4vYIbWVstphVH5tPzi+2jH9UWmxnGWSI aBSmNS7R3RMnYKNLIoQsJc5UhqJ2fzm4hV8itS20bBMmk3u5qn7G/pBDnnmSRFTFpImV 8aeQ== X-Gm-Message-State: AOAM532mdJ6brZ0+7NPkBUGxvzh00Q3d0F9u8bXTGPLlx8PgCG37itSQ eB5IgPjr2m1jx0byYNseRbGVNrum7ViLLQ== X-Google-Smtp-Source: ABdhPJwB7UV8zyJ+JEDCZvzxYUyeL9+8NEg/celyPAPixfU4DE3tpqBfJ4D0cO4Tg+93wcqHijJGuw== X-Received: by 2002:a17:902:b684:b0:156:80b4:db03 with SMTP id c4-20020a170902b68400b0015680b4db03mr6731823pls.16.1651384449565; Sat, 30 Apr 2022 22:54:09 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 41/45] target/arm: Enable FEAT_CSV2_2 for -cpu max Date: Sat, 30 Apr 2022 22:50:23 -0700 Message-Id: <20220501055028.646596-42-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651389352205100001 Content-Type: text/plain; charset="utf-8" There is no branch prediction in TCG, therefore there is no need to actually include the context number into the predictor. Therefore all we need to do is add the state for SCXTNUM_ELx. Signed-off-by: Richard Henderson Reviewed-by: Peter Maydell --- v2: Update emulation.rst; clear CSV2_FRAC; use decimal; tidy access_scxtnum. v3: Rely on EL3-no-EL2 squashing during registration. --- docs/system/arm/emulation.rst | 3 ++ target/arm/cpu.h | 16 +++++++++ target/arm/cpu64.c | 3 +- target/arm/helper.c | 61 ++++++++++++++++++++++++++++++++++- 4 files changed, 81 insertions(+), 2 deletions(-) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index b2a3e2a437..9765ee3eaf 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -13,6 +13,9 @@ the following architecture extensions: - FEAT_BF16 (AArch64 BFloat16 instructions) - FEAT_BTI (Branch Target Identification) - FEAT_CSV2 (Cache speculation variant 2) +- FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) +- FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) +- FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu.h b/target/arm/cpu.h index aade9237bd..18ca61e8e2 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -688,6 +688,8 @@ typedef struct CPUArchState { ARMPACKey apdb; ARMPACKey apga; } keys; + + uint64_t scxtnum_el[4]; #endif =20 #if defined(CONFIG_USER_ONLY) @@ -1211,6 +1213,7 @@ void pmu_init(ARMCPU *cpu); #define SCTLR_WXN (1U << 19) #define SCTLR_ST (1U << 20) /* up to ??, RAZ in v6 */ #define SCTLR_UWXN (1U << 20) /* v7 onward, AArch32 only */ +#define SCTLR_TSCXT (1U << 20) /* FEAT_CSV2_1p2, AArch64 only */ #define SCTLR_FI (1U << 21) /* up to v7, v8 RES0 */ #define SCTLR_IESB (1U << 21) /* v8.2-IESB, AArch64 only */ #define SCTLR_U (1U << 22) /* up to v6, RAO in v7 */ @@ -4022,6 +4025,19 @@ static inline bool isar_feature_aa64_dit(const ARMIS= ARegisters *id) return FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, DIT) !=3D 0; } =20 +static inline bool isar_feature_aa64_scxtnum(const ARMISARegisters *id) +{ + int key =3D FIELD_EX64(id->id_aa64pfr0, ID_AA64PFR0, CSV2); + if (key >=3D 2) { + return true; /* FEAT_CSV2_2 */ + } + if (key =3D=3D 1) { + key =3D FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, CSV2_FRAC); + return key >=3D 2; /* FEAT_CSV2_1p2 */ + } + return false; +} + static inline bool isar_feature_aa64_ssbs(const ARMISARegisters *id) { return FIELD_EX64(id->id_aa64pfr1, ID_AA64PFR1, SSBS) !=3D 0; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 25fe74f928..07b44a62be 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -748,7 +748,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SVE, 1); t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ - t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 1); /* FEAT_CSV2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; @@ -760,6 +760,7 @@ static void aarch64_max_initfn(Object *obj) * we do for EL2 with the virtualization=3Don property. */ t =3D FIELD_DP64(t, ID_AA64PFR1, MTE, 3); /* FEAT_MTE3 */ + t =3D FIELD_DP64(t, ID_AA64PFR1, CSV2_FRAC, 0); /* FEAT_CSV2_2 */ cpu->isar.id_aa64pfr1 =3D t; =20 t =3D cpu->isar.id_aa64mmfr0; diff --git a/target/arm/helper.c b/target/arm/helper.c index f62d16a456..7e31f11904 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -1770,6 +1770,9 @@ static void scr_write(CPUARMState *env, const ARMCPRe= gInfo *ri, uint64_t value) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D SCR_ATA; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D SCR_ENSCXT; + } } else { valid_mask &=3D ~(SCR_RW | SCR_ST); if (cpu_isar_feature(aa32_ras, cpu)) { @@ -5149,6 +5152,9 @@ static void do_hcr_write(CPUARMState *env, uint64_t v= alue, uint64_t valid_mask) if (cpu_isar_feature(aa64_mte, cpu)) { valid_mask |=3D HCR_ATA | HCR_DCT | HCR_TID5; } + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + valid_mask |=3D HCR_ENSCXT; + } } =20 /* Clear RES0 bits. */ @@ -5800,6 +5806,10 @@ static void define_arm_vh_e2h_redirects_aliases(ARMC= PU *cpu) { K(3, 0, 5, 6, 0), K(3, 4, 5, 6, 0), K(3, 5, 5, 6, 0), "TFSR_EL1", "TFSR_EL2", "TFSR_EL12", isar_feature_aa64_mte }, =20 + { K(3, 0, 13, 0, 7), K(3, 4, 13, 0, 7), K(3, 5, 13, 0, 7), + "SCXTNUM_EL1", "SCXTNUM_EL2", "SCXTNUM_EL12", + isar_feature_aa64_scxtnum }, + /* TODO: ARMv8.2-SPE -- PMSCR_EL2 */ /* TODO: ARMv8.4-Trace -- TRFCR_EL2 */ }; @@ -7223,7 +7233,52 @@ static const ARMCPRegInfo mte_el0_cacheop_reginfo[] = =3D { }, }; =20 -#endif +static CPAccessResult access_scxtnum(CPUARMState *env, const ARMCPRegInfo = *ri, + bool isread) +{ + uint64_t hcr =3D arm_hcr_el2_eff(env); + int el =3D arm_current_el(env); + + if (el =3D=3D 0 && !((hcr & HCR_E2H) && (hcr & HCR_TGE))) { + if (env->cp15.sctlr_el[1] & SCTLR_TSCXT) { + if (hcr & HCR_TGE) { + return CP_ACCESS_TRAP_EL2; + } + return CP_ACCESS_TRAP; + } + } else if (el < 2 && (env->cp15.sctlr_el[2] & SCTLR_TSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 2 && arm_is_el2_enabled(env) && !(hcr & HCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL2; + } + if (el < 3 + && arm_feature(env, ARM_FEATURE_EL3) + && !(env->cp15.scr_el3 & SCR_ENSCXT)) { + return CP_ACCESS_TRAP_EL3; + } + return CP_ACCESS_OK; +} + +static const ARMCPRegInfo scxtnum_reginfo[] =3D { + { .name =3D "SCXTNUM_EL0", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 3, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL0_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[0]) }, + { .name =3D "SCXTNUM_EL1", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 0, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL1_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[1]) }, + { .name =3D "SCXTNUM_EL2", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 4, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL2_RW, .accessfn =3D access_scxtnum, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[2]) }, + { .name =3D "SCXTNUM_EL3", .state =3D ARM_CP_STATE_AA64, + .opc0 =3D 3, .opc1 =3D 6, .crn =3D 13, .crm =3D 0, .opc2 =3D 7, + .access =3D PL3_RW, + .fieldoffset =3D offsetof(CPUARMState, scxtnum_el[3]) }, +}; +#endif /* TARGET_AARCH64 */ =20 static CPAccessResult access_predinv(CPUARMState *env, const ARMCPRegInfo = *ri, bool isread) @@ -8362,6 +8417,10 @@ void register_cp_regs_for_features(ARMCPU *cpu) define_arm_cp_regs(cpu, mte_tco_ro_reginfo); define_arm_cp_regs(cpu, mte_el0_cacheop_reginfo); } + + if (cpu_isar_feature(aa64_scxtnum, cpu)) { + define_arm_cp_regs(cpu, scxtnum_reginfo); + } #endif =20 if (cpu_isar_feature(any_predinv, cpu)) { --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651390023540589.7623539864151; Sun, 1 May 2022 00:27:03 -0700 (PDT) Received: from localhost ([::1]:48126 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3yw-0005rN-9x for importer@patchew.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id u63-20020a626042000000b005082a7fd144sm2341507pfb.3.2022.04.30.22.54.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:54:10 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=43XuEEQaBW24fA/OpN/C0G+r/QXfL2oSSQvbYI2NnFc=; b=Dp1EyG8Bw7vAGIJeggffnOJMdkd15qSMriDMrKVG2swELp/f/VtJVqsu4sj3DfWdAW 0LiUDXc0esBLl+HTotaiGSUwwtljWb96m3JYuSv1ereA92F1H6s/X3A5Dv5DtNtkR4cR kKpjK1U4GbVu4IFVco/p15RLH9La9oqcpYXXZfsuQ8LdpfWcy/u2+1GqSHyeN4JxUd1b Fg3q5m7eeuF2Slfqqyug/GksT6n6EbOuL3Y/X7dw3s2QPQDR6k1S4aFWfhYPXYk7jwEx lFunEZCWl4sCpagPt9Kj68QQkm+3BSzR4STCufyOUJiuknFNJlozO0EUDWKEm8qcRzIp xAKQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=43XuEEQaBW24fA/OpN/C0G+r/QXfL2oSSQvbYI2NnFc=; b=ujRuF1MnmC8GF2Lq2FWCY8ZuSEmdqwt8vqQSNjfQbHjjCULfLRmqsJtAwUX2a+GJq5 H4GYm/zKw8J3A48l/806EeXi7au+oRd3jizHUIWt2H8D3SHcG8/R5+U2QOfL2CoOINQg 5RA00YIfbCEHmwlIVk/WtM1w2e4nlVjNduN/UXq2Sl7qJd6zaGvTJna+NlVy1PyxC0dV talPWDIXXQNA0L5PtKi2swuBHriLmYPOK7iLWXmSCe9xOE1deEti5rtzxOfLtn1EkVWP KbCW9GwXVoRWQVKXmJb6Jg3XpW/nfY2ikUFdNbxzzpcux2Fzt048eixIseAumXn79tJc 1MxA== X-Gm-Message-State: AOAM533tvTpruzGEZxuIAa8dOqP6hZJLCEI5UDobZ42m/cep4oII5IJc UrZ3oc1YZ94PNJDvCdBgfA9LJcQ24xSbYA== X-Google-Smtp-Source: ABdhPJyr9it5k4sTI158z0pOnp4LAaYZJoffy6uQhDVxXqC9A6uCK/C3zlRZ4MbueU18RlSGhUkHGQ== X-Received: by 2002:a17:90b:38c5:b0:1da:4d99:6951 with SMTP id nn5-20020a17090b38c500b001da4d996951mr7018770pjb.243.1651384450605; Sat, 30 Apr 2022 22:54:10 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 42/45] target/arm: Enable FEAT_CSV3 for -cpu max Date: Sat, 30 Apr 2022 22:50:24 -0700 Message-Id: <20220501055028.646596-43-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::102b; envelope-from=richard.henderson@linaro.org; helo=mail-pj1-x102b.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651390025333100001 Content-Type: text/plain; charset="utf-8" This extension concerns cache speculation, which TCG does not implement. Thus we can trivially enable this feature. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/cpu_tcg.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 9765ee3eaf..48522b8e1c 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -16,6 +16,7 @@ the following architecture extensions: - FEAT_CSV2_1p1 (Cache speculation variant 2, version 1.1) - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) +- FEAT_CSV3 (Cache speculation variant 3) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 07b44a62be..40f77defb5 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -749,6 +749,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64PFR0, SEL2, 1); /* FEAT_SEL2 */ t =3D FIELD_DP64(t, ID_AA64PFR0, DIT, 1); /* FEAT_DIT */ t =3D FIELD_DP64(t, ID_AA64PFR0, CSV2, 2); /* FEAT_CSV2_2 */ + t =3D FIELD_DP64(t, ID_AA64PFR0, CSV3, 1); /* FEAT_CSV3 */ cpu->isar.id_aa64pfr0 =3D t; =20 t =3D cpu->isar.id_aa64pfr1; diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c index 762b961707..ea4eccddc3 100644 --- a/target/arm/cpu_tcg.c +++ b/target/arm/cpu_tcg.c @@ -74,6 +74,7 @@ void aa32_max_features(ARMCPU *cpu) cpu->isar.id_pfr0 =3D t; =20 t =3D cpu->isar.id_pfr2; + t =3D FIELD_DP32(t, ID_PFR2, CSV3, 1); /* FEAT_CSV3 */ t =3D FIELD_DP32(t, ID_PFR2, SSBS, 1); /* FEAT_SSBS */ cpu->isar.id_pfr2 =3D t; =20 --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651389540985469.4162958366438; Sun, 1 May 2022 00:19:00 -0700 (PDT) Received: from localhost ([::1]:38576 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3r9-0007fb-JT for importer@patchew.org; Sun, 01 May 2022 03:18:59 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44564) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2XA-0001Cb-9S for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:17 -0400 Received: from mail-pl1-x62e.google.com ([2607:f8b0:4864:20::62e]:43005) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2X6-0001m8-Rl for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:14 -0400 Received: by mail-pl1-x62e.google.com with SMTP id d22so104960plr.9 for ; Sat, 30 Apr 2022 22:54:12 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id u63-20020a626042000000b005082a7fd144sm2341507pfb.3.2022.04.30.22.54.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:54:11 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=ffCp2E5F/+S85cFm2jKC10BX2N+sZzcIlrVCqyHFbrg=; b=zxJYJUsGj3UMTelT5M2HSrf0qaKnT/X2o/MbbbJP33P/jKqt5SaZVjuTr4XE678RcU p1cnpxxwlUJ9VMoYhsBUcafrDSTNuJMeeG6EzOrpfi47NGVdMLDg5h4pu32iA0LuZ7KF /HiKCH0tc6dTWh+jSo0nFhAZc7w8hZT/Sj17YuSeYuSqbcbq8ZmOpH1TrTaMLXCZleFy AB/JoRJxFiRKvNKLWPXfjN1KXQ+gA+CXbNnzEqT2HQU68aP7nU4Tw7vw/iUhrthBYZkW hXnaka1r65/Gf9oJjPaHCVoE9noWpDHJT0t4vLwmjh8dpjKG76WysD7Z0yn9tl2FHld3 qNow== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=ffCp2E5F/+S85cFm2jKC10BX2N+sZzcIlrVCqyHFbrg=; b=zJg9FsGsPsjg0xDTZhkqlF6d9CnlOzxOduqnQZgyuOTzXnedCaQJ2rPoUZSFj43FoV mDr+JIrjSrKxmSErHHGiSy6f4JUSyVo88JUc5u306wvlZ+J6wjq3dALRMC+y9BeuxiDy vWmRCfZ37zrL6d8E+VVy7HVhR8nKqsPAZcLLY5Og28SVF6K5Cyrz2Jft1aL2NUop3VSH FGXEANyXj6R+vyfGz9RNkrB5ZpYM/j+51eoxXktp/aNJq19bCZ6Fxud9s+CkL4mHk5rw 0E7KAVZPJgNq+Dgc1F7xu71i3lXNwTDT63IsO9mPD+/lSq+RHv4662usfwi7bx4UVl+G /YdQ== X-Gm-Message-State: AOAM532lDMeiFUVSzkPYq/6/S/By+8KUSL365Zd3CODLqwxHrb+4+KvP CgR68jHByb4ZdICjqhFo59GnLegWs8/73g== X-Google-Smtp-Source: ABdhPJxu5gKq24w25XtOOqiunLYW774XHug1zE3LNJzAjy6r5cXeJm+wXppWs1WUeGFkHnPCjekyGw== X-Received: by 2002:a17:90a:c595:b0:1d9:532e:52fd with SMTP id l21-20020a17090ac59500b001d9532e52fdmr7143348pjt.79.1651384451611; Sat, 30 Apr 2022 22:54:11 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 43/45] target/arm: Enable FEAT_DGH for -cpu max Date: Sat, 30 Apr 2022 22:50:25 -0700 Message-Id: <20220501055028.646596-44-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62e; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62e.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651389544027100003 Content-Type: text/plain; charset="utf-8" This extension concerns not merging memory access, which TCG does not implement. Thus we can trivially enable this feature. Add a comment to handle_hint for the DGH instruction, but no code. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- v2: Update emulation.rst --- docs/system/arm/emulation.rst | 1 + target/arm/cpu64.c | 1 + target/arm/translate-a64.c | 1 + 3 files changed, 3 insertions(+) diff --git a/docs/system/arm/emulation.rst b/docs/system/arm/emulation.rst index 48522b8e1c..8ed466bf68 100644 --- a/docs/system/arm/emulation.rst +++ b/docs/system/arm/emulation.rst @@ -17,6 +17,7 @@ the following architecture extensions: - FEAT_CSV2_1p2 (Cache speculation variant 2, version 1.2) - FEAT_CSV2_2 (Cache speculation variant 2, version 2) - FEAT_CSV3 (Cache speculation variant 3) +- FEAT_DGH (Data gathering hint) - FEAT_DIT (Data Independent Timing instructions) - FEAT_DPB (DC CVAP instruction) - FEAT_Debugv8p2 (Debug changes for v8.2) diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index 40f77defb5..f55121060d 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -738,6 +738,7 @@ static void aarch64_max_initfn(Object *obj) t =3D FIELD_DP64(t, ID_AA64ISAR1, SB, 1); /* FEAT_SB */ t =3D FIELD_DP64(t, ID_AA64ISAR1, SPECRES, 1); /* FEAT_SPECRES */ t =3D FIELD_DP64(t, ID_AA64ISAR1, BF16, 1); /* FEAT_BF16 */ + t =3D FIELD_DP64(t, ID_AA64ISAR1, DGH, 1); /* FEAT_DGH */ t =3D FIELD_DP64(t, ID_AA64ISAR1, I8MM, 1); /* FEAT_I8MM */ cpu->isar.id_aa64isar1 =3D t; =20 diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 5a02e076b7..6a27234a5c 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -1427,6 +1427,7 @@ static void handle_hint(DisasContext *s, uint32_t ins= n, break; case 0b00100: /* SEV */ case 0b00101: /* SEVL */ + case 0b00110: /* DGH */ /* we treat all as NOP at least for now */ break; case 0b00111: /* XPACLRI */ --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651390476101268.52177400456753; Sun, 1 May 2022 00:34:36 -0700 (PDT) Received: from localhost ([::1]:53166 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl46D-0001F3-Eb for importer@patchew.org; Sun, 01 May 2022 03:34:33 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44568) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2XA-0001Cd-9f for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:17 -0400 Received: from mail-pl1-x62a.google.com ([2607:f8b0:4864:20::62a]:36545) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2X7-0001mI-UQ for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:15 -0400 Received: by mail-pl1-x62a.google.com with SMTP id n14so3397010plf.3 for ; Sat, 30 Apr 2022 22:54:13 -0700 (PDT) Received: from stoup.. ([71.212.142.129]) by smtp.gmail.com with ESMTPSA id u63-20020a626042000000b005082a7fd144sm2341507pfb.3.2022.04.30.22.54.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:54:12 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=vEHioUTW07RbxrApJKm//wt4N/0RvoNJcCdNTfvqqX8=; b=thDrjyzp+jfsNrGVER2O+pQaUjKBTN4zLVzDjsMiW+fmvIoLwXaa4bqztwrOuxuByT hOjlFQqxkqkre7Ylmmd7tXz8srFUF0l8oFNnFvKXJGUw0zTqJ07ELcbllsk0lcNygyyV LPybMt6WeOEoe4Q21r4wThSAQT6kLk5ORvJWjc4H/QtrcA1Fc/cMWdZfDsSnNNnc/JOF uhg1H9o8Hqxh0b2T5MGNxPIyvW9gVvbhKYaF6AkqLp28b+9ets4FCYwxkuoEemkFpsrk 6MlMhNkoSgZ0OaqsH0vuRHNnA3cP36GcEKH89uIl11ZkCbZW0RHmBejjsNNNR8T59ySI U8Ug== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=vEHioUTW07RbxrApJKm//wt4N/0RvoNJcCdNTfvqqX8=; b=rwN6Nz8OuNCPmeLQs2CXNQ2LoexYvm7y3+tZOjWBcowdszofZx88HDsaktOIuZMraV 9wehfmq2M9o84PKrW/tPsdfb5QqAQUEK9snt2C2uktMK3zMK/pGO/df1otNjoAyokDWX WWzaB+dDsqq4UOncD69b5FY6Xd/FFUAUglLUwoebnb6poWSk/dG1yFKNVZ8sH5V07DOv cbZVF0DZduyouKZyOEW13cz8Ox1cId3kr3RtxnmBTWT3bqYH4nUpnuYsPA3NHNjekwrB 6iJHWax4962k16FM/UiZSFK+UKICZq2sW1zsN7dFohn+rwxq3JxXn3sOm6XESkzgfiI3 bJxA== X-Gm-Message-State: AOAM532p84zYINVFVCsZt5hUQUHmwfB+eqEt2Lkjw8kHy6DZPpio+h1h qR/1K+g2xb1c7jvFR3HNWI1VSUKjI/Wreg== X-Google-Smtp-Source: ABdhPJx2/CcmwIJCx9qElGQu76bwS1ETam+CJmyHj2pXmGfHRd+McRWG2MqTdj1QVSlf35il9CjRtw== X-Received: by 2002:a17:902:b606:b0:158:f7d1:c085 with SMTP id b6-20020a170902b60600b00158f7d1c085mr6299777pls.12.1651384452625; Sat, 30 Apr 2022 22:54:12 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 44/45] target/arm: Define cortex-a76 Date: Sat, 30 Apr 2022 22:50:26 -0700 Message-Id: <20220501055028.646596-45-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651390477692100001 Content-Type: text/plain; charset="utf-8" Enable the a76 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 5fe045cbf0..3e264d85af 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -55,6 +55,7 @@ Supported guest CPU types: - ``cortex-a53`` (64-bit) - ``cortex-a57`` (64-bit) - ``cortex-a72`` (64-bit) +- ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2387401963..2ddde88f5e 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -145,6 +145,7 @@ static const int sbsa_ref_irqmap[] =3D { static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index f94278935f..12bc2318ec 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -202,6 +202,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a53"), ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), + ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index f55121060d..adfe6b26be 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -194,6 +194,71 @@ static void aarch64_a72_initfn(Object *obj) define_cortex_a72_a57_a53_cp_reginfo(cpu); } =20 +static void aarch64_a76_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,cortex-a76"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444C004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000010305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101122ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000010ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0b1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.18 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x707fe03a; /* 512KB L2 cache */ + + /* From B2.93 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -881,6 +946,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a57", .initfn =3D aarch64_a57_initfn }, { .name =3D "cortex-a53", .initfn =3D aarch64_a53_initfn }, { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, + { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) --=20 2.34.1 From nobody Sun May 12 00:57:19 2024 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org; dmarc=fail(p=none dis=none) header.from=linaro.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651388539055503.6885636183749; Sun, 1 May 2022 00:02:19 -0700 (PDT) Received: from localhost ([::1]:47522 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nl3az-0002e2-8C for importer@patchew.org; Sun, 01 May 2022 03:02:17 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:44592) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nl2XB-0001D9-PU for qemu-devel@nongnu.org; Sun, 01 May 2022 01:54:18 -0400 Received: from mail-pg1-x530.google.com ([2607:f8b0:4864:20::530]:39685) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_128_GCM_SHA256:128) (Exim 4.90_1) (envelope-from ) id 1nl2XA-0001mU-0V for qemu-devel@nongnu.org; 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([71.212.142.129]) by smtp.gmail.com with ESMTPSA id u63-20020a626042000000b005082a7fd144sm2341507pfb.3.2022.04.30.22.54.12 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 30 Apr 2022 22:54:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=zS8iy63zUNyzTAn358CLXJXvtW6Z0IyKqcTl9uBiuyg=; b=S3ee89VHXM7cuc34a76obe6OVFEOtRbfwHYWcQIhH5FWuE+gGhV28iBe3uSzQwsLNb PHBTpD+TS81ZKVEGr8n8BC7BO3++lpl86uOcblaF6O966Sqo7rHdmzsNrQZ5fjgkUK8C J7WJtWl0+UNRuBaIUxDJ7JaZBTDIWTR7Fp8DqGhnZg0//ch66yCBb09AS4LfG1rvZ1/y yEproadiolE1GlPMcXelfujqnKna3tMzPrgJdeJsjRLfJfoeot/3epb+3N1RlG7CDmHT tTltTGjgR96n6Kx9Pba/n9lhMOSjEYWl4GtvUlo24YJb/KX2snAABlCF6kWBLhNOvVgZ A6/w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=zS8iy63zUNyzTAn358CLXJXvtW6Z0IyKqcTl9uBiuyg=; b=6rdDKu1TWqPyFKCAhnfNZao4jxW+f4PKjj97gm1XV7LDavt9Po+uiuZrHHxNo+sP7W vYCGIABnJsx7q9U1p6KlNxH73RijKJrLzxqPgniSxvcF3jQ6Rx3UOqUY3lb+XMwzO+Qb E7qxTZ+AiU66NUaiPAOH9vy/3oGOkhwc9gRmJ737KFQDW0jSG/rtrpyfB7MHlVjW8unl 01HaaKDj5+1KQ7iQao8zpG/hHenifmFmVKujD8t+6puugz/k0s7OQRvHdLhKGCdj9ySJ rODpOA5kFuePwM74KxHRWUlbNCXiAEYDgvcoirFcmfC6KWCF/lLIB9UvQKkKls2iMu7B 43oA== X-Gm-Message-State: AOAM531n1wT77m57QziTyNGEYxGk300rJBrlMTI9lqkOGOTORJKFkM9m RDkWGBv2JawQnG21SCUmT7VL+KHGy9PSHA== X-Google-Smtp-Source: ABdhPJwTnX3R83345mMjqypBZXlLM7FImKP75of2EuViEaej29XEAfnfZdHdVL/l5druYRjvkQazpg== X-Received: by 2002:a63:2c02:0:b0:3ab:2bed:beac with SMTP id s2-20020a632c02000000b003ab2bedbeacmr5363125pgs.86.1651384453504; Sat, 30 Apr 2022 22:54:13 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v4 45/45] target/arm: Define neoverse-n1 Date: Sat, 30 Apr 2022 22:50:27 -0700 Message-Id: <20220501055028.646596-46-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220501055028.646596-1-richard.henderson@linaro.org> References: <20220501055028.646596-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::530; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x530.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell , qemu-arm@nongnu.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651388540022100001 Content-Type: text/plain; charset="utf-8" Enable the n1 for virt and sbsa board use. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson --- docs/system/arm/virt.rst | 1 + hw/arm/sbsa-ref.c | 1 + hw/arm/virt.c | 1 + target/arm/cpu64.c | 66 ++++++++++++++++++++++++++++++++++++++++ 4 files changed, 69 insertions(+) diff --git a/docs/system/arm/virt.rst b/docs/system/arm/virt.rst index 3e264d85af..3d1058a80c 100644 --- a/docs/system/arm/virt.rst +++ b/docs/system/arm/virt.rst @@ -58,6 +58,7 @@ Supported guest CPU types: - ``cortex-a76`` (64-bit) - ``a64fx`` (64-bit) - ``host`` (with KVM only) +- ``neoverse-n1`` (64-bit) - ``max`` (same as ``host`` for KVM; best possible emulation with TCG) =20 Note that the default is ``cortex-a15``, so for an AArch64 guest you must diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 2ddde88f5e..dac8860f2d 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -146,6 +146,7 @@ static const char * const valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a57"), ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("max"), }; =20 diff --git a/hw/arm/virt.c b/hw/arm/virt.c index 12bc2318ec..da7e3ede56 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -204,6 +204,7 @@ static const char *valid_cpus[] =3D { ARM_CPU_TYPE_NAME("cortex-a72"), ARM_CPU_TYPE_NAME("cortex-a76"), ARM_CPU_TYPE_NAME("a64fx"), + ARM_CPU_TYPE_NAME("neoverse-n1"), ARM_CPU_TYPE_NAME("host"), ARM_CPU_TYPE_NAME("max"), }; diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c index adfe6b26be..04427e073f 100644 --- a/target/arm/cpu64.c +++ b/target/arm/cpu64.c @@ -259,6 +259,71 @@ static void aarch64_a76_initfn(Object *obj) cpu->isar.mvfr2 =3D 0x00000043; } =20 +static void aarch64_neoverse_n1_initfn(Object *obj) +{ + ARMCPU *cpu =3D ARM_CPU(obj); + + cpu->dtb_compatible =3D "arm,neoverse-n1"; + set_feature(&cpu->env, ARM_FEATURE_V8); + set_feature(&cpu->env, ARM_FEATURE_NEON); + set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER); + set_feature(&cpu->env, ARM_FEATURE_AARCH64); + set_feature(&cpu->env, ARM_FEATURE_CBAR_RO); + set_feature(&cpu->env, ARM_FEATURE_EL2); + set_feature(&cpu->env, ARM_FEATURE_EL3); + set_feature(&cpu->env, ARM_FEATURE_PMU); + + /* Ordered by B2.4 AArch64 registers by functional group */ + cpu->clidr =3D 0x82000023; + cpu->ctr =3D 0x8444c004; + cpu->dcz_blocksize =3D 4; + cpu->isar.id_aa64dfr0 =3D 0x0000000110305408ull; + cpu->isar.id_aa64isar0 =3D 0x0000100010211120ull; + cpu->isar.id_aa64isar1 =3D 0x0000000000100001ull; + cpu->isar.id_aa64mmfr0 =3D 0x0000000000101125ull; + cpu->isar.id_aa64mmfr1 =3D 0x0000000010212122ull; + cpu->isar.id_aa64mmfr2 =3D 0x0000000000001011ull; + cpu->isar.id_aa64pfr0 =3D 0x1100000010111112ull; /* GIC filled in lat= er */ + cpu->isar.id_aa64pfr1 =3D 0x0000000000000020ull; + cpu->id_afr0 =3D 0x00000000; + cpu->isar.id_dfr0 =3D 0x04010088; + cpu->isar.id_isar0 =3D 0x02101110; + cpu->isar.id_isar1 =3D 0x13112111; + cpu->isar.id_isar2 =3D 0x21232042; + cpu->isar.id_isar3 =3D 0x01112131; + cpu->isar.id_isar4 =3D 0x00010142; + cpu->isar.id_isar5 =3D 0x01011121; + cpu->isar.id_isar6 =3D 0x00000010; + cpu->isar.id_mmfr0 =3D 0x10201105; + cpu->isar.id_mmfr1 =3D 0x40000000; + cpu->isar.id_mmfr2 =3D 0x01260000; + cpu->isar.id_mmfr3 =3D 0x02122211; + cpu->isar.id_mmfr4 =3D 0x00021110; + cpu->isar.id_pfr0 =3D 0x10010131; + cpu->isar.id_pfr1 =3D 0x00010000; /* GIC filled in later */ + cpu->isar.id_pfr2 =3D 0x00000011; + cpu->midr =3D 0x414fd0c1; /* r4p1 */ + cpu->revidr =3D 0; + + /* From B2.23 CCSIDR_EL1 */ + cpu->ccsidr[0] =3D 0x701fe01a; /* 64KB L1 dcache */ + cpu->ccsidr[1] =3D 0x201fe01a; /* 64KB L1 icache */ + cpu->ccsidr[2] =3D 0x70ffe03a; /* 1MB L2 cache */ + + /* From B2.98 SCTLR_EL3 */ + cpu->reset_sctlr =3D 0x30c50838; + + /* From B4.23 ICH_VTR_EL2 */ + cpu->gic_num_lrs =3D 4; + cpu->gic_vpribits =3D 5; + cpu->gic_vprebits =3D 5; + + /* From B5.1 AdvSIMD AArch64 register summary */ + cpu->isar.mvfr0 =3D 0x10110222; + cpu->isar.mvfr1 =3D 0x13211111; + cpu->isar.mvfr2 =3D 0x00000043; +} + void arm_cpu_sve_finalize(ARMCPU *cpu, Error **errp) { /* @@ -948,6 +1013,7 @@ static const ARMCPUInfo aarch64_cpus[] =3D { { .name =3D "cortex-a72", .initfn =3D aarch64_a72_initfn }, { .name =3D "cortex-a76", .initfn =3D aarch64_a76_initfn }, { .name =3D "a64fx", .initfn =3D aarch64_a64fx_initfn }, + { .name =3D "neoverse-n1", .initfn =3D aarch64_neoverse_n1_init= fn }, { .name =3D "max", .initfn =3D aarch64_max_initfn }, #if defined(CONFIG_KVM) || defined(CONFIG_HVF) { .name =3D "host", .initfn =3D aarch64_host_initfn }, --=20 2.34.1