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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Weiwei Li <liweiwei@iscas.ac.cn>,
Junqiang Wang <wangjunqiang@iscas.ac.cn>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PULL 04/25] target/riscv: rvk: add cfg properties for zbk* and zk*
Date: Fri, 29 Apr 2022 14:30:58 +1000
Message-Id: <20220429043119.1478881-5-alistair.francis@opensource.wdc.com>
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From: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Acked-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220423023510.30794-2-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 13 +++++++++++++
target/riscv/cpu.c | 23 +++++++++++++++++++++++
2 files changed, 36 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 46c66fbf8e..fe6c9a2c92 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -377,7 +377,20 @@ struct RISCVCPUConfig {
bool ext_zba;
bool ext_zbb;
bool ext_zbc;
+ bool ext_zbkb;
+ bool ext_zbkc;
+ bool ext_zbkx;
bool ext_zbs;
+ bool ext_zk;
+ bool ext_zkn;
+ bool ext_zknd;
+ bool ext_zkne;
+ bool ext_zknh;
+ bool ext_zkr;
+ bool ext_zks;
+ bool ext_zksed;
+ bool ext_zksh;
+ bool ext_zkt;
bool ext_counters;
bool ext_ifencei;
bool ext_icsr;
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index ace68ed855..62a47c197b 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -612,6 +612,29 @@ static void riscv_cpu_realize(DeviceState *dev, Error =
**errp)
cpu->cfg.ext_zfinx =3D true;
}
=20
+ if (cpu->cfg.ext_zk) {
+ cpu->cfg.ext_zkn =3D true;
+ cpu->cfg.ext_zkr =3D true;
+ cpu->cfg.ext_zkt =3D true;
+ }
+
+ if (cpu->cfg.ext_zkn) {
+ cpu->cfg.ext_zbkb =3D true;
+ cpu->cfg.ext_zbkc =3D true;
+ cpu->cfg.ext_zbkx =3D true;
+ cpu->cfg.ext_zkne =3D true;
+ cpu->cfg.ext_zknd =3D true;
+ cpu->cfg.ext_zknh =3D true;
+ }
+
+ if (cpu->cfg.ext_zks) {
+ cpu->cfg.ext_zbkb =3D true;
+ cpu->cfg.ext_zbkc =3D true;
+ cpu->cfg.ext_zbkx =3D true;
+ cpu->cfg.ext_zksed =3D true;
+ cpu->cfg.ext_zksh =3D true;
+ }
+
/* Set the ISA extensions, checks should have happened above */
if (cpu->cfg.ext_i) {
ext |=3D RVI;
--=20
2.35.1