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From: Alistair Francis <alistair.francis@opensource.wdc.com>
To: qemu-devel@nongnu.org
Cc: alistair23@gmail.com, Frank Chang <frank.chang@sifive.com>,
Jim Shu <jim.shu@sifive.com>, Alistair Francis <alistair.francis@wdc.com>,
Bin Meng <bmeng.cn@gmail.com>
Subject: [PULL 03/25] target/riscv: Support configuarable marchid, mvendorid,
mipid CSR values
Date: Fri, 29 Apr 2022 14:30:57 +1000
Message-Id: <20220429043119.1478881-4-alistair.francis@opensource.wdc.com>
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From: Frank Chang <frank.chang@sifive.com>
Allow user to set core's marchid, mvendorid, mipid CSRs through
-cpu command line option.
The default values of marchid and mipid are built with QEMU's version
numbers.
Signed-off-by: Frank Chang <frank.chang@sifive.com>
Reviewed-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Message-Id: <20220422040436.2233-1-frank.chang@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
---
target/riscv/cpu.h | 4 ++++
target/riscv/cpu.c | 9 +++++++++
target/riscv/csr.c | 38 ++++++++++++++++++++++++++++++++++----
3 files changed, 47 insertions(+), 4 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 34c22d5d3b..46c66fbf8e 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -393,6 +393,10 @@ struct RISCVCPUConfig {
bool ext_zve32f;
bool ext_zve64f;
=20
+ uint32_t mvendorid;
+ uint64_t marchid;
+ uint64_t mipid;
+
/* Vendor-specific custom extensions */
bool ext_XVentanaCondOps;
=20
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 0c774056c5..ace68ed855 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,11 @@
=20
/* RISC-V CPU definitions */
=20
+#define RISCV_CPU_MARCHID ((QEMU_VERSION_MAJOR << 16) | \
+ (QEMU_VERSION_MINOR << 8) | \
+ (QEMU_VERSION_MICRO))
+#define RISCV_CPU_MIPID RISCV_CPU_MARCHID
+
static const char riscv_single_letter_exts[] =3D "IEMAFDQCPVH";
=20
struct isa_ext_data {
@@ -810,6 +815,10 @@ static Property riscv_cpu_properties[] =3D {
DEFINE_PROP_UINT16("vlen", RISCVCPU, cfg.vlen, 128),
DEFINE_PROP_UINT16("elen", RISCVCPU, cfg.elen, 64),
=20
+ DEFINE_PROP_UINT32("mvendorid", RISCVCPU, cfg.mvendorid, 0),
+ DEFINE_PROP_UINT64("marchid", RISCVCPU, cfg.marchid, RISCV_CPU_MARCHID=
),
+ DEFINE_PROP_UINT64("mipid", RISCVCPU, cfg.mipid, RISCV_CPU_MIPID),
+
DEFINE_PROP_BOOL("svinval", RISCVCPU, cfg.ext_svinval, false),
DEFINE_PROP_BOOL("svnapot", RISCVCPU, cfg.ext_svnapot, false),
DEFINE_PROP_BOOL("svpbmt", RISCVCPU, cfg.ext_svpbmt, false),
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 6ba85e7b5d..1c2d3f7193 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -612,6 +612,36 @@ static RISCVException write_ignore(CPURISCVState *env,=
int csrno,
return RISCV_EXCP_NONE;
}
=20
+static RISCVException read_mvendorid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs =3D env_cpu(env);
+ RISCVCPU *cpu =3D RISCV_CPU(cs);
+
+ *val =3D cpu->cfg.mvendorid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_marchid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs =3D env_cpu(env);
+ RISCVCPU *cpu =3D RISCV_CPU(cs);
+
+ *val =3D cpu->cfg.marchid;
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_mipid(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ CPUState *cs =3D env_cpu(env);
+ RISCVCPU *cpu =3D RISCV_CPU(cs);
+
+ *val =3D cpu->cfg.mipid;
+ return RISCV_EXCP_NONE;
+}
+
static RISCVException read_mhartid(CPURISCVState *env, int csrno,
target_ulong *val)
{
@@ -3260,10 +3290,10 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] =3D {
[CSR_MINSTRETH] =3D { "minstreth", any32, read_instreth },
=20
/* Machine Information Registers */
- [CSR_MVENDORID] =3D { "mvendorid", any, read_zero },
- [CSR_MARCHID] =3D { "marchid", any, read_zero },
- [CSR_MIMPID] =3D { "mimpid", any, read_zero },
- [CSR_MHARTID] =3D { "mhartid", any, read_mhartid },
+ [CSR_MVENDORID] =3D { "mvendorid", any, read_mvendorid },
+ [CSR_MARCHID] =3D { "marchid", any, read_marchid },
+ [CSR_MIMPID] =3D { "mimpid", any, read_mipid },
+ [CSR_MHARTID] =3D { "mhartid", any, read_mhartid },
=20
[CSR_MCONFIGPTR] =3D { "mconfigptr", any, read_zero,
.min_priv_ver =3D PRIV_VERSION_1_1=
2_0 },
--=20
2.35.1