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[2001:8b0:1d0::2]) by smtp.gmail.com with ESMTPSA id bh26-20020a05600c3d1a00b003928db85759sm130221wmb.15.2022.04.28.07.40.46 for (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 28 Apr 2022 07:40:46 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:subject:date:message-id:in-reply-to:references:mime-version :content-transfer-encoding; bh=mYyODwFcMHLdN9TkUuzBBFcMGJ14nt1LpKq9Utsp+38=; b=kw///7V2s7mfLTcZjEAa9r1DEw93Lra5NsRZn+Ik2MTM5OoWdk2lPHb5U1oaGFsfs+ AG6dt1OSfMFbEKh8UKeXrhzlomjXvnDSmuDD7nvUvJ7iD5fdBspbbHqn0APUAldTM1Vu tR/Uo5Z9lErhQM5IqZDmwNu2k6opW9nkPRhz0mCG+A11vabAAz9WhHhuA/Uf5JWzsnmz SNJIQerXDNWyeUCfEJPRJHqIYADRxUdFI73kAw4YQw53hcVxIYFsCc5SL15gcUHFof5s UHVdHZgKjPVoUxU0gfdatWPTyBPQHdUHV1yZ1cyIIISIImRirxvdk/5wfvTJobP1Yy5N mQzg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=mYyODwFcMHLdN9TkUuzBBFcMGJ14nt1LpKq9Utsp+38=; b=MzRL2XtGZmBnLdTcBAtML9cAnQI+NtPvwVHKQiy+VPvQS6nMbdkullpA+uewPn32c0 tBBylqUeNs/8vgWdX/iNZEmJ26vEdESwL9ptG+wZqL6kMqDx9Cnp5lkWM/6XMo9kaATc HeBJakY2cuT2t/dJ8h5mBrWiH8DXIRIf9pESXVvG/jA/sWAblIdG1G89F8k6DZKEsyrW ZQT7bJv9TAzSVp/4Q6ADL1znIJjV9lOgXy5RRwBnMReO01/yIjvjhka/5zUMchdMhl8D CZcAGG7lNTllcKYWT6pVQ6R5NmJLHtswIzfw/LZP7kUQxe1D9YeSJHKux3jJ8Tuo8oXv CH4g== X-Gm-Message-State: AOAM5315LknYoIaJmktyXZLYh4krQErAlkDT3USgE9mqnm1K3vQPgN5S 4ozs5RO0Gp2KuzCr27vtPryp/+SblKIKKQ== X-Google-Smtp-Source: ABdhPJyZNvADBvFlcI6Fj+RxM4NMUALAIdXWSq+MECO69BnL3E/dSAF65k5pMT63YoMTee+qoLq9OQ== X-Received: by 2002:a5d:6d89:0:b0:20a:9beb:9477 with SMTP id l9-20020a5d6d89000000b0020a9beb9477mr26265827wrs.142.1651156847083; Thu, 28 Apr 2022 07:40:47 -0700 (PDT) From: Peter Maydell To: qemu-devel@nongnu.org Subject: [PULL 49/54] target/arm: Use field names for accessing DBGWCRn Date: Thu, 28 Apr 2022 15:39:53 +0100 Message-Id: <20220428143958.2451229-50-peter.maydell@linaro.org> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20220428143958.2451229-1-peter.maydell@linaro.org> References: <20220428143958.2451229-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2a00:1450:4864:20::434; envelope-from=peter.maydell@linaro.org; helo=mail-wr1-x434.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1651159248059100001 From: Richard Henderson While defining these names, use the correct field width of 5 not 4 for DBGWCR.MASK. This typo prevented setting a watchpoint larger than 32k. Reported-by: Chris Howard Signed-off-by: Richard Henderson Reviewed-by: Alex Benn=C3=A9e Message-id: 20220427051926.295223-1-richard.henderson@linaro.org Signed-off-by: Peter Maydell --- target/arm/internals.h | 12 ++++++++++++ target/arm/debug_helper.c | 10 +++++----- target/arm/helper.c | 8 ++++---- target/arm/kvm64.c | 14 +++++++------- 4 files changed, 28 insertions(+), 16 deletions(-) diff --git a/target/arm/internals.h b/target/arm/internals.h index 9556e3b29e4..255833479d4 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -81,6 +81,18 @@ FIELD(V7M_EXCRET, RES1, 7, 25) /* including the must-be-= 1 prefix */ */ #define FNC_RETURN_MIN_MAGIC 0xfefffffe =20 +/* Bit definitions for DBGWCRn and DBGWCRn_EL1 */ +FIELD(DBGWCR, E, 0, 1) +FIELD(DBGWCR, PAC, 1, 2) +FIELD(DBGWCR, LSC, 3, 2) +FIELD(DBGWCR, BAS, 5, 8) +FIELD(DBGWCR, HMC, 13, 1) +FIELD(DBGWCR, SSC, 14, 2) +FIELD(DBGWCR, LBN, 16, 4) +FIELD(DBGWCR, WT, 20, 1) +FIELD(DBGWCR, MASK, 24, 5) +FIELD(DBGWCR, SSCE, 29, 1) + /* We use a few fake FSR values for internal purposes in M profile. * M profile cores don't have A/R format FSRs, but currently our * get_phys_addr() code assumes A/R profile and reports failures via diff --git a/target/arm/debug_helper.c b/target/arm/debug_helper.c index 32f3caec238..46893697cc7 100644 --- a/target/arm/debug_helper.c +++ b/target/arm/debug_helper.c @@ -143,9 +143,9 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_w= p) * Non-Secure to simplify the code slightly compared to the full * table in the ARM ARM. */ - pac =3D extract64(cr, 1, 2); - hmc =3D extract64(cr, 13, 1); - ssc =3D extract64(cr, 14, 2); + pac =3D FIELD_EX64(cr, DBGWCR, PAC); + hmc =3D FIELD_EX64(cr, DBGWCR, HMC); + ssc =3D FIELD_EX64(cr, DBGWCR, SSC); =20 switch (ssc) { case 0: @@ -184,8 +184,8 @@ static bool bp_wp_matches(ARMCPU *cpu, int n, bool is_w= p) g_assert_not_reached(); } =20 - wt =3D extract64(cr, 20, 1); - lbn =3D extract64(cr, 16, 4); + wt =3D FIELD_EX64(cr, DBGWCR, WT); + lbn =3D FIELD_EX64(cr, DBGWCR, LBN); =20 if (wt && !linked_bp_matches(cpu, lbn)) { return false; diff --git a/target/arm/helper.c b/target/arm/helper.c index 63397bbac1d..5a244c3ed93 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -6320,12 +6320,12 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) env->cpu_watchpoint[n] =3D NULL; } =20 - if (!extract64(wcr, 0, 1)) { + if (!FIELD_EX64(wcr, DBGWCR, E)) { /* E bit clear : watchpoint disabled */ return; } =20 - switch (extract64(wcr, 3, 2)) { + switch (FIELD_EX64(wcr, DBGWCR, LSC)) { case 0: /* LSC 00 is reserved and must behave as if the wp is disabled */ return; @@ -6344,7 +6344,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) * CONSTRAINED UNPREDICTABLE; we opt to ignore BAS in this case, * thus generating a watchpoint for every byte in the masked region. */ - mask =3D extract64(wcr, 24, 4); + mask =3D FIELD_EX64(wcr, DBGWCR, MASK); if (mask =3D=3D 1 || mask =3D=3D 2) { /* Reserved values of MASK; we must act as if the mask value was * some non-reserved value, or as if the watchpoint were disabled. @@ -6361,7 +6361,7 @@ void hw_watchpoint_update(ARMCPU *cpu, int n) wvr &=3D ~(len - 1); } else { /* Watchpoint covers bytes defined by the byte address select bits= */ - int bas =3D extract64(wcr, 5, 8); + int bas =3D FIELD_EX64(wcr, DBGWCR, BAS); int basstart; =20 if (extract64(wvr, 2, 1)) { diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 17dd2f77d9f..b8cfaf5782a 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -208,7 +208,7 @@ static int insert_hw_watchpoint(target_ulong addr, target_ulong len, int type) { HWWatchpoint wp =3D { - .wcr =3D 1, /* E=3D1, enable */ + .wcr =3D R_DBGWCR_E_MASK, /* E=3D1, enable */ .wvr =3D addr & (~0x7ULL), .details =3D { .vaddr =3D addr, .len =3D len } }; @@ -221,19 +221,19 @@ static int insert_hw_watchpoint(target_ulong addr, * HMC=3D0 SSC=3D0 PAC=3D3 will hit EL0 or EL1, any security state, * valid whether EL3 is implemented or not */ - wp.wcr =3D deposit32(wp.wcr, 1, 2, 3); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, PAC, 3); =20 switch (type) { case GDB_WATCHPOINT_READ: - wp.wcr =3D deposit32(wp.wcr, 3, 2, 1); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 1); wp.details.flags =3D BP_MEM_READ; break; case GDB_WATCHPOINT_WRITE: - wp.wcr =3D deposit32(wp.wcr, 3, 2, 2); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 2); wp.details.flags =3D BP_MEM_WRITE; break; case GDB_WATCHPOINT_ACCESS: - wp.wcr =3D deposit32(wp.wcr, 3, 2, 3); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, LSC, 3); wp.details.flags =3D BP_MEM_ACCESS; break; default: @@ -252,8 +252,8 @@ static int insert_hw_watchpoint(target_ulong addr, int bits =3D ctz64(len); =20 wp.wvr &=3D ~((1 << bits) - 1); - wp.wcr =3D deposit32(wp.wcr, 24, 4, bits); - wp.wcr =3D deposit32(wp.wcr, 5, 8, 0xff); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, MASK, bits); + wp.wcr =3D FIELD_DP64(wp.wcr, DBGWCR, BAS, 0xff); } else { return -ENOBUFS; } --=20 2.25.1