From nobody Mon Feb 9 14:01:46 2026 Delivered-To: importer@patchew.org Authentication-Results: mx.zohomail.com; dkim=fail; spf=pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) smtp.mailfrom=qemu-devel-bounces+importer=patchew.org@nongnu.org Return-Path: Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) by mx.zohomail.com with SMTPS id 1651050589331253.23597361255884; Wed, 27 Apr 2022 02:09:49 -0700 (PDT) Received: from localhost ([::1]:47752 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1njdgC-0001kK-0X for importer@patchew.org; Wed, 27 Apr 2022 05:09:48 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:39086) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njdY6-00065N-98; Wed, 27 Apr 2022 05:01:26 -0400 Received: from beetle.greensocs.com ([5.135.226.135]:35016) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1njdY3-00024i-Ec; Wed, 27 Apr 2022 05:01:25 -0400 Received: from crumble.bar.greensocs.com (unknown [172.17.10.6]) by beetle.greensocs.com (Postfix) with ESMTPS id 746E72077F; Wed, 27 Apr 2022 09:01:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=greensocs.com; s=mail; t=1651050080; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding; bh=vTuy2Q3HKMxmWp0VRYSAap4dqyjc1PqEPVf4LD5lV0g=; b=m/++t9BjlWk2HE9MwQCl3oYY4kSxAixJyTANJ2JCU3yxHNtT8TW4zS2i0Tg6XWzvkHcnQt zNT3YPkwokDwrs2I2iZ3PKe9fupQ8TE/P8omUCSu6N2fq986EVYAGMLpoZHMbr9GGumEl0 Y/uH8D55jfuBnCPBALeak97xZCo3yf0= From: Damien Hedde To: qemu-devel@nongnu.org Subject: [PATCH v2] target/arm: Disable cryptographic instructions when neon is disabled Date: Wed, 27 Apr 2022 11:01:17 +0200 Message-Id: <20220427090117.6954-1-damien.hedde@greensocs.com> X-Mailer: git-send-email 2.35.1 MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=5.135.226.135; envelope-from=damien.hedde@greensocs.com; helo=beetle.greensocs.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Damien Hedde , Peter Maydell , "open list:ARM TCG CPUs" , richard.henderson@linaro.org Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: fail (Header signature does not verify) X-ZM-MESSAGEID: 1651050592349100001 Content-Type: text/plain; charset="utf-8" As of now, cryptographic instructions ISAR fields are never cleared so we can end up with a cpu with cryptographic instructions but no floating-point/neon instructions which is not a possible configuration according to ARM specifications. In QEMU, we have 3 kinds of cpus regarding cryptographic instructions: + no support + cortex-a57/a72: cryptographic extension is optional, floating-point/neon is not. + cortex-a53: crytographic extension is optional as well as floationg-point/neon. But cryptographic requires floating-point/neon support. Therefore we can safely clear the ISAR fields when neon is disabled. Note that other arm cpus seem to follow this. For example cortex-a55 is like cortex-a53 and cortex-a76/cortex-a710 are like cortex-a57/a72. Signed-off-by: Damien Hedde Reviewed-by: Richard Henderson --- v2: also clear SHA3 / SM3 / SM4 (Richard) --- target/arm/cpu.c | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/target/arm/cpu.c b/target/arm/cpu.c index e3f8215203..e46a766d77 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -1587,6 +1587,12 @@ static void arm_cpu_realizefn(DeviceState *dev, Erro= r **errp) unset_feature(env, ARM_FEATURE_NEON); =20 t =3D cpu->isar.id_aa64isar0; + t =3D FIELD_DP64(t, ID_AA64ISAR0, AES, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA1, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA2, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SHA3, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM3, 0); + t =3D FIELD_DP64(t, ID_AA64ISAR0, SM4, 0); t =3D FIELD_DP64(t, ID_AA64ISAR0, DP, 0); cpu->isar.id_aa64isar0 =3D t; =20 @@ -1601,6 +1607,9 @@ static void arm_cpu_realizefn(DeviceState *dev, Error= **errp) cpu->isar.id_aa64pfr0 =3D t; =20 u =3D cpu->isar.id_isar5; + u =3D FIELD_DP32(u, ID_ISAR5, AES, 0); + u =3D FIELD_DP32(u, ID_ISAR5, SHA1, 0); + u =3D FIELD_DP32(u, ID_ISAR5, SHA2, 0); u =3D FIELD_DP32(u, ID_ISAR5, RDM, 0); u =3D FIELD_DP32(u, ID_ISAR5, VCMA, 0); cpu->isar.id_isar5 =3D u; --=20 2.35.1