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([2607:fb90:27d0:b0f2:934d:3e2:9f8c:dd1]) by smtp.gmail.com with ESMTPSA id 6-20020a17090a030600b001cd4989ff5fsm6835904pje.38.2022.04.22.09.53.28 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 22 Apr 2022 09:53:29 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references :mime-version:content-transfer-encoding; bh=JmB13VTyuzzFASmlJJ9jmm7vtSLnsoUw3SQpc47Yi90=; b=D6JguGtIHsu1nGm5u0m3vA679rkzQUgoS9RDshbzSThvCdWmBFJa3vf6pvwqMzv2fu EVUcHD+j9W5awhhFYBqi6E5xjRdxSn7a8oRT2ll9pJAMiII+X6tn/Tnjad5coVOAjNTx SSwHcfEQIZJBOJ4r8ADOAcdjoIRDTzGELD3gn8JKravGbwX7YcSG6yEgSdGVsNSGdg20 gwegMDQ1YUkpMl/tDgQ39jIxfuq3Q7tGsZrn5+bu9iEx6wRQd+b+FpFHk3CkhGRb8iiy 080SdxB5U2w2kj3S1KTPs+kXVeDUTMWbZcCHQGiFs4cTaEenVjzpyX7wfPr/Y1OdtQFj OPgw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references:mime-version:content-transfer-encoding; bh=JmB13VTyuzzFASmlJJ9jmm7vtSLnsoUw3SQpc47Yi90=; b=whVrYdqiaixdEnD1oT7ezWWmjca3LWA+ZJxf//O3EdfEV/bEi9qxz35oG5p+SxcmWC CqoxB5pFzCGtLribS3wZn7e/B7sorZLe+LwhPWrGuqlR4pVgKmMTV+hLDCKlZnobKU6C IfSMWxXXOp5Se1P4jLCHZ5gcsQ9FCZpjnW9Oq9hWh1hY1o8hwLmksNHwVkHBlnn5txLi ikhScTmr0pDMwpMYK7XeOBarVva3J/6wkpq7VzqLFFv8Qo6NkJWBiCDlzaf5n0xAOo/7 j2j/sPCoZRzpm6jdKKQKkBEp58cfSErbaE97axZWhilSzCBI/A6sQU01VcRlZRuqyuhg WP2g== X-Gm-Message-State: AOAM533l+ke7h4vjN/bBArnTu07iCuBc31LLzCoYnmoxY6MT4ER+7Fqp cweyb69YFOX96cfS0j8sZj39cMP/8whjmrD+ X-Google-Smtp-Source: ABdhPJw8dlMjyu7U+iK7sABN0uwDCSro3z3UIXacc+b1j0Kzx4qEGhsUAYWfh/FDOAVU1Yy584nHOw== X-Received: by 2002:a17:902:d4ce:b0:15b:3832:dc09 with SMTP id o14-20020a170902d4ce00b0015b3832dc09mr5386830plg.168.1650646409665; Fri, 22 Apr 2022 09:53:29 -0700 (PDT) From: Richard Henderson To: qemu-devel@nongnu.org Subject: [PATCH v8 27/68] target/nios2: Use hw/registerfields.h for CR_TLBACC fields Date: Fri, 22 Apr 2022 09:51:57 -0700 Message-Id: <20220422165238.1971496-28-richard.henderson@linaro.org> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20220422165238.1971496-1-richard.henderson@linaro.org> References: <20220422165238.1971496-1-richard.henderson@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=2607:f8b0:4864:20::630; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x630.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Maydell Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZohoMail-DKIM: pass (identity @linaro.org) X-ZM-MESSAGEID: 1650646965374100001 Content-Type: text/plain; charset="utf-8" Retain the helper macros for single bit fields as aliases to the longer R_*_MASK names. Use FIELD_EX32 and FIELD_DP32 instead of manually manipulating the fields. Since we're rewriting the references to CR_TLBACC_IGN_* anyway, we correct the name of this field to IG, which is its name in the official CPU documentation. Reviewed-by: Peter Maydell Signed-off-by: Richard Henderson Message-Id: <20220421151735.31996-28-richard.henderson@linaro.org> --- target/nios2/cpu.h | 23 +++++++++++++++-------- target/nios2/mmu.c | 16 ++++++++-------- 2 files changed, 23 insertions(+), 16 deletions(-) diff --git a/target/nios2/cpu.h b/target/nios2/cpu.h index a6811ff7ea..bfa86edd97 100644 --- a/target/nios2/cpu.h +++ b/target/nios2/cpu.h @@ -115,14 +115,21 @@ FIELD(CR_PTEADDR, VPN, 2, 20) FIELD(CR_PTEADDR, PTBASE, 22, 10) =20 #define CR_TLBACC 9 -#define CR_TLBACC_IGN_SHIFT 25 -#define CR_TLBACC_IGN_MASK (0x7F << CR_TLBACC_IGN_SHIFT) -#define CR_TLBACC_C (1 << 24) -#define CR_TLBACC_R (1 << 23) -#define CR_TLBACC_W (1 << 22) -#define CR_TLBACC_X (1 << 21) -#define CR_TLBACC_G (1 << 20) -#define CR_TLBACC_PFN_MASK 0x000FFFFF + +FIELD(CR_TLBACC, PFN, 0, 20) +FIELD(CR_TLBACC, G, 20, 1) +FIELD(CR_TLBACC, X, 21, 1) +FIELD(CR_TLBACC, W, 22, 1) +FIELD(CR_TLBACC, R, 23, 1) +FIELD(CR_TLBACC, C, 24, 1) +FIELD(CR_TLBACC, IG, 25, 7) + +#define CR_TLBACC_C R_CR_TLBACC_C_MASK +#define CR_TLBACC_R R_CR_TLBACC_R_MASK +#define CR_TLBACC_W R_CR_TLBACC_W_MASK +#define CR_TLBACC_X R_CR_TLBACC_X_MASK +#define CR_TLBACC_G R_CR_TLBACC_G_MASK + #define CR_TLBMISC 10 #define CR_TLBMISC_WAY_SHIFT 20 #define CR_TLBMISC_WAY_MASK (0xF << CR_TLBMISC_WAY_SHIFT) diff --git a/target/nios2/mmu.c b/target/nios2/mmu.c index 75afc56daf..826cd2afb4 100644 --- a/target/nios2/mmu.c +++ b/target/nios2/mmu.c @@ -49,7 +49,7 @@ unsigned int mmu_translate(CPUNios2State *env, } =20 lu->vaddr =3D vaddr & TARGET_PAGE_MASK; - lu->paddr =3D (entry->data & CR_TLBACC_PFN_MASK) << TARGET_PAGE_BI= TS; + lu->paddr =3D FIELD_EX32(entry->data, CR_TLBACC, PFN) << TARGET_PA= GE_BITS; lu->prot =3D ((entry->data & CR_TLBACC_R) ? PAGE_READ : 0) | ((entry->data & CR_TLBACC_W) ? PAGE_WRITE : 0) | ((entry->data & CR_TLBACC_X) ? PAGE_EXEC : 0); @@ -86,27 +86,27 @@ void helper_mmu_write_tlbacc(CPUNios2State *env, uint32= _t v) CPUState *cs =3D env_cpu(env); Nios2CPU *cpu =3D env_archcpu(env); =20 - trace_nios2_mmu_write_tlbacc(v >> CR_TLBACC_IGN_SHIFT, + trace_nios2_mmu_write_tlbacc(FIELD_EX32(v, CR_TLBACC, IG), (v & CR_TLBACC_C) ? 'C' : '.', (v & CR_TLBACC_R) ? 'R' : '.', (v & CR_TLBACC_W) ? 'W' : '.', (v & CR_TLBACC_X) ? 'X' : '.', (v & CR_TLBACC_G) ? 'G' : '.', - v & CR_TLBACC_PFN_MASK); + FIELD_EX32(v, CR_TLBACC, PFN)); =20 /* if tlbmisc.WE =3D=3D 1 then trigger a TLB write on writes to TLBACC= */ if (env->ctrl[CR_TLBMISC] & CR_TLBMISC_WR) { int way =3D (env->ctrl[CR_TLBMISC] >> CR_TLBMISC_WAY_SHIFT); int vpn =3D FIELD_EX32(env->mmu.pteaddr_wr, CR_PTEADDR, VPN); int pid =3D (env->mmu.tlbmisc_wr & CR_TLBMISC_PID_MASK) >> 4; - int g =3D (v & CR_TLBACC_G) ? 1 : 0; - int valid =3D ((vpn & CR_TLBACC_PFN_MASK) < 0xC0000) ? 1 : 0; + int g =3D FIELD_EX32(v, CR_TLBACC, G); + int valid =3D FIELD_EX32(vpn, CR_TLBACC, PFN) < 0xC0000; Nios2TLBEntry *entry =3D &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; uint32_t newTag =3D (vpn << 12) | (g << 11) | (valid << 10) | pid; uint32_t newData =3D v & (CR_TLBACC_C | CR_TLBACC_R | CR_TLBACC_W | - CR_TLBACC_X | CR_TLBACC_PFN_MASK); + CR_TLBACC_X | R_CR_TLBACC_PFN_MASK); =20 if ((entry->tag !=3D newTag) || (entry->data !=3D newData)) { if (entry->tag & (1 << 10)) { @@ -153,7 +153,7 @@ void helper_mmu_write_tlbmisc(CPUNios2State *env, uint3= 2_t v) &env->mmu.tlb[(way * cpu->tlb_num_ways) + (vpn & env->mmu.tlb_entry_mask)]; =20 - env->ctrl[CR_TLBACC] &=3D CR_TLBACC_IGN_MASK; + env->ctrl[CR_TLBACC] &=3D R_CR_TLBACC_IG_MASK; env->ctrl[CR_TLBACC] |=3D entry->data; env->ctrl[CR_TLBACC] |=3D (entry->tag & (1 << 11)) ? CR_TLBACC_G := 0; env->ctrl[CR_TLBMISC] =3D @@ -208,7 +208,7 @@ void dump_mmu(CPUNios2State *env) entry->tag >> 12, entry->tag & ((1 << cpu->pid_num_bits) - 1), (entry->tag & (1 << 11)) ? 'G' : '-', - entry->data & CR_TLBACC_PFN_MASK, + FIELD_EX32(entry->data, CR_TLBACC, PFN), (entry->data & CR_TLBACC_C) ? 'C' : '-', (entry->data & CR_TLBACC_R) ? 'R' : '-', (entry->data & CR_TLBACC_W) ? 'W' : '-', --=20 2.34.1