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dkim=pass reason="pass (just generated, assumed good)" header.d=opensource.wdc.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d= opensource.wdc.com; h=content-transfer-encoding:mime-version :references:in-reply-to:x-mailer:message-id:date:subject:to :from; s=dkim; t=1650587909; x=1653179910; bh=HZtMfNayAzWb857EUp h0gC4EyuX8kVZF+e012B4DRfM=; b=S4Ze9QehQgaTbfFv9Zp/gBUdB1N0QjQXfG y1FcnWWvmt4YMVLn6pBjq9gt3tOT9CIAVip7QUPLzaUHc0u85DEXrZ926zjY+bGr N1YV6d05jUtJVXh3pQigAx90JQAk7ZiadUlph14KnFuXHDISienaX593DsvDxfrE 8Ep8uHePoPPr7P7H/2+FtmjJX3hMs3f/McUxTA/D6Xv/PyW/qYaEYLiHK4Gwqpb8 2VqLiTKqqu+dQUWk4kG5TPctHwBUDyS4/1rM1XZyf4uQBcp6gOk8HPs8ZLcyGwTB noW9AZBMDpgh7rh5n8Ck6CN277YIT6VGdHsiRkCLNZhkXPkgo5Ow== X-Virus-Scanned: amavisd-new at usg-ed-osssrv.wdc.com From: Alistair Francis To: qemu-devel@nongnu.org Cc: alistair23@gmail.com, Jim Shu , Frank Chang , Alistair Francis Subject: [PULL v2 24/31] hw/intc: riscv_aclint: Add reset function of ACLINT devices Date: Fri, 22 Apr 2022 10:36:49 +1000 Message-Id: <20220422003656.1648121-25-alistair.francis@opensource.wdc.com> X-Mailer: git-send-email 2.35.1 In-Reply-To: <20220422003656.1648121-1-alistair.francis@opensource.wdc.com> References: <20220422003656.1648121-1-alistair.francis@opensource.wdc.com> MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Received-SPF: pass (zohomail.com: domain of gnu.org designates 209.51.188.17 as permitted sender) client-ip=209.51.188.17; envelope-from=qemu-devel-bounces+importer=patchew.org@nongnu.org; helo=lists.gnu.org; Received-SPF: pass client-ip=68.232.141.245; envelope-from=prvs=1041ecfe3=alistair.francis@opensource.wdc.com; helo=esa1.hgst.iphmx.com X-Spam_score_int: -43 X-Spam_score: -4.4 X-Spam_bar: ---- X-Spam_report: (-4.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+importer=patchew.org@nongnu.org Sender: "Qemu-devel" X-ZM-MESSAGEID: 1650589703842100001 Content-Type: text/plain; charset="utf-8" From: Jim Shu This commit implements reset function of all ACLINT devices. ACLINT device reset will clear MTIME and MSIP register to 0. Depend on RISC-V ACLINT spec v1.0-rc4: https://github.com/riscv/riscv-aclint/blob/v1.0-rc4/riscv-aclint.adoc Signed-off-by: Jim Shu Reviewed-by: Frank Chang Reviewed-by: Alistair Francis Message-Id: <20220420080901.14655-5-frank.chang@sifive.com> Signed-off-by: Alistair Francis --- hw/intc/riscv_aclint.c | 39 +++++++++++++++++++++++++++++++++++++++ 1 file changed, 39 insertions(+) diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index 3b3ab548f6..0412edc982 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -293,11 +293,29 @@ static void riscv_aclint_mtimer_realize(DeviceState *= dev, Error **errp) } } =20 +static void riscv_aclint_mtimer_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MTIMER device reset, the MTIME register is cleared to zero. + * - On MTIMER device reset, the MTIMECMP registers are in unknown s= tate. + */ + RISCVAclintMTimerState *mtimer =3D RISCV_ACLINT_MTIMER(obj); + + /* + * Clear mtime register by writing to 0 it. + * Pending mtime interrupts will also be cleared at the same time. + */ + riscv_aclint_mtimer_write(mtimer, mtimer->time_base, 0, 8); +} + static void riscv_aclint_mtimer_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); dc->realize =3D riscv_aclint_mtimer_realize; device_class_set_props(dc, riscv_aclint_mtimer_properties); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D riscv_aclint_mtimer_reset_enter; } =20 static const TypeInfo riscv_aclint_mtimer_info =3D { @@ -452,11 +470,32 @@ static void riscv_aclint_swi_realize(DeviceState *dev= , Error **errp) } } =20 +static void riscv_aclint_swi_reset_enter(Object *obj, ResetType type) +{ + /* + * According to RISC-V ACLINT spec: + * - On MSWI device reset, each MSIP register is cleared to zero. + * + * p.s. SSWI device reset does nothing since SETSIP register always re= ads 0. + */ + RISCVAclintSwiState *swi =3D RISCV_ACLINT_SWI(obj); + int i; + + if (!swi->sswi) { + for (i =3D 0; i < swi->num_harts; i++) { + /* Clear MSIP registers by lowering software interrupts. */ + qemu_irq_lower(swi->soft_irqs[i]); + } + } +} + static void riscv_aclint_swi_class_init(ObjectClass *klass, void *data) { DeviceClass *dc =3D DEVICE_CLASS(klass); dc->realize =3D riscv_aclint_swi_realize; device_class_set_props(dc, riscv_aclint_swi_properties); + ResettableClass *rc =3D RESETTABLE_CLASS(klass); + rc->phases.enter =3D riscv_aclint_swi_reset_enter; } =20 static const TypeInfo riscv_aclint_swi_info =3D { --=20 2.35.1