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From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Subject: [PULL 03/31] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
Date: Thu, 21 Apr 2022 12:18:18 +0100
Message-Id: <20220421111846.2011565-4-peter.maydell@linaro.org>
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From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
Connect the 4 TTC timers on the ZynqMP.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
Message-id: 20220331222017.2914409-3-edgar.iglesias@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
include/hw/arm/xlnx-zynqmp.h | 4 ++++
hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 9d9a9d0bf9d..85fd9f53daa 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -41,6 +41,7 @@
#include "hw/or-irq.h"
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
#include "hw/misc/xlnx-zynqmp-crf.h"
+#include "hw/timer/cadence_ttc.h"
=20
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
=20
+#define XLNX_ZYNQMP_NUM_TTC 4
+
/*
* Unimplemented mmio regions needed to boot some images.
*/
@@ -128,6 +131,7 @@ struct XlnxZynqMPState {
qemu_or_irq qspi_irq_orgate;
XlnxZynqMPAPUCtrl apu_ctrl;
XlnxZynqMPCRF crf;
+ CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
=20
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 5bfe285a191..375309e68eb 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -68,6 +68,9 @@
#define APU_ADDR 0xfd5c0000
#define APU_IRQ 153
=20
+#define TTC0_ADDR 0xFF110000
+#define TTC0_IRQ 36
+
#define IPI_ADDR 0xFF300000
#define IPI_IRQ 64
=20
@@ -316,6 +319,24 @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s,=
qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
}
=20
+static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+ int i, irq;
+
+ for (i =3D 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
+ object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
+ TYPE_CADENCE_TTC);
+ sbd =3D SYS_BUS_DEVICE(&s->ttc[i]);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
+ for (irq =3D 0; irq < 3; irq++) {
+ sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
+ }
+ }
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -721,6 +742,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error=
**errp)
xlnx_zynqmp_create_efuse(s, gic_spi);
xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
xlnx_zynqmp_create_crf(s, gic_spi);
+ xlnx_zynqmp_create_ttc(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
=20
for (i =3D 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
--=20
2.25.1